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Author SHA1 Message Date
Konstantin Zhuravlyov 331f97e171 AMDGPU: Bring processors and features in sync with the spec 
- Remove gfx800
- Make iceland gfx802
- Add xnack to gfx902

Differential Revision: https://reviews.llvm.org/D43355

llvm-svn: 325393
 2018-02-16 21:26:25 +00:00
Dmitry Preobrazhensky 0a1ff464e1 [AMDGPU][MC] Corrected dst/data size for MIMG opcodes with d16 modifier 
See bug 36154: https://bugs.llvm.org/show_bug.cgi?id=36154

Differential Revision: https://reviews.llvm.org/D42847

Reviewers: cfang, artem.tamazov, arsenm
llvm-svn: 324237
 2018-02-05 14:18:53 +00:00
Dmitry Preobrazhensky e3271aee44 [AMDGPU][MC] Added validation of d16 and r128 modifiers of MIMG opcodes 
See bugs 36094, 36095:
  https://bugs.llvm.org/show_bug.cgi?id=36094
  https://bugs.llvm.org/show_bug.cgi?id=36095

Differential Revision: https://reviews.llvm.org/D42692

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 324231
 2018-02-05 12:45:43 +00:00
Dmitry Preobrazhensky 4f321aef74 [AMDGPU][MC] Corrected parsing of image opcode modifiers r128 and d16 
See bugs 36092, 36093:
    https://bugs.llvm.org/show_bug.cgi?id=36092
    https://bugs.llvm.org/show_bug.cgi?id=36093

Differential Revision: https://reviews.llvm.org/D42583

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 323651
 2018-01-29 14:20:42 +00:00
Dmitry Preobrazhensky 706828157f [AMDGPU][MC] Added validation of image dst/data size (must match dmask and tfe) 
See bug 36000: https://bugs.llvm.org/show_bug.cgi?id=36000

Differential Revision: https://reviews.llvm.org/D42483

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 323538
 2018-01-26 16:42:51 +00:00
Dmitry Preobrazhensky 0b4eb1ead1 [AMDGPU][MC] Added support of 64-bit image atomics 
See bug 35998: https://bugs.llvm.org/show_bug.cgi?id=35998

Differential Revision: https://reviews.llvm.org/D42469

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 323534
 2018-01-26 15:43:29 +00:00
Dmitry Preobrazhensky 0e074e349d [AMDGPU][MC] Corrected parsing of image modifiers and encoding of image atomics 
See bugs
    35962: https://bugs.llvm.org/show_bug.cgi?id=35962
    35963: https://bugs.llvm.org/show_bug.cgi?id=35963

Differential Revision: https://reviews.llvm.org/D42184

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 322942
 2018-01-19 13:49:53 +00:00
Dmitry Preobrazhensky 6b65f7c380 [AMDGPU][MC][GFX9] Enable inline constants for SDWA operands 
See bug 35771: https://bugs.llvm.org/show_bug.cgi?id=35771

Differential Revision: https://reviews.llvm.org/D42058

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 322655
 2018-01-17 14:00:48 +00:00
Stanislav Mekhanoshin 62875fcd6c [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32 
Differential Revision: https://reviews.llvm.org/D41617

llvm-svn: 322500
 2018-01-15 18:49:15 +00:00
Changpeng Fang 44dfa1de3b AMDGPU/SI: Add d16 support for buffer intrinsics. 
Differential Revision:
  https://reviews.llvm.org/D38906

Reviewers:
  Matt and Brian.

llvm-svn: 322402
 2018-01-12 21:12:19 +00:00
Dmitry Preobrazhensky 3afbd825a3 [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support 
See bug 35764: https://bugs.llvm.org/show_bug.cgi?id=35764

Differential Revision: https://reviews.llvm.org/D41614

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 322189
 2018-01-10 14:22:19 +00:00
Dmitry Preobrazhensky 414e05383f [AMDGPU][MC] Incorrect parsing of flat/global atomic modifiers 
See bug 35730: https://bugs.llvm.org/show_bug.cgi?id=35730

Differential Revision: https://reviews.llvm.org/D41598

Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 321552
 2017-12-29 13:55:11 +00:00
Dmitry Preobrazhensky 471adf7fdc [AMDGPU][MC] Corrected handling of negative expressions 
See bug 35716: https://bugs.llvm.org/show_bug.cgi?id=35716

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D41488

llvm-svn: 321372
 2017-12-22 18:03:35 +00:00
Dmitry Preobrazhensky c5b0c172f6 [AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32 
See bug 35645: https://bugs.llvm.org/show_bug.cgi?id=35645

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D41186

llvm-svn: 321367
 2017-12-22 17:13:28 +00:00
Dmitry Preobrazhensky 2713495318 [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers 
See bug 35561: https://bugs.llvm.org/show_bug.cgi?id=35561

This patch also affects implementation of SGPR and VGPR registers though changes are cosmetic.

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D41437

llvm-svn: 321359
 2017-12-22 15:18:06 +00:00
Matt Arsenault f7f59b5292 [AMDGPU, AsmParser] Enable the mnemonic spell corrector. 
Patch by Dmitry Venikov

llvm-svn: 321202
 2017-12-20 18:52:57 +00:00
Dmitry Preobrazhensky ac2b02643b [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma 
See bugs 35494 and 35559:
https://bugs.llvm.org/show_bug.cgi?id=35494
https://bugs.llvm.org/show_bug.cgi?id=35559

Reviewers: vpykhtin, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D41007

llvm-svn: 320375
 2017-12-11 15:23:20 +00:00
Konstantin Zhuravlyov c40d9f2e5d AMDGPU/GCN: Bring processors in sync with AMDGPUUsage 
- Add gfx704
    - Change bonaire to gfx704
  - Remove gfx804
  - Remove gfx901
  - Remove gfx903

Differential Revision: https://reviews.llvm.org/D40046

llvm-svn: 320194
 2017-12-08 20:52:28 +00:00
Konstantin Zhuravlyov 06ae4ec78e AMDGPU: Add num spilled s/vgprs to metadata 
This was requested by tools.

Differential Revision: https://reviews.llvm.org/D40321

llvm-svn: 319192
 2017-11-28 17:51:08 +00:00
Dmitry Preobrazhensky 0e8924a5c7 [AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16 
See bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629

Reviewers: artem.tamazov, SamWot, arsenm

Differential Revision: https://reviews.llvm.org/D39488

llvm-svn: 318955
 2017-11-24 15:37:14 +00:00
Dmitry Preobrazhensky dd2f1c993e [AMDGPU][MC][GFX9] Added support of 'inst_offset' modifier for compatibility with SP3 
See bug 35329: https://bugs.llvm.org//show_bug.cgi?id=35329

Reviewers: arsenm, vpykhtin, artem.tamazov

Differential Revision: https://reviews.llvm.org/D40350

llvm-svn: 318947
 2017-11-24 13:22:38 +00:00
Dmitry Preobrazhensky c492500e7e [AMDGPU][mc][tests] Updated generated lit tests for GFX8/9 
Summary:
Added tests to better cover features introduced by commit rL318675.
See http://llvm.org/viewvc/llvm-project?view=revision&revision=318675

llvm-svn: 318841
 2017-11-22 15:47:27 +00:00
Dmitry Preobrazhensky a0342dc9eb [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev} 
See bug 34765: https://bugs.llvm.org//show_bug.cgi?id=34765

Reviewers: tamazov, SamWot, arsenm, vpykhtin

Differential Revision: https://reviews.llvm.org/D40088

llvm-svn: 318675
 2017-11-20 18:24:21 +00:00
Dmitry Preobrazhensky 682a654758 [AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix* 
See bug 35148: https://bugs.llvm.org//show_bug.cgi?id=35148

Reviewers: tamazov, SamWot, arsenm

Differential Revision: https://reviews.llvm.org/D39492

llvm-svn: 318526
 2017-11-17 15:15:40 +00:00
Konstantin Zhuravlyov 8d5e9e110c AMDGPU: Rename MaxFlatWorkgroupSize to MaxFlatWorkGroupSize for consistency 
Differential Revision: https://reviews.llvm.org/D38957

llvm-svn: 316097
 2017-10-18 17:31:09 +00:00
Konstantin Zhuravlyov 7dabe9ced7 AMDGPU: Start generating metadata for MaxFlatWorkGroupSize 
Differential Revision: https://reviews.llvm.org/D38958

llvm-svn: 316024
 2017-10-17 20:03:21 +00:00
Konstantin Zhuravlyov a01d8b0b63 AMDGPU: Bring HSA metadata on par with the specification 
Differential Revision: https://reviews.llvm.org/D38753

llvm-svn: 315821
 2017-10-14 19:03:51 +00:00
Konstantin Zhuravlyov 219066bab8 AMDGPU: Improve note directive verification in assembler 
- Do not allow amd_amdgpu_isa directives on non-amdgcn architectures
  - Do not allow amd_amdgpu_hsa_metadata on non-amdhsa OSes
  - Do not allow amd_amdgpu_pal_metadata on non-amdpal OSes

Differential Revision: https://reviews.llvm.org/D38750

llvm-svn: 315812
 2017-10-14 16:15:28 +00:00
Konstantin Zhuravlyov eda425edd4 AMDGPU: Do not emit deprecated notes for code object v3 
Differential Revision: https://reviews.llvm.org/D38749

llvm-svn: 315810
 2017-10-14 15:59:07 +00:00
Konstantin Zhuravlyov 9c05b2bc3b AMDGPU: Add support for isa version note 
- Emit NT_AMD_AMDGPU_ISA
  - Add assembler parsing for isa version directive
    - If isa version directive does not match command line arguments, then return error

Differential Revision: https://reviews.llvm.org/D38748

llvm-svn: 315808
 2017-10-14 15:40:33 +00:00
Konstantin Zhuravlyov c3beb6a075 AMDGPU/NFC: Minor clean ups in PAL metadata 
- Move PAL metadata definitions to AMDGPUMetadata
  - Make naming consistent with HSA metadata

Differential Revision: https://reviews.llvm.org/D38745

llvm-svn: 315523
 2017-10-11 22:41:09 +00:00
Konstantin Zhuravlyov a63b0f9d20 AMDGPU/NFC: Rename code object metadata as HSA metadata 
- Rename AMDGPUCodeObjectMetadata to AMDGPUMetadata (PAL metadata will be included in this file in the follow up change)
  - Rename AMDGPUCodeObjectMetadataStreamer to AMDGPUHSAMetadataStreamer
  - Introduce HSAMD namespace
  - Other minor name changes in function and test names

llvm-svn: 315522
 2017-10-11 22:18:53 +00:00
Tim Renouf 72800f0436 [AMDGPU] implemented pal metadata 
Summary:
For the amdpal OS type:

We write an AMDGPU_PAL_METADATA record in the .note section in the ELF
(or as an assembler directive). It contains key=value pairs of 32 bit
ints. It is a merge of metadata from codegen of the shaders, and
metadata provided by the frontend as _amdgpu_pal_metadata IR metadata.
Where both sources have a key=value with the same key, the two values
are ORed together.

This .note record is part of the amdpal ABI and will be documented in
docs/AMDGPUUsage.rst in a future commit.

Eventually the amdpal OS type will stop generating the .AMDGPU.config
section once the frontend has safely moved over to using the .note
records above instead of .AMDGPU.config.

Reviewers: arsenm, nhaehnle, dstuttard

Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D37753

llvm-svn: 314829
 2017-10-03 19:03:52 +00:00
Nicolai Haehnle c2e79c2dfc AMDGPU: fix bad test exposed by r314522 
The test attempts to use -1 as carry-in for v_addc_*.

Before writing r314522, I did actually test this on real hardware,
and found that it doesn't work. So r314522 is correct in restricting
the carry-in operand: just remove those tests to make things pass
again.

llvm-svn: 314530
 2017-09-29 16:07:05 +00:00
Matt Arsenault 644883ff07 AMDGPU: Fix encoding of op_sel for mad_mix* opcodes 
llvm-svn: 313797
 2017-09-20 19:09:28 +00:00
Matt Arsenault efa1d655d4 AMDGPU: Add ds_{read|write}_addtid_b32 definitions 
llvm-svn: 312349
 2017-09-01 18:38:02 +00:00
Matt Arsenault ed6e8f0a90 AMDGPU: Add most d16 load/store instruction definitions 
Doesn't include the tied operand necessary for the loads,
but is enough for the assembler to work.

llvm-svn: 312347
 2017-09-01 18:36:06 +00:00
Matt Arsenault c8f8cda0cd AMDGPU: Correct operand types for v_mad_mix* 
These aren't really packed instructions, so the default
op_sel_hi should be 0 since this indicates a conversion.
The operand types are scalar values that behave similar
to an f16 scalar that may be converted to f32.

Doesn't change the default printing for op_sel_hi, just
the parsing.

llvm-svn: 312179
 2017-08-30 22:18:40 +00:00
Dmitry Preobrazhensky b865ef534a [AMDGPU][MC][GFX9] Added op_sel support for v_mad_*16, v_fma_f16, v_div_fixup_f16 
This change implements features postponed in https://reviews.llvm.org/D35424 because of a dependency on https://reviews.llvm.org/D36322

Reviewers: SamWot, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D36694

llvm-svn: 311011
 2017-08-16 15:16:32 +00:00
Dmitry Preobrazhensky ff64aa514b [AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodes 
See Bug 34152: https://bugs.llvm.org//show_bug.cgi?id=34152

Reviewers: SamWot, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D36674

llvm-svn: 311006
 2017-08-16 13:51:56 +00:00
Dmitry Preobrazhensky 1e32550de6 [AMDGPU][MC][GFX9] Added 16-bit renamed and "_legacy" VALU opcodes 
See Bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629

Reviewers: vpykhtin, SamWot, arsenm

Differential Revision: https://reviews.llvm.org/D36322

llvm-svn: 310497
 2017-08-09 17:10:47 +00:00
Matt Arsenault 36b4b0bed7 AMDGPU: Remove -mcpu=SI 
Leftover from before amdgcn/r600 split.

llvm-svn: 310277
 2017-08-07 18:30:35 +00:00
Dmitry Preobrazhensky 50805a0b83 [AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VI 
See bug 32621: https://bugs.llvm.org//show_bug.cgi?id=32621

Reviewers: vpykhtin, SamWot, arsenm

Differential Revision: https://reviews.llvm.org/D35902

llvm-svn: 310251
 2017-08-07 13:14:12 +00:00
Dmitry Preobrazhensky 4b11a78a6e [AMDGPU][MC] Enabled expressions as operands 
See bug 33579: https://bugs.llvm.org//show_bug.cgi?id=33579

Reviewers: vpykhtin, SamWot, arsenm

Differential Revision: https://reviews.llvm.org/D36091

llvm-svn: 310059
 2017-08-04 13:55:24 +00:00
Matt Arsenault ca7b0a1777 AMDGPU: Add instruction definitions for some scratch_* instructions 
Omit atomics for now since they probably aren't useful.

llvm-svn: 308747
 2017-07-21 15:36:16 +00:00
Dmitry Preobrazhensky abf2839478 [AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifier 
See bug 33591: https://bugs.llvm.org//show_bug.cgi?id=33591

Reviewers: vpykhtin, artem.tamazov, SamWot, arsenm

Differential Revision: https://reviews.llvm.org/D35424

llvm-svn: 308740
 2017-07-21 13:54:11 +00:00
Matt Arsenault c37fe66ec5 AMDGPU: Add encoding for carryless add/sub instructions 
llvm-svn: 308639
 2017-07-20 17:42:47 +00:00
Matt Arsenault f65c5ac9c9 AMDGPU: Add encodings for global atomics 
llvm-svn: 308638
 2017-07-20 17:31:56 +00:00
Matt Arsenault 04004716ff AMDGPU: Correct encoding for global instructions 
The soffset field needs to be be set to 0x7f to disable it,
not 0. 0 is interpreted as an SGPR offset.

This should be enough to get basic usage of the global instructions
working. Technically it is possible to use an SGPR_32 offset,
but I'm not sure if it's correct with 64-bit pointers, but
that is not handled now. This should also be cleaned up
to be more similar to how different MUBUF modes are handled,
and to have InstrMappings between the different types.

llvm-svn: 308583
 2017-07-20 05:17:54 +00:00
Sam Kolton 4685b70a77 [AMDGPU] resubmit r308179: CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions 
llvm-svn: 308310
 2017-07-18 14:23:26 +00:00
Dmitry Preobrazhensky 095ec3da81 [AMDGPU][MC] Added missing VOP3P opcodes 
Added support of the following opcodes:
  v_pk_sub_u16
  v_pk_mad_i16
  v_pk_mad_u16

See Bug 33593: https://bugs.llvm.org//show_bug.cgi?id=33593

Reviewers: vpykhtin, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D34890

llvm-svn: 308281
 2017-07-18 09:24:10 +00:00
Chandler Carruth 9a7442d088 Revert r308179 which causes tablegen to spam stderr on every build. 
Original commit log:
[AMDGPU] CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions

llvm-svn: 308270
 2017-07-18 07:40:47 +00:00
Sam Kolton a2b9e2f755 [AMDGPU] CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions 
Summary:
Previously, CodeGen checked first src operand type to determine if omod is supported by instruction. This isn't correct for some instructions: e.g. V_CMP_EQ_F32 has floating-point src operands but desn't support omod.
Changed .td files to check if dst operand instead of src operand.

Reviewers: arsenm, vpykhtin

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D35350

llvm-svn: 308179
 2017-07-17 14:23:38 +00:00
Dmitry Preobrazhensky b2d24e23ce [AMDGPU][mc][gfx9] Added support of op_sel/op_sel_hi for V_MAD_MIX* 
See https://bugs.llvm.org//show_bug.cgi?id=33595

Reviewers: vpykhtin, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D35021

llvm-svn: 307402
 2017-07-07 14:29:06 +00:00
Richard Smith d0c0c13447 Fix ODR violations due to abuse of LLVM_YAML_IS_(FLOW_)?SEQUENCE_VECTOR 
This is a short-term fix for PR33650 aimed to get the modules build bots green again.

Remove all the places where we use the LLVM_YAML_IS_(FLOW_)?SEQUENCE_VECTOR
macros to try to locally specialize a global template for a global type. That's
not how C++ works.

Instead, we now centrally define how to format vectors of fundamental types and
of string (std::string and StringRef). We use flow formatting for the former
cases, since that's the obvious right thing to do; in the latter case, it's
less clear what the right choice is, but flow formatting is really bad for some
cases (due to very long strings), so we pick block formatting. (Many of the
cases that were using flow formatting for strings are improved by this change.)

Other than the flow -> block formatting change for some vectors of strings,
this should result in no functionality change.

Differential Revision: https://reviews.llvm.org/D34907

Corresponding updates to clang, clang-tools-extra, and lld to follow.

llvm-svn: 306878
 2017-06-30 20:56:57 +00:00
David Stuttard 70e8bc1bf3 [AMDGPU] Add intrinsics for tbuffer load and store 
Intrinsic already existed for llvm.SI.tbuffer.store

Needed tbuffer.load and also re-implementing the intrinsic as llvm.amdgcn.tbuffer.*

Added CodeGen tests for the 2 new variants added.
Left the original llvm.SI.tbuffer.store implementation to avoid issues with existing code

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, tpr

Differential Revision: https://reviews.llvm.org/D30687

llvm-svn: 306031
 2017-06-22 16:29:22 +00:00
Dmitry Preobrazhensky dc4ac823ec [AMDGPU][MC] Corrected V_*QSAD* instructions to check that dest register is different than any of the src 
See Bug 33279: https://bugs.llvm.org//show_bug.cgi?id=33279

Reviewers: artem.tamazov, vpykhtin

Differential Revision: https://reviews.llvm.org/D34003

llvm-svn: 305915
 2017-06-21 14:41:34 +00:00
Matt Arsenault 9698f1c862 AMDGPU: Start adding global_* instructions 
llvm-svn: 305838
 2017-06-20 19:54:14 +00:00
Artem Tamazov 314eafb73d [AMDGPU][mc][tests][NFC] Bulk ISA tests: Massive update. Add Gfx9 dasm tests. 
A new Gfx9 dasm test added with approx 29000 cases.
Existing tests extended by (approx.):
* Gfx7 asm: 5000 test cases
* Gfx8 asm: 5000 test cases
* Gfx9 asm: 14400 test cases
* Gfx8 dasm: 5200 test cases

llvm-svn: 305702
 2017-06-19 15:55:02 +00:00
Matt Arsenault fd02314113 AMDGPU: Start adding offset fields to flat instructions 
llvm-svn: 305194
 2017-06-12 15:55:58 +00:00
Wei Ding 7c3e5115a5 AMDGPU : Fix ISA Version Definitions. 
Differential Revision: http://reviews.llvm.org/D28531

llvm-svn: 305137
 2017-06-10 03:53:19 +00:00
Dmitry Preobrazhensky 5a2f881b39 [AMDGPU][MC] Corrected error message for s_waitcnt helpers 
See Bug 32711: https://bugs.llvm.org//show_bug.cgi?id=32711

Reviewers: artem.tamazov

Differential Revision: https://reviews.llvm.org/D33781

llvm-svn: 304922
 2017-06-07 16:08:02 +00:00
Dmitry Preobrazhensky 793c592652 [AMDGPU][MC] New syntax for ds_swizzle_b32 offset 
See Bug 28601: https://bugs.llvm.org//show_bug.cgi?id=28601

Reviewers: artem.tamazov, vpykhtin

Differential Revision: https://reviews.llvm.org/D33542

llvm-svn: 304309
 2017-05-31 16:26:47 +00:00
Dmitry Preobrazhensky 6a2431df0b [AMDGPU][MC][GFX9] Corrected encoding of flat_scratch* for SDWA opcodes 
See bug 33171: https://bugs.llvm.org/show_bug.cgi?id=33171

Reviewers: Sam Kolton

Differential Revision: https://reviews.llvm.org/D33553

llvm-svn: 304015
 2017-05-26 18:01:29 +00:00
Sam Kolton f7659d71eb [AMDGPU] SDWA: Add assembler support for GFX9 
Summary:
Added separate pseudo and real instruction for GFX9 SDWA instructions.
Currently supports only in assembler.
Depends D32493

Reviewers: vpykhtin, artem.tamazov

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D33132

llvm-svn: 303620
 2017-05-23 10:08:55 +00:00
Dmitry Preobrazhensky 9321e8fcec [AMDGPU][MC] Fixed bugs in export instruction 
See Bugs 33019, 33056:
  https://bugs.llvm.org//show_bug.cgi?id=33019
  https://bugs.llvm.org//show_bug.cgi?id=33056

Reviewers: artem.tamazov, vpykhtin

Differential Revision: https://reviews.llvm.org/D33288

llvm-svn: 303423
 2017-05-19 13:36:09 +00:00
Matt Arsenault ee324ffc1f AMDGPU: Fix min3/max3 combines for f16/i16 
Fix missing instruction definitions for min3/max3.

llvm-svn: 303284
 2017-05-17 19:25:06 +00:00
Dmitry Preobrazhensky 167f8b69e3 [AMDGPU][MC] Corrected several VI opcodes to avoid printing _e64 
See bug 32936: https://bugs.llvm.org//show_bug.cgi?id=32936

Reviewers: artem.tamazov, vpykhtin

Differential Revision: https://reviews.llvm.org/D33123

llvm-svn: 303070
 2017-05-15 14:28:23 +00:00
Matt Arsenault 47ccafe787 AMDGPU: Remove tfe bit from flat instruction definitions 
We don't use it and it was removed in gfx9, and the encoding
bit repurposed.

Additionally actually using it requires changing the output register
class, which wasn't done anyway.

llvm-svn: 302814
 2017-05-11 17:38:33 +00:00
Dmitry Preobrazhensky da61a7f9ef [AMDGPU][MC] Corrected v_madak/madmk to avoid printing "_e32" in disassembler output 
See bug 32927: https://bugs.llvm.org//show_bug.cgi?id=32927

Reviewers: vpykhtin, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D32913

llvm-svn: 302648
 2017-05-10 13:00:28 +00:00
Sam Kolton 5d99386b4d [AMDGPU] DPP: add support for GFX9 
Reviewers: artem.tamazov

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D32588

llvm-svn: 301551
 2017-04-27 15:42:38 +00:00
Dmitry Preobrazhensky 43d297eb45 [AMDGPU][MC] Added arg checks for vmcnt, expcnt, lgkmcnt helpers 
Summary of changes:
- corrected vmcnt, expcnt, lgkmcnt helpers to checks their argument for truncation;
- added saturated versions of these helpers.

See bug 32711 for details: https://bugs.llvm.org//show_bug.cgi?id=32711

Reviewers: artem.tamazov, vpykhtin

Differential Revision: https://reviews.llvm.org/D32546

llvm-svn: 301439
 2017-04-26 17:55:50 +00:00
Dmitry Preobrazhensky c7d35a0d6a [AMDGPU][MC] Added check for truncation of SOPK imm operand 
See bug 30827: https://bugs.llvm.org//show_bug.cgi?id=30827

Reviewers: artem.tamazov, vpykhtin

Differential Revision: https://reviews.llvm.org/D32535

llvm-svn: 301418
 2017-04-26 15:34:19 +00:00
Artem Tamazov d6656b945e [AMDGPU][mc][tests][NFC] Bulk ISA tests: update for Gfx7/Gfx8, add for Gfx9. 
llvm-svn: 301247
 2017-04-24 20:42:27 +00:00
Artem Tamazov 557a057d4f [AMDGPU][mc][tests][NFC] Update bulk ISA tests for Gfx7 and Gfx8 
Added approx. 1100 gfx7 and 1040 gfx8 test cases.

llvm-svn: 300734
 2017-04-19 19:12:06 +00:00
Dmitry Preobrazhensky e6ef099dcd [AMDGPU][MC] Corrected ds_write_src2_* to require one offset instead of two. 
Fixed bug 32551: https://bugs.llvm.org//show_bug.cgi?id=32551

Reviewers: vpykhtin

Differential Revision: https://reviews.llvm.org/D31809

llvm-svn: 300319
 2017-04-14 12:28:07 +00:00
Dmitry Preobrazhensky 5714860ee4 [AMDGPU][MC] Enabled constants for src operands of s_cbranch_g_fork 
Fixed bug 32619: https://bugs.llvm.org//show_bug.cgi?id=32619

Reviewers: artem.tamazov, vpykhtin

Differential Revision: https://reviews.llvm.org/D31973

llvm-svn: 300318
 2017-04-14 11:52:26 +00:00
Dmitry Preobrazhensky 14104e0d0f [AMDGPU][MC] Added support for several VI-specific opcodes (s_wakeup, etc) 
Added support for VI:

- s_endpgm_saved
- s_wakeup
- s_rfe_restore_b64
- v_perm_b32

Enabled for VI:

- v_mov_fed_b32
- v_mov_fed_b32_e64

See bug 32593: https://bugs.llvm.org//show_bug.cgi?id=32593

Reviewers: artem.tamazov, vpykhtin

Differential Revision: https://reviews.llvm.org/D31931

llvm-svn: 300076
 2017-04-12 17:10:07 +00:00
Dmitry Preobrazhensky 5ac9fd64a3 [AMDGPU][MC] Corrected parsing of v_cmp_class* and v_cmpx_class* 
Fixed bug 32565: https://bugs.llvm.org//show_bug.cgi?id=32565

Reviewers: vpykhtin

Differential Revision: https://reviews.llvm.org/D31820

llvm-svn: 300073
 2017-04-12 16:31:18 +00:00
Dmitry Preobrazhensky 3bff0c8c59 [AMDGPU][MC] Corrected encoding of V_MQSAD_U32_U8 for CI 
Corrected encoding of V_MQSAD_U32_U8 for CI

See bug 32552: https://bugs.llvm.org//show_bug.cgi?id=32552

Reviewers: vpykhtin

Differential Revision: https://reviews.llvm.org/D31810

llvm-svn: 300070
 2017-04-12 15:36:09 +00:00
Dmitry Preobrazhensky 7184c44d66 [AMDGPU][MC] Corrected ds_wrxchg2* to support two offsets 
Fixed bug 28227: https://bugs.llvm.org//show_bug.cgi?id=28227

Reviewers: vpykhtin

Differential Revision: https://reviews.llvm.org/D31808

llvm-svn: 300066
 2017-04-12 14:29:45 +00:00
Dmitry Preobrazhensky 12194e9bec [AMDGPU][MC] Corrected src0 size for s_cbranch_join 
Fix for bug 28159: https://bugs.llvm.org//show_bug.cgi?id=28159

Reviewers: vpykhtin, arsenm

Differential Revision: https://reviews.llvm.org/D31595

llvm-svn: 300055
 2017-04-12 12:40:19 +00:00
Dmitry Preobrazhensky e5147247b8 [AMDGPU][MC] Fix for Bug 28211 + LIT tests 
- corrected DS_GWS_* opcodes (see VI_Shader_Programming#16.pdf for detailed description)
  - address operand is not used
  - several opcodes have data operand
  - all opcodes have offset modifier
- DS_AND_SRC2_B32: corrected typo in mnemo
- DS_WRAP_RTN_F32 replaced with DS_WRAP_RTN_B32
- added CI/VI opcodes:
  - DS_CONDXCHG32_RTN_B64
  - DS_GWS_SEMA_RELEASE_ALL
- added VI opcodes:
  - DS_CONSUME
  - DS_APPEND
  - DS_ORDERED_COUNT

Differential Revision: https://reviews.llvm.org/D31707

llvm-svn: 299767
 2017-04-07 13:07:13 +00:00
Dmitry Preobrazhensky 3ac6311a8d [AMDGPU][MC] Fix for Bug 28158 + LIT tests 
Added support of the following instructions:
- s_cbranch_cdbgsys
- s_cbranch_cdbgsys_and_user
- s_cbranch_cdbgsys_or_user
- s_cbranch_cdbguser
- s_setkill

Reviewers: vpykhtin

Differential Revision: https://reviews.llvm.org/D31469

llvm-svn: 299567
 2017-04-05 17:26:45 +00:00
Dmitry Preobrazhensky 45db65037f [AMDGPU][MC] Fix for Bug 28167 + LIT tests 
Corrected src0 for v_writelane_b32:
- Enabled inline constants and literals for SI/CI (VOP2)
- Enabled inline constants for VI (VOP3)

Reviewers: vpykhtin, arsenm

https://reviews.llvm.org/D31463

llvm-svn: 299555
 2017-04-05 16:08:21 +00:00
Dmitry Preobrazhensky c512d44845 [AMDGPU][MC] Fix for Bug 28207 + LIT tests 
Enabled clamp and omod for v_cvt_* opcodes which have src0 of an integer type

Reviewers: vpykhtin, arsenm

Differential Revision: https://reviews.llvm.org/D31327

llvm-svn: 298852
 2017-03-27 15:57:17 +00:00
Konstantin Zhuravlyov 4986d9fb45 [AMDGPU] Rename Kind to ValueKind in metadata to be consistent 
llvm-svn: 298722
 2017-03-24 18:43:15 +00:00
Konstantin Zhuravlyov 4cbb68959b [AMDGPU] Do not emit isa info as code object metadata 
- It was decided to expose this information through other means (rocr)

Differential Revision: https://reviews.llvm.org/D30970

llvm-svn: 298560
 2017-03-22 23:27:09 +00:00
Konstantin Zhuravlyov a780ffaac2 [AMDGPU] Emit kernel debug properties as code object metadata 
Differential Revision: https://reviews.llvm.org/D30969

llvm-svn: 298558
 2017-03-22 23:10:46 +00:00
Konstantin Zhuravlyov ca0e7f6472 [AMDGPU] Emit kernel code properties as code object metadata 
- These are not required for low level runtime

Differential Revision: https://reviews.llvm.org/D29949

llvm-svn: 298556
 2017-03-22 22:54:39 +00:00
Konstantin Zhuravlyov 7498cd61fb [AMDGPU] Restructure code object metadata creation 
- Rename runtime metadata -> code object metadata
  - Make metadata not flow
  - Switch enums to use ScalarEnumerationTraits
  - Cleanup and move AMDGPUCodeObjectMetadata.h to AMDGPU/MCTargetDesc
  - Introduce in-memory representation for attributes
  - Code object metadata streamer
  - Create metadata for isa and printf during EmitStartOfAsmFile
  - Create metadata for kernel during EmitFunctionBodyStart
  - Finalize and emit metadata to .note during EmitEndOfAsmFile
  - Other minor improvements/bug fixes

Differential Revision: https://reviews.llvm.org/D29948

llvm-svn: 298552
 2017-03-22 22:32:22 +00:00
Dmitry Preobrazhensky 895d377dc7 [AMDGPU][MC] Fix for Bug 28204 + LIT tests 
Fixed v_mad_i64_i32/u64_u32 encoding

Reviewers: artem.tamazov

Differential Revision: https://reviews.llvm.org/D30828

llvm-svn: 298502
 2017-03-22 13:31:01 +00:00
Dmitry Preobrazhensky 1e124e1825 [AMDGPU][MC] Fix for Bugs 28201, 28199, 28170 + LIT tests 
This fix enables sp3 abs modifier with constants

Reviewers: artem.tamazov

Differential Revision: https://reviews.llvm.org/D30825

llvm-svn: 298265
 2017-03-20 16:33:20 +00:00
Dmitry Preobrazhensky 40af9c35d3 [AMDGPU][MC] Fix for Bugs 28200, 28202 + LIT tests 
Fixed several related issues with VOP3 fp modifiers.

Reviewers: artem.tamazov

Differential Revision: https://reviews.llvm.org/D30821

llvm-svn: 298255
 2017-03-20 14:50:35 +00:00
Dmitry Preobrazhensky 03880f8d24 [AMDGPU][MC] Fix for Bug 30829 + LIT tests 
Added code to check constant bus restrictions for VOP formats (only one SGPR value or literal-constant may be used by the instruction).
Note that the same checks are performed by SIInstrInfo::verifyInstruction (used by lowering code).
Added LIT tests.

llvm-svn: 296873
 2017-03-03 14:31:06 +00:00
Matt Arsenault 4d263f6f18 AMDGPU: Add definition for v_swap_b32 
This is somewhat tricky because there are two
pairs of tied operands, and it isn't allowed to be
VOP3 encoded.

llvm-svn: 296519
 2017-02-28 21:09:04 +00:00
Matt Arsenault 03612631cb AMDGPU: Add definition for v_xad_u32 
llvm-svn: 296515
 2017-02-28 20:27:30 +00:00
Matt Arsenault 781249833b AMDGPU: Add ds_nop to assembler 
llvm-svn: 296513
 2017-02-28 20:15:46 +00:00
Matt Arsenault dedc544ac7 AMDGPU: Add definitions for ds_{read|write}_b{96|128} 
It's not clear to me if this is always better than
doing ds_write2_b64 This adds the constraint of
a 128-bit register input instead of a pair of
64-bit.

llvm-svn: 296512
 2017-02-28 20:15:43 +00:00
Konstantin Zhuravlyov 182e9cc6d5 [AMDGPU] Change amd_kernel_code_t's minor version to 1 
- We do emit amd_kernel_code_t v1.1

Differential Revision: https://reviews.llvm.org/D30433

llvm-svn: 296489
 2017-02-28 17:17:52 +00:00