62a6f7eda6
Add entry in getTargetNodeName() for ARMISD::VBICIMM.
...
llvm-svn: 120233
2010-11-28 06:51:11 +00:00
7283b8d18c
Move more PEI-related hooks to TFI
...
llvm-svn: 120229
2010-11-27 23:05:25 +00:00
d08fbd19f5
Move callee-saved regs spills / reloads to TFI
...
llvm-svn: 120228
2010-11-27 23:05:03 +00:00
5d882894d8
Lower TLS_addr32 and TLS_addr64.
...
llvm-svn: 120225
2010-11-27 20:43:02 +00:00
eab0800695
Implement the data16 prefix.
...
llvm-svn: 120224
2010-11-27 20:29:45 +00:00
f2d08136bf
Remove PIC16 remnants.
...
llvm-svn: 120223
2010-11-27 18:20:30 +00:00
e308b8edab
macho-dump: Add support for --dump-section-data and tweak a few format strings.
...
llvm-svn: 120219
2010-11-27 13:58:16 +00:00
83224fc391
macho-dump: Add support for dumping symbol table entries.
...
llvm-svn: 120218
2010-11-27 13:52:53 +00:00
8680ce6ffc
macho-dump: Add support for dumping string table data.
...
llvm-svn: 120217
2010-11-27 13:46:11 +00:00
0ac77d526d
macho-dump: Add support for dumping relocation entries.
...
llvm-svn: 120216
2010-11-27 13:39:48 +00:00
5867690cfa
macho-dump: Add support for dumping sections.
...
llvm-svn: 120215
2010-11-27 13:33:15 +00:00
c983afc5a1
macho-dump: Add support for dumping dysymtab indirect symbol table.
...
llvm-svn: 120214
2010-11-27 13:26:12 +00:00
032f08b556
Unbreak build for newer GCCs.
...
llvm-svn: 120205
2010-11-27 09:08:25 +00:00
33dab2a6ee
macho-dump: Add support for dumping symtab and dysymtab commands.
...
llvm-svn: 120204
2010-11-27 08:33:44 +00:00
a8070e0284
macho-dump: Add support for dumping segment load commands.
...
llvm-svn: 120203
2010-11-27 08:22:29 +00:00
8ba5f39f70
Second attempt at fixing the performance regressions introduced
...
by my recent GVN improvement. Looking through a single layer of
PHI nodes when attempting to sink GEPs, we need to iteratively
look through arbitrary PHI nests.
llvm-svn: 120202
2010-11-27 08:15:55 +00:00
65dc891942
raw_ostream::write_escaped: Add a UseHexEscapes argument.
...
llvm-svn: 120200
2010-11-27 07:59:50 +00:00
768a5e8004
Fix a comment.
...
llvm-svn: 120199
2010-11-27 07:39:37 +00:00
3977e7d22c
Object/Mach-O: Add header and load command information.
...
llvm-svn: 120198
2010-11-27 07:19:41 +00:00
d74cf2c8f6
Refactor. Set alignment bit in VLD1-dup instruction classes.
...
llvm-svn: 120197
2010-11-27 07:12:02 +00:00
feb1c5d830
Object/Mach-O: Validate Mach-O magic and initialize format info.
...
llvm-svn: 120195
2010-11-27 06:39:22 +00:00
c92eea0175
Add NEON VLD1-dup instructions (load 1 element to all lanes).
...
llvm-svn: 120194
2010-11-27 06:35:16 +00:00
3a63f9d852
Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions.
...
I added these instructions recently but I have no idea where these "1"
values in the NextCycles field came from. As far as I can tell now,
these instruction stages are clearly intended to overlap.
llvm-svn: 120193
2010-11-27 06:35:09 +00:00
1df8d83a55
MC/Mach-O: Start stubbing out a Mach-O object file wrapper.
...
llvm-svn: 120190
2010-11-27 05:38:50 +00:00
4b128a5d4f
Reduce nesting.
...
llvm-svn: 120189
2010-11-27 05:18:48 +00:00
eab6e401fe
MC/Mach-O: Migrate more constants into MachOFormat.h.
...
llvm-svn: 120188
2010-11-27 04:59:14 +00:00
a5f50c16f7
MC/Mach-O: Switch to using MachOFormat.h.
...
- I'm leaving MachO.h, because I believe it has external consumers, but I would really like to eliminate it (we have stylistic disagreements with one another).
llvm-svn: 120187
2010-11-27 04:38:36 +00:00
2263ca4834
MC/Mach-O: Introduce Object/MachOFormat for describing purely platform / machine
...
independent information on the Mach object format, and move some stuff from
MachObjectWriter.cpp there.
llvm-svn: 120186
2010-11-27 04:19:38 +00:00
bf4a4e4ad9
Remove the unused TheTarget member.
...
llvm-svn: 120168
2010-11-26 04:24:21 +00:00
f13f442b1a
Fix Whitespace.
...
llvm-svn: 120166
2010-11-26 04:16:08 +00:00
a12095d26d
Move tree navigation to a new Path class that doesn't have to be a template.
...
The path also holds a reference to the root node, and that allows important
iterator accessors like start() and stop() to have no conditional code. (When
the compiler is clever enough to remove it.)
llvm-svn: 120165
2010-11-26 01:39:40 +00:00
7c2acd022e
Use multiple 0x66 prefixes so that all nops up to 15 bytes are a single instruction.
...
llvm-svn: 120147
2010-11-25 17:14:16 +00:00
aef5bd049f
Namespacify.
...
llvm-svn: 120146
2010-11-25 16:42:51 +00:00
f8e127eaf6
Factor some code to parseSectionFlags and fix the default type of a section.
...
llvm-svn: 120145
2010-11-25 15:32:56 +00:00
b8de00ee07
Treat a call of function pointer like a load of the pointer when considering
...
whether the pointer can be replaced with the global variable it is a copy of.
Fixes PR8680.
llvm-svn: 120126
2010-11-24 22:04:20 +00:00
9f75d5df0b
Behave a bit more like gnu as and use the symbol (instead of the section)
...
for any relocation to a symbol defined in a tls section.
llvm-svn: 120121
2010-11-24 21:57:39 +00:00
708ac4d6ad
Relocate with the symbol if the relocation is of kind NTPOFF.
...
Patch by David Meyer, I added the test.
llvm-svn: 120104
2010-11-24 19:23:50 +00:00
e98d483b71
Fix and add tests for all cases in x86 and x86_64 where gnu as implicitly
...
sets the type of a symbol to STT_TLS.
llvm-svn: 120100
2010-11-24 18:51:21 +00:00
8ad3b25633
Updating MBlaze .mask and .frame directives to match GCC's output and fixing regression introduced in 120095 by checking MCStreamer::hasRawTextSupport.
...
llvm-svn: 120097
2010-11-24 16:32:35 +00:00
51917b868d
1. Fixing error where basic block labels were not being printed out when they need to be for the MBlaze backend because AsmPrinter::isBlockOnlyReachableByFallthrough does not take into account delay slots.
...
2. Re-adding .mask and .frame directives in printed assembly.
3. Adding .ent and .end directives in printed assembly.
4. Minor cleanups to MBlaze backend.
llvm-svn: 120095
2010-11-24 15:39:32 +00:00
e0a1d2b32c
Use i8 as SETCC result type for i1 in SPU.
...
llvm-svn: 120092
2010-11-24 12:59:16 +00:00
97fc68774c
Allow for 'fcmp ogt' in SPU.
...
Fix by Visa Putkinen!
llvm-svn: 120090
2010-11-24 11:42:17 +00:00
4e70ac7b68
If a symbol is used as tls, mark it as tls even if not declare as so. Probably
...
fixes PR8659.
llvm-svn: 120076
2010-11-24 02:19:40 +00:00
6bf4e6d8b2
add a MemoryBuffer::getOpenFile method, which turns an open
...
file descriptor into a MemoryBuffer (and closes the FD).
llvm-svn: 120065
2010-11-23 22:20:27 +00:00
0488d564e1
Rename SimplifyDistributed to the more meaningfull name SimplifyByFactorizing.
...
llvm-svn: 120051
2010-11-23 20:42:39 +00:00
94a622af4c
The srem -> urem transform is not safe for any divisor that's not a power of two.
...
E.g. -5 % 5 is 0 with srem and 1 with urem.
Also addresses Frits van Bommel's comments.
llvm-svn: 120049
2010-11-23 20:33:57 +00:00
433c1679cf
Replace calls to ConstantFoldInstruction with calls to SimplifyInstruction
...
in two places that are really interested in simplified instructions, not
constants.
llvm-svn: 120044
2010-11-23 20:26:33 +00:00
bb2cd025a9
Constant folding here is pointless, because InstructionSimplify
...
(which does constant folding and more) is called a few lines
later.
llvm-svn: 120042
2010-11-23 20:24:21 +00:00
8e21bf84e8
Move the ARM reloc constants to Support/ELF.h
...
llvm-svn: 120035
2010-11-23 19:40:36 +00:00
d7d2cf7842
Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations.
...
We need to check if the individual vector elements are sign/zero-extended
values. For now this only handles constants values. Radar 8687140.
llvm-svn: 120034
2010-11-23 19:38:38 +00:00
b5afa65b0a
InstCombine: Reduce "X shift (A srem B)" to "X shift (A urem B)" iff B is positive.
...
This allows to transform the rem in "1 << ((int)x % 8);" to an and.
llvm-svn: 120028
2010-11-23 18:52:42 +00:00
60813f96e0
Propagate LeftDistributes and RightDistributes into their only uses.
...
Stylistic improvement suggested by Frits van Bommel.
llvm-svn: 120026
2010-11-23 15:28:14 +00:00
22df741687
Fix typo pointed out by Frits van Bommel and Marius Wachtler.
...
llvm-svn: 120025
2010-11-23 15:25:34 +00:00
adc7771f18
Exploit distributive laws (eg: And distributes over Or, Mul over Add, etc) in a
...
fairly systematic way in instcombine. Some of these cases were already dealt
with, in which case I removed the existing code. The case of Add has a bunch of
funky logic which covers some of this plus a few variants (considers shifts to be
a form of multiplication), which I didn't touch. The simplification performed is:
A*B+A*C -> A*(B+C). The improvement is to do this in cases that were not already
handled [such as A*B-A*C -> A*(B-C), which was reported on the mailing list], and
also to do it more often by not checking for "only one use" if "B+C" simplifies.
llvm-svn: 120024
2010-11-23 14:23:47 +00:00
e1b6c273b8
Division by pow-of-2 is not cheap on SPU, do it with
...
shifts.
llvm-svn: 120022
2010-11-23 13:27:59 +00:00
f6c05b1d01
Implement the rex64 prefix.
...
llvm-svn: 120017
2010-11-23 11:23:24 +00:00
a021988d64
Expand a little on the description of what InstructionSimplify does.
...
llvm-svn: 120016
2010-11-23 10:50:08 +00:00
763dec0ab8
Clarify that constant folding of instructions applies when all operands
...
are constant. There was in fact one exception to this (phi nodes) - so
remove that exception (InstructionSimplify handles this so there should
be no loss).
llvm-svn: 120015
2010-11-23 10:16:18 +00:00
5c1d4e3b1e
Invalidate the layout on any relaxation, not just Instructions. Bug found by David Meyer.
...
While here, remove unused argument and rename UpdateForSlide to Invalidate.
llvm-svn: 120009
2010-11-23 08:08:33 +00:00
3c7cab1402
Produce a relocation for pcrel absolute values. Based on a patch by David Meyer.
...
llvm-svn: 120006
2010-11-23 07:20:12 +00:00
2dd97d2d60
Revert functionality doug added in r98575 that was never
...
documented and only used by some clang stuff I just removed.
llvm-svn: 120002
2010-11-23 06:09:51 +00:00
6e13aa1d3b
Reuse data fragments while lowering. Patch by David Meyer.
...
llvm-svn: 119999
2010-11-23 05:49:35 +00:00
527da1b6e2
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
...
llvm-svn: 119990
2010-11-23 03:31:01 +00:00
4329e078ac
add a 'LLVMConstIntOfArbitraryPrecision' api to the C api,
...
patch by Greg Pfeil!
llvm-svn: 119989
2010-11-23 02:47:22 +00:00
e5afa15b77
duncan's spider sense was right, I completely reversed the condition
...
on this instcombine xform. This fixes a miscompilation of 403.gcc.
llvm-svn: 119988
2010-11-23 02:42:04 +00:00
767a1e9adc
Fixed some style issues (no _, no spc after !)
...
llvm-svn: 119986
2010-11-22 22:05:16 +00:00
6e39a50fd5
Remove duplicated constants. Thanks to Jason for noticing it.
...
llvm-svn: 119985
2010-11-22 21:49:05 +00:00
f1ebb63161
InstCombine: Implement X - A*-B -> X + A*B.
...
llvm-svn: 119984
2010-11-22 20:31:27 +00:00
16b75262c4
Make the <ARCH>ELFObjectWriter statics private
...
llvm-svn: 119982
2010-11-22 18:57:00 +00:00
84ffdd5cf1
Fix misplaced statics.
...
llvm-svn: 119981
2010-11-22 18:47:05 +00:00
a262546df7
Kill trailing whitespace
...
llvm-svn: 119979
2010-11-22 18:42:07 +00:00
7c7d0ef287
Refactor the ELFRelocationEntry (pull up) and move the arch-specific statics to inside the class where it belongs.
...
Next step is to rationally break apart the RecordRelocation()
Probably the step will be to have 1 member function for ech slot of the ELFRelocationEntry()
llvm-svn: 119978
2010-11-22 18:41:13 +00:00
eb56dca4fd
Fix epilogue codegen to avoid leaving the stack pointer in an invalid
...
state. Previously Thumb2 would restore sp from fp like this:
mov sp, r7
sub, sp, #4
If an interrupt is taken after the 'mov' but before the 'sub', callee-saved
registers might be clobbered by the interrupt handler. Instead, try
restoring directly from sp:
add sp, #4
Or, if necessary (with VLA, etc.) use a scratch register to compute sp and
then restore it:
sub.w r4, r7, #8
mov sp, r7
rdar://8465407
llvm-svn: 119977
2010-11-22 18:12:04 +00:00
c133c54426
If a GEP index simply advances by multiples of a type of zero size,
...
then replace the index with zero.
llvm-svn: 119974
2010-11-22 16:32:50 +00:00
77d11d054c
Fix a bug with extractelement on SPU.
...
In the attached testcase, the element was
never extracted (missing rotate).
llvm-svn: 119973
2010-11-22 16:28:26 +00:00
3c227b0b89
Add basic CFI methods to the streamer interface.
...
llvm-svn: 119972
2010-11-22 14:27:24 +00:00
8a0f486e36
Move the "gep undef" -> "undef" transform from instcombine to
...
InstructionSimplify.
llvm-svn: 119970
2010-11-22 13:42:49 +00:00
556f203d64
Remove some #includes.
...
llvm-svn: 119967
2010-11-22 11:53:17 +00:00
24656c9583
Implement the "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" optimization.
...
This currently only catches the most basic case, a two-case switch, but can be
extended later.
llvm-svn: 119964
2010-11-22 09:45:38 +00:00
c6648eb4c3
Don't keep track of inserted phis in PromoteMemoryToRegister: the information
...
is never used. Patch by Cameron Zwarich.
llvm-svn: 119963
2010-11-22 09:41:24 +00:00
5cadccc4ea
Fix a compiler warning about Kind being used uninitialized
...
when assertions are disabled.
llvm-svn: 119962
2010-11-22 09:38:00 +00:00
37b0736bdc
Pseudos default to 4byte size, let the instruction size field notice
...
that branch tables are special.
llvm-svn: 119954
2010-11-21 23:38:19 +00:00
7699d6cfe9
Implement ELF object file writing support for the MBlaze backend. Its not perfect yet, but it works for many tests.
...
llvm-svn: 119952
2010-11-21 22:06:28 +00:00
f1d3800e65
Implement branch analysis in the MBlaze backend.
...
llvm-svn: 119951
2010-11-21 21:53:36 +00:00
f4efd582ad
Make it a little bit more explicit that the MBlaze backend only supports upto
...
32-bit immediate values.
llvm-svn: 119950
2010-11-21 21:39:46 +00:00
7493e30d42
Fix an error in the MBlaze delay slot filler where instructions that already
...
fill a delay slot are moved to fill a different delay slot.
llvm-svn: 119949
2010-11-21 21:36:12 +00:00
fc9aead6fd
fix comment
...
llvm-svn: 119948
2010-11-21 19:05:34 +00:00
5d2262dc76
apparently tailcalls are better on darwin/x86-64 than on linux?
...
llvm-svn: 119947
2010-11-21 18:59:20 +00:00
585dfa2b3d
Initialize MemDep's TD member so buildbots don't trip over an uninitialized pointer (TD is passed to PHITransAddr).
...
I wonder why this didn't explode earlier.
llvm-svn: 119944
2010-11-21 15:21:46 +00:00
cf4bceba49
Add a rather pointless InstructionSimplify transform, inspired by recent constant
...
folding improvements: if P points to a type of size zero, turn "gep P, N" into "P".
More generally, if a gep index type has size zero, instcombine could replace the
index with zero, but that is not done here.
llvm-svn: 119942
2010-11-21 13:53:09 +00:00
1f86be9164
Fix spelling.
...
llvm-svn: 119941
2010-11-21 12:43:13 +00:00
22db31305f
More Thumb encodings.
...
llvm-svn: 119940
2010-11-21 11:49:36 +00:00
c01d679928
Add encoding for ARM "trap" instruction.
...
llvm-svn: 119938
2010-11-21 11:05:29 +00:00
219dabdf68
The "trap" instruction is one of this which doesn't have a condition code. Hack
...
the code to not add a "condition code" if it's trap.
llvm-svn: 119937
2010-11-21 10:56:05 +00:00
3acd02706a
- Give "trap" the correct encoding, at least according to Darwin's assembler.
...
- Add comments saying where the encodings for other instructions came from.
llvm-svn: 119936
2010-11-21 10:55:23 +00:00
6ce038082b
apply Dan's fix for PR8268 which allows constant folding to handle indexes over
...
zero sized elements. This allows us to compile:
#include <string>
void foo() { std::string s; }
into an empty function.
llvm-svn: 119933
2010-11-21 08:39:01 +00:00
b4cd1819fa
implement PR8524, apparently mainline gas accepts movq as an alias for movd
...
when transfering between i64 gprs and mmx regs.
llvm-svn: 119931
2010-11-21 08:18:57 +00:00
5957229659
rework some DSE paths to use the newly-public "getPointerDependencyFrom"
...
method in MemDep instead of inserting an instruction, doing a query,
then removing it. Neither operation is effectively cached.
llvm-svn: 119930
2010-11-21 08:06:10 +00:00
663ba91cc6
add "getLocation" method to AliasAnalysis for getting the source and
...
destination location of a memcpy/memmove. I'm not clear about whether
TBAA works on these, so I'm leaving it out for now. Dan, please revisit
this when convenient.
llvm-svn: 119928
2010-11-21 07:51:27 +00:00
e48c31ce33
implement PR8576, deleting dead stores with intervening may-alias stores.
...
llvm-svn: 119927
2010-11-21 07:34:32 +00:00
9165d9d2ac
add some random notes.
...
llvm-svn: 119925
2010-11-21 07:05:31 +00:00
7e484e0be7
Use by-name rather than by-order operand matching for some NEON encodings.
...
llvm-svn: 119923
2010-11-21 06:47:06 +00:00
f7e896138e
optimize:
...
void a(int x) { if (((1<<x)&8)==0) b(); }
into "x != 3", which occurs over 100 times in 403.gcc but in no
other program in llvm-test.
llvm-svn: 119922
2010-11-21 06:44:42 +00:00
9de0176ef8
tail calls on x86 are implemented.
...
llvm-svn: 119920
2010-11-21 06:10:27 +00:00
e040a46eb3
BR_JTadd is ARM-only, so use the proper pseudo class to get the predicate.
...
llvm-svn: 119918
2010-11-21 01:26:01 +00:00
26cb15a549
Handle PCRel relocations with absolute values. Fixes PR8656.
...
llvm-svn: 119917
2010-11-21 00:48:25 +00:00
58f9f58716
Implement PR8644: forwarding a memcpy value to a byval,
...
allowing the memcpy to be eliminated.
Unfortunately, the requirements on byval's without explicit
alignment are really weak and impossible to predict in the
mid-level optimizer, so this doesn't kick in much with current
frontends. The fix is to change clang to set alignment on all
byval arguments.
llvm-svn: 119916
2010-11-21 00:28:59 +00:00
c31de25137
A few more thumb instruction MC encodings.
...
llvm-svn: 119913
2010-11-20 22:52:33 +00:00
0a3c28bd6b
Rewrite address handling to use a structure with all the possible address
...
mode variables. Handle frame indexes in load/store and allocas again.
llvm-svn: 119912
2010-11-20 22:38:27 +00:00
d0aec3bf64
STRH only needs the additional operand, not t2STRH. Also invert conditional
...
to match the one from the load emitter above.
llvm-svn: 119911
2010-11-20 22:01:38 +00:00
ddd1b7b801
Simplify code. No change in functionality.
...
llvm-svn: 119908
2010-11-20 18:43:35 +00:00
36590fc72a
Make this compile on case-sensitive file systemsw
...
llvm-svn: 119905
2010-11-20 16:14:57 +00:00
4687778398
Move some more hooks to TargetFrameInfo
...
llvm-svn: 119904
2010-11-20 15:59:32 +00:00
f6fb58a216
Silence Release build warnings about unused functions.
...
llvm-svn: 119903
2010-11-20 15:53:24 +00:00
7c601ded34
On X86, MEMBARRIER, MFENCE, SFENCE, LFENCE are not target memory intrinsics,
...
so don't claim they are. They are allocated using DAG.getNode, so attempts
to access MemSDNode fields results in reading off the end of the allocated
memory. This fixes crashes with "llc -debug" due to debug code trying to
print MemSDNode fields for these barrier nodes (since the crashes are not
deterministic, use valgrind to see this). Add some nasty checking to try
to catch this kind of thing in the future.
llvm-svn: 119901
2010-11-20 11:25:00 +00:00
cf7fefb25c
Removing the useless test that I added recently. It was meant as an example, but not complicated enough to merit another test.
...
llvm-svn: 119898
2010-11-20 07:26:51 +00:00
ada75c5ad1
RABasic fix. Regalloc is responsible for updating block live ins.
...
llvm-svn: 119896
2010-11-20 02:57:05 +00:00
799ec1c4d6
Whitespace.
...
llvm-svn: 119895
2010-11-20 02:43:55 +00:00
284326bd69
Add more Thumb add instruction encodings.
...
llvm-svn: 119883
2010-11-20 01:18:47 +00:00
fe1de03629
Add Thumb encodings for some add instructions.
...
llvm-svn: 119882
2010-11-20 01:00:29 +00:00
e60fd5a9db
Add more encodings for Thumb instructions.
...
llvm-svn: 119881
2010-11-20 00:53:35 +00:00
0914d44fa4
Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the same
...
value that the one in ARMMCCodeEmitter.cpp does.
llvm-svn: 119878
2010-11-20 00:26:37 +00:00
54df187f25
Check for _setjmp too, because it's also used.
...
llvm-svn: 119875
2010-11-20 00:03:09 +00:00
2aff392af9
Fix ARM LDR* post-indexed operand encoding.
...
llvm-svn: 119869
2010-11-19 23:14:43 +00:00
1825cc74f4
Encodings for the compare instructions.
...
llvm-svn: 119868
2010-11-19 23:14:32 +00:00
b4fd2c90e9
The Vm and Vn register fields must be the same for a register-register vmov.
...
llvm-svn: 119867
2010-11-19 23:12:43 +00:00
a5f048485f
Fix a cut-n-paste-error.
...
llvm-svn: 119866
2010-11-19 23:01:16 +00:00
ea326db47b
Document the new GVN number table structure.
...
llvm-svn: 119865
2010-11-19 22:48:40 +00:00
785952e5ac
Operand names
...
llvm-svn: 119864
2010-11-19 22:43:08 +00:00
5876e41c9f
trailing whitespace
...
llvm-svn: 119863
2010-11-19 22:42:55 +00:00
35e2d7f610
Don't need to save piecemeal now.
...
llvm-svn: 119862
2010-11-19 22:39:56 +00:00
cee83d6e6b
Update comment.
...
llvm-svn: 119861
2010-11-19 22:37:58 +00:00
a82fb71324
Add encodings for some of the thumb ADD instructions. Tests will come once the
...
asm parser can handle them.
llvm-svn: 119860
2010-11-19 22:37:33 +00:00
558b61e2d4
Update comment.
...
llvm-svn: 119859
2010-11-19 22:36:41 +00:00
7d8df3185f
Clarify operand names.
...
llvm-svn: 119858
2010-11-19 22:36:02 +00:00
fef5f315af
Refactor address mode handling into a single struct (ala x86), this
...
should give allow a wider range of addressing modes.
No functional change.
llvm-svn: 119856
2010-11-19 22:30:02 +00:00
48bf4f8e56
Fix encoding for ARM MLS instruction.
...
llvm-svn: 119855
2010-11-19 22:22:37 +00:00
dfb8c3bbfc
When folding addressing modes in CodeGenPrepare, attempt to look through PHI nodes
...
if all the operands of the PHI are equivalent. This allows CodeGenPrepare to undo
unprofitable PRE transforms.
llvm-svn: 119853
2010-11-19 22:15:03 +00:00
09d7bfd886
Add ARM encoding information for STRD.
...
llvm-svn: 119852
2010-11-19 22:14:31 +00:00
5a77b8b5c4
Shuffle things around a bit to keep like things together. Tidy up formatting.
...
llvm-svn: 119851
2010-11-19 22:06:57 +00:00
c92a5770df
Revert accidental commit.
...
llvm-svn: 119850
2010-11-19 22:06:18 +00:00
49a2e2384b
Change long binary encodings to use hex instead. It's more readable. Also
...
initialize missing bit.
llvm-svn: 119849
2010-11-19 22:02:18 +00:00
6e9aace4f3
Factor out operand encoding bits for ARM addressing mode 2 store instructions.
...
llvm-svn: 119846
2010-11-19 21:35:06 +00:00
09f6823eb6
Delete another dead class.
...
llvm-svn: 119844
2010-11-19 21:16:08 +00:00
e093e5f0dc
whitespace tweak.
...
llvm-svn: 119843
2010-11-19 21:14:37 +00:00
cf14a382ec
Fix a use after free. Patch by Frits van Bommel.
...
llvm-svn: 119842
2010-11-19 21:14:29 +00:00
d6e5c9f2fe
Refactor PICSTR* instructions to really be pseudos. Nuke dead classes.
...
llvm-svn: 119841
2010-11-19 21:14:02 +00:00
4a22eba616
Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes.
...
llvm-svn: 119840
2010-11-19 21:07:51 +00:00
003c6e700b
Add ARM binary encoding information for the rest of the indexed loads.
...
llvm-svn: 119821
2010-11-19 19:41:26 +00:00
88ff56caa3
Make isScalarToVector to return false if the node is a scalar. This will prevent
...
DAGCombine from making an illegal transformation of bitcast of a scalar to a
vector into a scalar_to_vector.
llvm-svn: 119819
2010-11-19 19:08:12 +00:00
8be14414f6
Added support for the Mach-O .symbol_resolver directive. rdar://8673046
...
llvm-svn: 119816
2010-11-19 18:39:33 +00:00
c6ac246671
Remove dead code.
...
llvm-svn: 119815
2010-11-19 18:18:37 +00:00
76aed40813
ARM LDRD binary encoding.
...
llvm-svn: 119812
2010-11-19 18:16:46 +00:00
d7a3550a5e
Remove hard tabs.
...
llvm-svn: 119810
2010-11-19 18:01:37 +00:00
2bb49e15a6
Remove trailing whitespace.
...
llvm-svn: 119806
2010-11-19 17:11:02 +00:00
2e49eaa92f
Avoid release build warnings.
...
llvm-svn: 119804
2010-11-19 16:36:02 +00:00
336021f758
Fix decoding ambiguities of stdrex and ldrex.
...
llvm-svn: 119801
2010-11-19 13:11:50 +00:00
c77ebcc9a5
Silence warning about an uninitialized variable.
...
llvm-svn: 119800
2010-11-19 11:37:26 +00:00
b238de0415
Remove threading of Xor over selects and phis, with an explanation
...
of why such threading is pointless.
llvm-svn: 119798
2010-11-19 09:20:39 +00:00
9900b4802e
Add a MCLineSectionOrder vector so that we produce the line tables in a
...
deterministic order.
llvm-svn: 119795
2010-11-19 07:41:23 +00:00
2debc86138
These instructions are thumb2 only.
...
llvm-svn: 119793
2010-11-19 06:28:11 +00:00
0eb2994626
Fix an obvious oversight.
...
llvm-svn: 119792
2010-11-19 06:15:10 +00:00
4031c5eb48
Don't attempt trivial coalescing for sub-register copies.
...
Patch by Krister Wombell!
llvm-svn: 119791
2010-11-19 05:45:24 +00:00
0b4c9aa9a9
Add an assert.
...
llvm-svn: 119788
2010-11-19 04:55:36 +00:00
345945e355
Add ADT/IntervalMap.
...
This is a sorted interval map data structure for small keys and values with
automatic coalescing and bidirectional iteration over coalesced intervals.
Except for coalescing intervals, it provides similar functionality to std::map.
It is however much more compact for small keys and values, and hopefully faster
too.
The container object itself can hold the first few intervals without any
allocations, then it switches to a cache conscious B+-tree representation. A
recycling allocator can be shared between many containers, even between
containers holding different types.
The IntervalMap is initially intended to be used with SlotIndex intervals for:
- Backing store for LiveIntervalUnion that is smaller and faster than std::set.
- Backing store for LiveInterval with less overhead than std::vector for typical
intervals and O(N log N) merging of large intervals. 99% of virtual registers
need 4 entries or less and would benefit from the small object optimization.
- Backing store for LiveDebugVariable which doesn't exist yet, but will track
debug variables during register allocation.
This is a work in progress. Missing items are:
- Performance metrics.
- erase().
- insert() shrinkage.
- clear().
- More performance metrics.
- Simplification and detemplatization.
llvm-svn: 119787
2010-11-19 04:47:19 +00:00
92ca933f6e
Fix llvm-gcc boostrap on OS X by avoiding printing sleb and uleb when
...
possible.
llvm-svn: 119785
2010-11-19 04:10:13 +00:00
b58867ccba
Change some methods in MCDwarf.cpp to be able to handle an arbitrary
...
MCStreamer instead of just MCObjectStreamer. Address changes cannot
be as efficient as we have to use DW_LNE_set_addres, but at least
most of the logic is shared.
This will be used so that, with CodeGen still using EmitDwarfLocDirective,
llvm-gcc is able to produce debug_line sections without needing an
assembler that supports .loc.
llvm-svn: 119777
2010-11-19 02:26:16 +00:00
945b776b6e
Add MC encodings for some Thumb instructions. Test for a few of them. The "bx
...
lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...
llvm-svn: 119774
2010-11-19 01:33:10 +00:00
09770251f6
Revert "Add ADT/IntervalMap.", GCC doesn't like it.
...
This reverts r119772.
llvm-svn: 119773
2010-11-19 01:21:03 +00:00
6d89171dcc
Add ADT/IntervalMap.
...
This is a sorted interval map data structure for small keys and values with
automatic coalescing and bidirectional iteration over coalesced intervals.
Except for coalescing intervals, it provides similar functionality to std::map.
It is however much more compact for small keys and values, and hopefully faster
too.
The container object itself can hold the first few intervals without any
allocations, then it switches to a cache conscious B+-tree representation. A
recycling allocator can be shared between many containers, even between
containers holding different types.
The IntervalMap is initially intended to be used with SlotIndex intervals for:
- Backing store for LiveIntervalUnion that is smaller and faster than std::set.
- Backing store for LiveInterval with less overhead than std::vector for typical
intervals and O(N log N) merging of large intervals. 99% of virtual registers
need 4 entries or less and would benefit from the small object optimization.
- Backing store for LiveDebugVariable which doesn't exist yet, but will track
debug variables during register allocation.
This is a work in progress. Missing items are:
- Performance metrics.
- erase().
- insert() shrinkage.
- clear().
- More performance metrics.
- Simplification and detemplatization.
llvm-svn: 119772
2010-11-19 01:14:40 +00:00
461e704a2c
Aligned and unaligned copies of the same string
...
were not hashing to the same value. Analysis
and patch by Frits van Bommel!
llvm-svn: 119770
2010-11-19 00:48:58 +00:00
20b5ea9858
Use array_pod_sort because the list is contiguous.
...
llvm-svn: 119769
2010-11-19 00:38:19 +00:00
f53e4d9fd1
Provide Thumb2 encodings for strex and ldrex.
...
llvm-svn: 119768
2010-11-19 00:28:38 +00:00
2aeb8b9361
Minor cleanups to a few llvm_unreachable() calls.
...
llvm-svn: 119767
2010-11-19 00:27:09 +00:00
2ecfcbd2aa
An 'unreachable' shouldn't have a '0 &&' prefix.
...
llvm-svn: 119762
2010-11-19 00:05:15 +00:00
2063b84297
Add support for parsing the writeback ("!") token.
...
llvm-svn: 119761
2010-11-18 23:43:05 +00:00
5a97bd873e
Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM.
...
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.
llvm-svn: 119760
2010-11-18 23:37:15 +00:00
3517585249
Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2.
...
llvm-svn: 119755
2010-11-18 23:29:56 +00:00
14ee344944
Move getInitialFrameState() to TargetFrameInfo
...
llvm-svn: 119754
2010-11-18 23:25:52 +00:00
a391c97bd0
ARM Encoding information for UXTAH and friends.
...
llvm-svn: 119753
2010-11-18 23:24:22 +00:00
cd68095650
Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first).
...
Added test case.
llvm-svn: 119749
2010-11-18 22:06:46 +00:00
0ab0f67925
Don't allocate the SmallVector of Registers. It gets messy figuring out who
...
should delete what when the object gets copied around. It's also making valgrind
upset.
llvm-svn: 119747
2010-11-18 21:50:54 +00:00
10839cb62c
Provide Thumb2 encodings for mov's that come from MOVCC SDNodes.
...
llvm-svn: 119744
2010-11-18 21:46:31 +00:00
1b91ae18ed
Add ARM encoding information for LDRH post-increment.
...
llvm-svn: 119743
2010-11-18 21:43:37 +00:00
0eecf5d201
Move hasFP() and few related hooks to TargetFrameInfo.
...
llvm-svn: 119740
2010-11-18 21:19:35 +00:00
c92331b984
Fix thinko: we must turn select(anyext, sext) into sext(select)
...
not anyext(select). Spotted by Frits van Bommel.
llvm-svn: 119739
2010-11-18 21:16:28 +00:00
7d47133ff7
Split up ARM LowerShift function.
...
This function was being called from two different places for completely
unrelated reasons. During type legalization, it was called to expand 64-bit
shift operations. During operation legalization, it was called to handle
Neon vector shifts. The vector shift code was not written to check for
illegal types, since it was assumed to be only called after type legalization.
Fixed this by splitting off the 64-bit shift expansion into a separate
function. I don't have a particular testcase for this; I just noticed it
by inspection.
llvm-svn: 119738
2010-11-18 21:16:28 +00:00
3fec5ff14b
More Thumb2 encodings.
...
llvm-svn: 119737
2010-11-18 21:15:19 +00:00
3625098459
Fill out the set of Thumb2 multiplication operator encodings.
...
llvm-svn: 119733
2010-11-18 20:32:18 +00:00
12f3b3b44f
The DAGCombiner was threading select over pairs of extending loads even
...
if the extension types were not the same. The result was that if you
fed a select with sext and zext loads, as in the testcase, then it
would get turned into a zext (or sext) of the select, which is wrong
in the cases when it should have been an sext (resp. zext). Reported
and diagnosed by Sebastien Deldon.
llvm-svn: 119728
2010-11-18 20:05:18 +00:00
aef146b890
Factor code for testing whether replacing one value with another
...
preserves LCSSA form out of ScalarEvolution and into the LoopInfo
class. Use it to check that SimplifyInstruction simplifications
are not breaking LCSSA form. Fixes PR8622.
llvm-svn: 119727
2010-11-18 19:59:41 +00:00
b9bd594610
Missed the _RET versions of LDMIA.
...
llvm-svn: 119726
2010-11-18 19:44:29 +00:00
b006fc9c07
Rewrite stack callee saved spills and restores to use push/pop instructions.
...
Remove movePastCSLoadStoreOps and associated code for simple pointer
increments. Update routines that depended upon other opcodes for save/restore.
Adjust all testcases accordingly.
llvm-svn: 119725
2010-11-18 19:40:05 +00:00
2e831897d6
Fix an order-of-deallocation issue where the AttrListImpl could be deallocated before the global
...
LLVMContext, causing memory errors. Patch by Peter Collingbourne.
llvm-svn: 119721
2010-11-18 18:59:13 +00:00
aa398c1617
Use thread-safe statics to avoid a static constructor here. This isn't thread-safe on MSVC, but we don't
...
support threaded LLVM there anyways.
llvm-svn: 119718
2010-11-18 18:49:05 +00:00
e4f7ec17f8
Oops, missed this file when remaing ExpandPseudos to ExpandISelPseudos.
...
llvm-svn: 119717
2010-11-18 18:48:28 +00:00
c2b786163c
Rename ExpandPseudos to ExpandISelPseudos to help clarify its role.
...
llvm-svn: 119716
2010-11-18 18:45:06 +00:00
c21c100f3d
Completely rework the datastructure GVN uses to represent the value number to leader mapping. Previously,
...
this was a tree of hashtables, and a query recursed into the table for the immediate dominator ad infinitum
if the initial lookup failed. This led to really bad performance on tall, narrow CFGs.
We can instead replace it with what is conceptually a multimap of value numbers to leaders (actually
represented by a hashtable with a list of Value*'s as the value type), and then
determine which leader from that set to use very cheaply thanks to the DFS numberings maintained by
DominatorTree. Because there are typically few duplicates of a given value, this scan tends to be
quite fast. Additionally, we use a custom linked list and BumpPtr allocation to avoid any unnecessary
allocation in representing the value-side of the multimap.
This change brings with it a 15% (!) improvement in the total running time of GVN on 403.gcc, which I
think is pretty good considering that includes all the "real work" being done by MemDep as well.
The one downside to this approach is that we can no longer use GVN to perform simple conditional progation,
but that seems like an acceptable loss since we now have LVI and CorrelatedValuePropagation to pick up
the slack. If you see conditional propagation that's not happening, please file bugs against LVI or CVP.
llvm-svn: 119714
2010-11-18 18:32:40 +00:00
51fdc47a11
ARMPseudoInst instructions should default to being considered a single 4-byte
...
instruction. Any that may be expanded otherwise by MC lowering should
override this value. rdar://8683274
llvm-svn: 119713
2010-11-18 18:01:40 +00:00
5a1a2d53de
Fix typos.
...
llvm-svn: 119712
2010-11-18 17:44:17 +00:00
5ed61fe6a1
Bounds-check APInt's operator[].
...
llvm-svn: 119708
2010-11-18 17:14:56 +00:00
21a9683641
ExpandPseudos doesn't have any dependencies, so it can use the
...
simple form of INITIALIZE_PASS.
llvm-svn: 119707
2010-11-18 17:14:05 +00:00
f1ebfc1544
Strip trailing whitespace.
...
llvm-svn: 119706
2010-11-18 17:06:31 +00:00
0ab28b62b1
Use llvm_unreachable for "impossible" situations.
...
llvm-svn: 119705
2010-11-18 17:05:57 +00:00
2e1fc849b2
Add support for PHI-translating sext, zext, and trunc instructions,
...
enabling more PRE. PR8586.
llvm-svn: 119704
2010-11-18 17:05:13 +00:00
1385dff8c0
slightly simplify code and substantially improve comment. Instead of
...
saying "it would be bad", give an example of what is going on.
llvm-svn: 119695
2010-11-18 08:07:09 +00:00
731caac7c6
remove a pointless restriction from memcpyopt. It was
...
refusing to optimize two memcpy's like this:
copy A <- B
copy C <- A
if it couldn't prove that noalias(B,C). We can eliminate
the copy by producing a memmove instead of memcpy.
llvm-svn: 119694
2010-11-18 08:00:57 +00:00
c274a83442
remove another pointless noalias check: M is a memcpy, so the
...
source and dest are known to not overlap.
llvm-svn: 119692
2010-11-18 07:39:57 +00:00
75cfe98534
use AA::isNoAlias instead of open coding it. Remove an extraneous noalias check:
...
there is no need to check to see if the source and dest of a memcpy are noalias,
behavior is undefined if not.
llvm-svn: 119691
2010-11-18 07:38:43 +00:00
1e37bbafbb
finish a thought.
...
llvm-svn: 119690
2010-11-18 07:32:33 +00:00
7e9b2ea3bf
rearrange some code, splitting memcpy/memcpy optimization
...
out of processMemCpy into its own function.
llvm-svn: 119687
2010-11-18 07:02:37 +00:00
ac5701319b
allow eliminating an alloca that is just copied from an constant global
...
if it is passed as a byval argument. The byval argument will just be a
read, so it is safe to read from the original global instead. This allows
us to promote away the %agg.tmp alloca in PR8582
llvm-svn: 119686
2010-11-18 06:41:51 +00:00
f183d5c4be
enhance the "alloca is just a memcpy from constant global"
...
to ignore calls that obviously can't modify the alloca
because they are readonly/readnone.
llvm-svn: 119683
2010-11-18 06:26:49 +00:00
7aeae25c78
fix a small oversight in the "eliminate memcpy from constant global"
...
optimization. If the alloca that is "memcpy'd from constant" also has
a memcpy from *it*, ignore it: it is a load. We now optimize the testcase to:
define void @test2() {
%B = alloca %T
%a = bitcast %T* @G to i8*
%b = bitcast %T* %B to i8*
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %b, i8* %a, i64 124, i32 4, i1 false)
call void @bar(i8* %b)
ret void
}
previously we would generate:
define void @test() {
%B = alloca %T
%b = bitcast %T* %B to i8*
%G.0 = getelementptr inbounds %T* @G, i32 0, i32 0
%tmp3 = load i8* %G.0, align 4
%G.1 = getelementptr inbounds %T* @G, i32 0, i32 1
%G.15 = bitcast [123 x i8]* %G.1 to i8*
%1 = bitcast [123 x i8]* %G.1 to i984*
%srcval = load i984* %1, align 1
%B.0 = getelementptr inbounds %T* %B, i32 0, i32 0
store i8 %tmp3, i8* %B.0, align 4
%B.1 = getelementptr inbounds %T* %B, i32 0, i32 1
%B.12 = bitcast [123 x i8]* %B.1 to i8*
%2 = bitcast [123 x i8]* %B.1 to i984*
store i984 %srcval, i984* %2, align 1
call void @bar(i8* %b)
ret void
}
llvm-svn: 119682
2010-11-18 06:20:47 +00:00
dca25f69ca
trivial QoI improvement. On this invalid input:
...
sahf movl 344(%rdi),%r14d
we used to produce:
t.s:2:1: error: unexpected token in argument list
^
we now produce:
t.s:1:11: error: unexpected token in argument list
sahf movl 344(%rdi),%r14d
^
rdar://8581401
llvm-svn: 119676
2010-11-18 02:53:02 +00:00
67c6ab8865
Change CodeGen to use .loc directives. This produces a lot more readable output
...
and testing is easier. A good example is the unknown-location.ll test that
now can just look for ".loc 1 0 0". We also don't use a DW_LNE_set_address for
every address change anymore.
llvm-svn: 119613
2010-11-18 02:04:25 +00:00
2d4e42fba6
Silence compiler warnings.
...
llvm-svn: 119610
2010-11-18 01:43:23 +00:00
9c335bf977
Remove trailing whitespace.
...
llvm-svn: 119608
2010-11-18 01:39:50 +00:00
a74c7ccd59
ARM PseudoInst instructions don't need or use an assembler string. Get rid of
...
the operand to the pattern.
llvm-svn: 119607
2010-11-18 01:38:26 +00:00
ed0d840838
Do not throw away alignment when generating the DAG for
...
memset; we may need it to decide between MOVAPS and MOVUPS
later. Adjust a test that was looking for wrong code.
PR 3866 / 8675131.
llvm-svn: 119605
2010-11-18 01:35:23 +00:00
a2f30cc121
Code clean up.
...
llvm-svn: 119604
2010-11-18 01:28:51 +00:00
19be1fbca1
Add FIXME.
...
llvm-svn: 119603
2010-11-18 01:20:48 +00:00
cfb66204b7
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not
...
just pretend to be.
llvm-svn: 119602
2010-11-18 01:15:56 +00:00
d127e7174b
Try again at providing Thumb2 encodings for basic multiplication operators.
...
llvm-svn: 119601
2010-11-18 01:08:42 +00:00
8e7f8df4a2
Refactor a few ARM load instructions to better parameterize things and re-use
...
common encoding information.
llvm-svn: 119598
2010-11-18 00:46:58 +00:00
28883834e1
Revert r119593 while I figure out my testing disagrees with the buildbot.
...
llvm-svn: 119597
2010-11-18 00:42:51 +00:00
8ea83d81e0
Introduce memoization for ScalarEvolution dominates and properlyDominates
...
queries, and SCEVExpander getRelevantLoop queries.
llvm-svn: 119595
2010-11-18 00:34:22 +00:00
64aaddcd64
Provide correct Thumb2 encodings for basic multiplication operators.
...
llvm-svn: 119593
2010-11-18 00:19:10 +00:00
ddc7ce548c
Bug 8621 fix - pointer cast stripped from inline asm constraint argument.
...
llvm-svn: 119590
2010-11-17 23:58:47 +00:00
56f471726c
Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't mark
...
it as such. Add some encoding information.
llvm-svn: 119588
2010-11-17 23:33:14 +00:00
7e6b393e66
Factor out the code for purging a SCEV from all the various memoization maps.
...
Some of these maps may merge in the future, but for now it's convenient to have
a utility function for them.
llvm-svn: 119587
2010-11-17 23:28:48 +00:00
7ee1bbb76c
Merge the implementations of isLoopInvariant and hasComputableLoopEvolution, and
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memoize the results. This improves compile time in code which highly complex
expressions which get queried many times.
llvm-svn: 119584
2010-11-17 23:21:44 +00:00
534749bf70
Make SCEV::getType() and SCEV::print non-virtual. Move SCEV::hasOperand
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to ScalarEvolution. Delete SCEV::~SCEV. SCEV is no longer virtual.
llvm-svn: 119578
2010-11-17 22:27:42 +00:00
55425e7f78
Second attempt at correct encodings for Thumb2 bitfield instructions.
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llvm-svn: 119575
2010-11-17 22:16:31 +00:00
4ded8f264a
Fix comment typo.
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llvm-svn: 119573
2010-11-17 21:57:51 +00:00
20d9ce21ef
Move SCEV::dominates and properlyDominates to ScalarEvolution.
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llvm-svn: 119570
2010-11-17 21:41:58 +00:00
881b45ccdf
Change ARMGlobalMerge to keep BSS globals in separate pools.
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This completes the fixes for Radar 8673120.
llvm-svn: 119566
2010-11-17 21:25:39 +00:00
4c8ab19c22
Fix ARMGlobalMerge pass to check if globals are entirely within range.
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It is generally not sufficient to check if the starting offset is in range
of the maximum offset that can be efficiently used for the target.
llvm-svn: 119565
2010-11-17 21:25:36 +00:00
59182fb4b5
Change the symbol for merged globals from "merged" to "_MergedGlobals".
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This makes it more clear that the symbol is an internal, compiler-generated
name and gives a little more description about its contents.
llvm-svn: 119564
2010-11-17 21:25:33 +00:00
f796d4b469
Fix the ARMGlobalMerge pass to look at variable sizes instead of pointer sizes.
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It was mistakenly looking at the pointer type when checking for the size of
global variables. This is a partial fix for Radar 8673120.
llvm-svn: 119563
2010-11-17 21:25:27 +00:00
afd6db9932
Move SCEV::isLoopInvariant and hasComputableLoopEvolution to be member
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functions of ScalarEvolution, in preparation for memoization and
other optimizations.
llvm-svn: 119562
2010-11-17 21:23:15 +00:00
08c562bba6
Make the ARM BR_JTadd instruction an explicit pseudo and lower it properly
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in the MC lowering process.
llvm-svn: 119559
2010-11-17 21:05:55 +00:00
39c81c0a55
Avoid isel movcc of large immediates when the large immediate is available in a register. These immediates aren't free.
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llvm-svn: 119558
2010-11-17 20:56:30 +00:00
1ee6d24072
Reference ScalarEvolution by name rather than directly in LICM,
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to avoid an unneeded dependence.
llvm-svn: 119557
2010-11-17 20:50:07 +00:00
39d77131a1
Before replacing a phi node with a different value, it
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needs to be checked that this won't break LCSSA form.
Change the existing checking method to a more direct one:
rather than seeing if all predecessors belong to the loop,
check that the replacing value is either not in any loop or
is in a loop that contains the phi node.
llvm-svn: 119556
2010-11-17 20:49:12 +00:00
6c37ceb182
Revert r119551, which broke buildbots.
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llvm-svn: 119555
2010-11-17 20:48:51 +00:00
d3a32ae4c8
Verify SCEVAddRecExpr's invariant in ScalarEvolution::getAddRecExpr
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instead of in SCEVAddRecExpr's constructor, in preparation for an
upcoming change.
llvm-svn: 119554
2010-11-17 20:48:38 +00:00
7464116bde
Provide Thumb2 encodings for bitfield instructions.
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llvm-svn: 119551
2010-11-17 20:35:29 +00:00
ed75631743
Fix ScalarEvolution's range memoization to avoid using a
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default ctor with ConstantRange.
llvm-svn: 119550
2010-11-17 20:23:08 +00:00
7f8ab6ee8b
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
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and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.
Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.
Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.
2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.
rdar://8663787, rdar://8241368
llvm-svn: 119548
2010-11-17 20:13:28 +00:00
Bob Wilson