llvm-project

Commit Graph

Author	SHA1	Message	Date
Stanislav Mekhanoshin	74e2974ac6	[AMDGPU] Fixed some instructions latencies Differential Revision: https://reviews.llvm.org/D45073 llvm-svn: 328874	2018-03-30 16:19:13 +00:00
Matt Arsenault	301162c4fe	AMDGPU: Replace i64 add/sub lowering Use VOP3 add/addc like usual. This has some tradeoffs. Inline immediates fold a little better, but other constants are worse off. SIShrinkInstructions could be made smarter to handle these cases. This allows us to avoid selecting scalar adds where we need to track the carry in scc and replace its users. This makes it easier to use the carryless VALU adds. llvm-svn: 318340	2017-11-15 21:51:43 +00:00
Matt Arsenault	4f6318fe1b	AMDGPU: Select v_mad_u64_u32 and v_mad_i64_i32 llvm-svn: 317492	2017-11-06 17:04:37 +00:00

Author

SHA1

Message

Date

Stanislav Mekhanoshin

74e2974ac6

[AMDGPU] Fixed some instructions latencies

Differential Revision: https://reviews.llvm.org/D45073

llvm-svn: 328874

2018-03-30 16:19:13 +00:00

Matt Arsenault

301162c4fe

AMDGPU: Replace i64 add/sub lowering

Use VOP3 add/addc like usual.

This has some tradeoffs. Inline immediates fold
a little better, but other constants are worse off.
SIShrinkInstructions could be made smarter to handle
these cases.

This allows us to avoid selecting scalar adds where we
need to track the carry in scc and replace its users.
This makes it easier to use the carryless VALU adds.

llvm-svn: 318340

2017-11-15 21:51:43 +00:00

Matt Arsenault

4f6318fe1b

AMDGPU: Select v_mad_u64_u32 and v_mad_i64_i32

llvm-svn: 317492

2017-11-06 17:04:37 +00:00

3 Commits