Commit Graph

96076 Commits

Author SHA1 Message Date
Daniel Sanders 51287b9355 [mips][msa] Rename arguments to MSA_INSERT_DESC_BASE to better match their expected values.
No functional change.

llvm-svn: 191517
2013-09-27 12:45:08 +00:00
Daniel Sanders a515070eb3 [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.
For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is
later expanded to appropriate insve.[wd] insns.

llvm-svn: 191515
2013-09-27 12:31:32 +00:00
Daniel Sanders 39bb8ba023 [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64
For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may
be expanded to subregister copies and/or instructions as appropriate.

llvm-svn: 191514
2013-09-27 12:17:32 +00:00
Andrea Di Biagio 63192f635e Remove superfluous comment accidentally checked-in.
llvm-svn: 191513
2013-09-27 12:13:58 +00:00
Daniel Sanders 9ea9ff2da7 [mips][msa] Added support for MSA registers to copyPhysReg
llvm-svn: 191512
2013-09-27 12:03:51 +00:00
Daniel Sanders 7e51fe19d5 [mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics)
Updated some of the vshf since they (correctly) emit splati's now

llvm-svn: 191511
2013-09-27 11:48:57 +00:00
Andrea Di Biagio 56ce9c4e78 Re-apply the change from r191393 with fix for pr17380.
This change fixes the problem reported in pr17380 and re-add the dagcombine 
transformation ensuring that the value types are always legal if the 
transformation is triggered after Legalization took place.

Added the test case from pr17380.

llvm-svn: 191509
2013-09-27 11:37:05 +00:00
Daniel Sanders 928920ab29 [mips][msa] Added MSA.txt to describe instruction selection quirks.
This file contains notes about the instruction selection for MSA. For example,
it notes that ilvl.d is cannot be selected because ilvev.d covers the same
cases and is selected instead of ilvl.d.

llvm-svn: 191507
2013-09-27 10:42:22 +00:00
Tilmann Scheller 041f717680 Fix comment.
llvm-svn: 191505
2013-09-27 10:38:11 +00:00
Tilmann Scheller 88c8f16558 ARM: Teach assembler to enforce constraint for Thumb2 LDRD (literal/immediate) destination register operands.
LDRD<c> <Rt>, <Rt2>, <label>
LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}]
LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm>
LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!

As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2.

If this constraint is not met the result of executing the instruction will be unpredictable.

Fixes rdar://14479780.

llvm-svn: 191504
2013-09-27 10:30:18 +00:00
Daniel Sanders 84e7caf741 [mips][msa] Tidy up
lowerMSABinaryIntr, lowerMSABinaryImmIntr, lowerMSABranchIntr,
and lowerMSAUnaryIntr were trivially small functions. Inlined them into
their callers.

lowerMSASplat now takes its callers SDLoc instead of making a new one.

No functional change.

llvm-svn: 191503
2013-09-27 10:25:41 +00:00
Daniel Sanders 1b1e25b7c5 [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
llvm-svn: 191498
2013-09-27 10:08:31 +00:00
Daniel Sanders 36c671e2c7 [mips][msa] Expand all truncstores and loadexts for MSA as well as DSP
llvm-svn: 191496
2013-09-27 09:44:59 +00:00
Daniel Sanders f4f1a872ca [mips][msa] Added missing check in performSRACombine
Reviewers: jacksprat, dsanders

Reviewed By: dsanders

Differential Revision: http://llvm-reviews.chandlerc.com/D1755

llvm-svn: 191495
2013-09-27 09:25:29 +00:00
Puyan Lotfi 74e38de492 First check in. Modified a comment.
llvm-svn: 191491
2013-09-27 07:36:10 +00:00
Craig Topper dbe8b7d236 Put HasAVX512 predicate on some patterns to properly disable them when AVX512 isn't enabled. Currently it works simply because the SSE and AVX version of the same patterns are checked first in the DAG isel table.
llvm-svn: 191490
2013-09-27 07:20:47 +00:00
Craig Topper 8f14de8f32 Switch HasAVX to UseAVX in one spot to ensure that AVX512 form of VINSERTPS is used in AVX512 mode.
llvm-svn: 191489
2013-09-27 07:16:24 +00:00
Craig Topper c6a1aac735 Removal some duplicate patterns.
llvm-svn: 191488
2013-09-27 07:11:17 +00:00
Yunzhong Gao 4467f33e3c Fixing Intel format of the vshufpd instruction.
Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759

llvm-svn: 191481
2013-09-27 01:44:23 +00:00
Rui Ueyama 333d28a0bb Revert "llvm-objdump: Dump COFF import table if -private-headers option is given."
This reverts commit r191472 because it's failing on BE machine.

llvm-svn: 191480
2013-09-27 01:29:36 +00:00
Rui Ueyama 6b27fe648a Fix another -Wnon-pod-varargs error in r191472.
llvm-svn: 191474
2013-09-27 00:53:07 +00:00
Rui Ueyama 9a80df5537 Fix -Wnon-pod-varargs error in r191472.
llvm-svn: 191473
2013-09-27 00:20:53 +00:00
Rui Ueyama 5b1adbaad9 llvm-objdump: Dump COFF import table if -private-headers option is given.
This is a patch to add capability to llvm-objdump to dump COFF Import Table
entries, so that we can write tests for LLD checking Import Table contents.

llvm-objdump did not print anything but just file name if the format is COFF
and -private-headers option is given. This is a patch adds capability for
dumping DLL Import Table, which is specific to the COFF format.

In this patch I defined a new iterator to iterate over import table entries.
Also added a few functions to COFFObjectFile.cpp to access fields of the entry.

Differential Revision: http://llvm-reviews.chandlerc.com/D1719

llvm-svn: 191472
2013-09-27 00:07:01 +00:00
Adrian Prantl 6ac40036f1 MCParser/Debug info: Accept line number 0 as a legitimate value, since
CFE produces it to indicate artificial locations.
c.f.: DWARF standard, Table 6.2:
line -- An unsigned integer indicating a source line number. Lines are numbered beginning at 1. The compiler may emit the value 0 in cases where an instruction cannot be attributed to any source line.

llvm-svn: 191471
2013-09-26 23:37:11 +00:00
Jack Carter cb8b40b08d [mips][msa] Direct Object Emission for 3RF instructions.
Patch by Matheus Almeida

llvm-svn: 191461
2013-09-26 21:31:43 +00:00
Jack Carter 142ec8283d [mips][msa] Updates encoding of 3RF instructions to match the latest revision of the MSA spec (1.06).
This does not affect any of the existing output.

Patch by Matheus Almeida

llvm-svn: 191460
2013-09-26 21:18:57 +00:00
Weiming Zhao 286304a317 Fix PR 17372: Emitting PLD for stack address for ARM Thumb2
t2PLDi12, t2PLDi8, t2PLDs was omitted in Thumb2InstrInfo.
This patch fixes it.

llvm-svn: 191441
2013-09-26 17:25:10 +00:00
Bill Schmidt cea1596205 [PowerPC] Fix PR17354: Generate nop after local calls for PIC code.
When generating code for shared libraries, even local calls may be
intercepted, so we need a nop after the call for the linker to fix up the
TOC.  Test case adapted from the one provided in PR17354.

llvm-svn: 191440
2013-09-26 17:09:28 +00:00
Andrea Di Biagio 549d6605a0 Revert r191393 since it caused pr17380.
llvm-svn: 191438
2013-09-26 16:54:01 +00:00
Venkatraman Govindaraju 4c0cdd734c [Sparc] Implements exception handling in SPARC with DwarfCFI.
llvm-svn: 191432
2013-09-26 15:11:00 +00:00
Venkatraman Govindaraju 3816d43a9a Implements parsing and emitting of .cfi_window_save in MC.
llvm-svn: 191431
2013-09-26 14:49:40 +00:00
Amara Emerson b4ad2f396a [ARM] Use the load-acquire/store-release instructions optimally in AArch32.
Patch by Artyom Skrobov.

llvm-svn: 191428
2013-09-26 12:22:36 +00:00
David Majnemer 7137420d94 PPC: Allow partial fills in writeNopData()
When asked to pad an irregular number of bytes, we should fill with
zeros.  This is consistent with the behavior specified in the AIX
Assembler Language Reference as well as other LLVM and binutils
assemblers.

N.B. There is a small deviation from binutils' PPC assembler:
when handling pads which are greater than 4 bytes but not mod 4,
binutils will not emit any NOP sequences at all and only use zeros.
This may or may not be a bug but there is no excellent rationale as to
why that behavior is important to emulate.  If that behavior is needed,
we can change writeNopData() to behave in the same way.

This fixes PR17352.

llvm-svn: 191426
2013-09-26 09:18:48 +00:00
Renato Golin 22a2d963b9 Add links to cross-compilation docs from getting started
llvm-svn: 191425
2013-09-26 08:57:07 +00:00
Andrew Trick 71e8bb6d1d Added temp flag -misched-bench for staging in default changes.
llvm-svn: 191423
2013-09-26 05:53:35 +00:00
Andrew Trick 6f5aad7a24 whitespace
llvm-svn: 191422
2013-09-26 05:53:31 +00:00
David Majnemer 08249a31b2 PPC: Do not introduce ISD nodes for fctid and fctiw
llvm-svn: 191421
2013-09-26 05:22:11 +00:00
David Majnemer 6ad26d3364 PPC: Add support for fctid and fctiw
Encodings were checked against the Power ISA documents and double
checked against binutils.

This fixes PR17350.

llvm-svn: 191419
2013-09-26 04:11:24 +00:00
Jack Carter 3eb663b037 [mips][msa] Direct Object Emission for 3R instructions.
This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class.
 
Patch by Matheus Almeida

llvm-svn: 191415
2013-09-26 00:09:46 +00:00
Jack Carter 77551abef4 [mips][msa] Updates encoding of 3R instructions to match the latest revision of the MSA spec (1.06).
Internal changes only.
 
Patch by Matheus Almeida

llvm-svn: 191414
2013-09-26 00:02:44 +00:00
Jack Carter 3381298227 [mips][msa] Direct Object Emission for 2RF instructions.
Patch by Matheus Almeida

llvm-svn: 191413
2013-09-25 23:56:25 +00:00
Jack Carter 5dc8ac92b9 [mips][msa] Direct Object Emission support for the MSA instruction set.
In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions.

Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function).

Patch by Matheus Almeida

llvm-svn: 191412
2013-09-25 23:50:44 +00:00
Jack Carter 56c681eb7f [mips][msa] Updates encoding of 2RF instructions to match the latest revision of the MSA spec (1.06).
This only changes internal encodings and doesn't affect output.


Patch by Matheus Almeida

llvm-svn: 191411
2013-09-25 23:42:03 +00:00
Weiming Zhao 2052f4843b Fix PR 17368: disable vector mul distribution for square of add/sub for ARM
Generally, it is desirable to distribute (a + b) * c to a*c + b*c for
ARM with VMLx forwarding, where a, b and c are vectors.
However, for (a + b)*(a + b), distribution will result in one extra
instruction.
With distribution:
  x = a + b (add)
  y = a * x (mul)
  z = y + b * y (mla)

Without distribution:
  x = a + b (add)
  z = x * x (mul)

This patch checks if a mul is a square of add/sub. If yes, skip
distribution.

llvm-svn: 191410
2013-09-25 23:12:06 +00:00
Eric Christopher a9e303e746 Add gnu pubsections as options to llvm-dwarfdump.
Argument spelling feedback welcome.

llvm-svn: 191409
2013-09-25 23:02:44 +00:00
Eric Christopher 4c7e6ba7d3 Dump the normal dwarf pubtypes section as well.
llvm-svn: 191408
2013-09-25 23:02:41 +00:00
Eric Christopher 0de5359e20 Unify pubsection/gnu pubsection printing.
llvm-svn: 191407
2013-09-25 23:02:36 +00:00
Josh Magee 06ffaee67e Test commit. Removed trailing whitespace.
llvm-svn: 191402
2013-09-25 22:07:48 +00:00
Eric Christopher a88fd7fdb6 Slight formatting change for pubnames/pubtypes output.
llvm-svn: 191401
2013-09-25 21:17:37 +00:00
Reed Kotler a6ce797f05 Fix a bad typo in the inline assembly code for mips16 pic fp stubs
and make one cosmetic cleanup to make it look the same as gcc
in this area; adjusting test cases.

llvm-svn: 191400
2013-09-25 20:58:50 +00:00