f5e8c86424
Minor optimizations. DenseMap::begin() is surprisingly slow on an empty map.
...
llvm-svn: 103940
2010-05-17 15:30:37 +00:00
6649cdaa23
Extract spill cost calculation to a new method, and use definePhysReg() to clear
...
out aliases when allocating. Clean up allocVirtReg().
Use calcSpillCost() to allow more aggressive hinting. Now the hint is always
taken unless blocked by a reserved register. This leads to more coalescing,
lower register pressure, and less spilling.
llvm-svn: 103939
2010-05-17 15:30:32 +00:00
188855abef
Remove unused member variable.
...
llvm-svn: 103936
2010-05-17 09:47:55 +00:00
7d22a81b61
Only use clairvoyance when defining a register, and then only if it has one use.
...
This makes allocation independent on the ordering of use-def chains.
llvm-svn: 103935
2010-05-17 04:50:57 +00:00
f915d14955
Eliminate a hash table probe when killing virtual registers.
...
llvm-svn: 103934
2010-05-17 03:26:09 +00:00
edd3d9db13
Execute virtreg kills immediately instead of after processing all uses.
...
This is safe to do because the physreg has been marked UsedInInstr and the kill flag will be set on the last operand using the virtreg if there are more then one.
llvm-svn: 103933
2010-05-17 03:26:06 +00:00
e07a408afc
Sprinkle superregister <imp-def> and <imp-kill> operands when dealing with subregister indices.
...
llvm-svn: 103931
2010-05-17 02:49:21 +00:00
1069a09691
Now that we don't keep live registers across calls, there is not reason to go
...
through the very long list of call-clobbered registers. We just assume all
registers are clobbered.
llvm-svn: 103930
2010-05-17 02:49:18 +00:00
397068de06
Boldly attempt consistent capitalization. Functional changes unintended.
...
llvm-svn: 103929
2010-05-17 02:49:15 +00:00
68b1bbe66a
Assume that we'll handle mangling the symbols earlier and just put the
...
symbol to the file as we have it. Simplifies out tbss handling.
llvm-svn: 103928
2010-05-17 02:13:02 +00:00
8044c989d1
Spill and kill all virtual registers across a call.
...
Debug code doesn't use callee saved registers anyway, and the code is simpler this way. Now spillVirtReg always kills, and the isKill parameter is not needed.
llvm-svn: 103927
2010-05-17 02:07:32 +00:00
d2ef1fbc82
Reduce hashtable probes by using DenseMap::insert() for lookup.
...
llvm-svn: 103926
2010-05-17 02:07:29 +00:00
fb43e065a4
Make MBB a class member instead of passing it around everywhere.
...
llvm-svn: 103925
2010-05-17 02:07:22 +00:00
166a7993ba
Yes, if the redef is a copy, update the old val# with the copy. But make sure to clear the copy field if the redef is not a copy.
...
llvm-svn: 103922
2010-05-17 01:47:47 +00:00
5a2809cbd8
No reason not to run the NEON domain croassing fix up pass in thumb2 mode.
...
llvm-svn: 103917
2010-05-17 01:11:46 +00:00
2ef974ee0e
Revert 103911; it broke a test that expects bitconvert
...
<1xi64> -> i64 to work in MMX registers on hosts where -no-sse
is the default (not mine). The right thing is
to accept this and make i64->f64 conversions go through memory,
but I don't have time right now.
llvm-svn: 103914
2010-05-16 20:19:04 +00:00
fc1492d71b
Make x86-64 64-bit bitconvert work when SSE is not available.
...
(This worked as of about 6 months ago and I didn't track down
exactly what broke it; I think this fix is appropriate.)
llvm-svn: 103911
2010-05-16 18:22:38 +00:00
497d831966
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
...
llvm-svn: 103903
2010-05-16 09:15:36 +00:00
8f35fabbc1
Add support for thiscall calling convention.
...
Patch by Charles Davis and Steven Watanabe!
llvm-svn: 103902
2010-05-16 09:08:45 +00:00
4c719c4515
Generalize the ARM DAG combiner of mul with constants to all power-of-two cases.
...
llvm-svn: 103901
2010-05-16 08:54:20 +00:00
298e6b82eb
Model vst lane instructions with REG_SEQUENCE.
...
llvm-svn: 103898
2010-05-16 03:27:48 +00:00
3a366a88f2
Fix uint64->{float, double} conversion to do rounding correctly in 32-bit.
...
The implementation in LegalizeIntegerTypes to handle this as
sint64->float + appropriate power of 2 is subject to double rounding,
considered incorrect by numerics people. Use this implementation only
when it is safe. This leads to using library calls in some cases
that produced inline code before, but it's correct now.
(EVTToAPFloatSemantics belongs somewhere else, any suggestions?)
Add a correctly rounding (though not particularly fast) conversion
that uses X87 80-bit computations for x86-32.
7885399, 5901940. This shows up in gcc.c-torture/execute/ieee/rbug.c
in the gcc testsuite on some platforms.
llvm-svn: 103883
2010-05-15 18:51:12 +00:00
bb4656c05e
Improve assertion messages.
...
llvm-svn: 103882
2010-05-15 18:38:02 +00:00
1bf28a128b
Some cheap DAG combine goodness for multiplication with a particular constant.
...
This can be extended later on to handle more "complex" constants.
llvm-svn: 103881
2010-05-15 18:16:59 +00:00
2b7aace2e0
"trap" pseudo-op turned out to be apple-local.
...
Temporary emit it as raw bytes until it will be added to binutils as well.
llvm-svn: 103878
2010-05-15 17:19:20 +00:00
9e01b615a4
improve portability to systems that don't have round, patch by
...
Evzen Muller!
llvm-svn: 103877
2010-05-15 17:11:55 +00:00
93cd0f1c89
improve portability to systems that don't have powf/modf (e.g. solaris 9)
...
patch by Evzen Muller!
llvm-svn: 103876
2010-05-15 17:10:24 +00:00
75142e6bfc
Fix an GCC warning that seems to have actually caught a bug (!!!) in
...
a condition's grouping. Every other use of Allocatable.test(Hint) groups it the
same way as it is indented, so move the parentheses to agree with that
grouping.
llvm-svn: 103869
2010-05-15 10:23:23 +00:00
9e688cbcc9
Model 128-bit vld lane with REG_SEQUENCE.
...
llvm-svn: 103868
2010-05-15 07:53:37 +00:00
84ce290822
Calculate liveness on the fly for local registers.
...
When working top-down in a basic block, substituting physregs for virtregs, the use-def chains are kept up to date. That means we can recognize a virtreg kill by the use-def chain becoming empty.
This makes the fast allocator independent of incoming kill flags.
llvm-svn: 103866
2010-05-15 06:09:08 +00:00
b35818eb25
Teach the always inliner to release its inline cost estimates, like the basic
...
inliner did in r103653. Why does the always inliner even bother with cost
estimates anyways?
llvm-svn: 103858
2010-05-15 04:26:25 +00:00
002a45eb64
Clean up, no functional change.
...
llvm-svn: 103857
2010-05-15 03:41:58 +00:00
3d214cdfaf
v4i64 and v8i64 are only synthesizable when NEON is available.
...
llvm-svn: 103855
2010-05-15 02:20:21 +00:00
4cad68eb34
Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
...
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.
llvm-svn: 103854
2010-05-15 02:18:07 +00:00
0cbd11dfb2
Model 64-bit lane vld with REG_SEQUENCE.
...
llvm-svn: 103851
2010-05-15 01:36:29 +00:00
e26e56e72b
A partial re-def instruction may be a copy.
...
llvm-svn: 103850
2010-05-15 01:35:44 +00:00
8c2d062ea6
Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
...
instructions.
e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12
After REG_SEQUENCE is eliminated, we are left with:
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible,
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.
llvm-svn: 103835
2010-05-14 23:21:14 +00:00
cb78e5558b
Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE.
...
llvm-svn: 103833
2010-05-14 22:54:52 +00:00
88fb253562
Fast ISel trivially coalesces away no-op casts, so check for this when
...
setting kill flags.
llvm-svn: 103832
2010-05-14 22:53:18 +00:00
089e9421d2
Don't bother spilling before a return
...
llvm-svn: 103831
2010-05-14 22:40:43 +00:00
cdef6bc8de
RegAllocLocal can count copies too
...
llvm-svn: 103830
2010-05-14 22:40:40 +00:00
0160e55893
SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and
...
replace the check with the appropriate predicate. Modify the testcase to reflect
the correct code. (It should be saving callee-saved registers on the stack
allocated by the calling fuction.)
llvm-svn: 103829
2010-05-14 22:17:42 +00:00
b16013936b
Track allocatable instead of reserved regs, and never take an unallocatable hint.
...
llvm-svn: 103828
2010-05-14 22:02:56 +00:00
2f277c866d
Don't set kill flags for instructions which the scheduler has cloned.
...
llvm-svn: 103827
2010-05-14 22:01:14 +00:00
062a97f0f6
BR is a barrier.
...
llvm-svn: 103826
2010-05-14 22:00:27 +00:00
1713d95874
Several tail call tests apparently rely upon this being "adjusts stack" instead
...
of "has calls". That's probably wrong, but it needs further
investigation. Revert to the original behavior until this is settled.
llvm-svn: 103824
2010-05-14 21:58:35 +00:00
e68b814c8c
Avoid scanning the long tail of physreg operands on calls
...
llvm-svn: 103823
2010-05-14 21:55:52 +00:00
36debf8046
Do not forget to mark prcessed arguments.
...
llvm-svn: 103822
2010-05-14 21:55:50 +00:00
6c038e33e9
Count coalesced copies
...
llvm-svn: 103821
2010-05-14 21:55:50 +00:00
33af4fcdea
Allow virtreg redefines when verifying for RegAllocFast
...
llvm-svn: 103820
2010-05-14 21:55:44 +00:00
e9ac7ad68c
This should happen if there are no calls, not if it just doesn't adjust the
...
stack.
llvm-svn: 103813
2010-05-14 21:38:44 +00:00
db4bc54c4f
Revert r103804. The comment is correct.
...
llvm-svn: 103808
2010-05-14 21:28:24 +00:00
866b74ba8b
Remove trailing whitespace
...
llvm-svn: 103807
2010-05-14 21:20:46 +00:00
d772bdeb7e
80 column and trailing whitespace cleanup
...
llvm-svn: 103806
2010-05-14 21:19:48 +00:00
25749ad5c2
add cmd line option to leave dbgvalues in during post-RA sceduling. Useful
...
while debugging what's mishandled about them in the post-RA pass.
llvm-svn: 103805
2010-05-14 21:18:04 +00:00
7bf4bae5dc
Fix comment.
...
llvm-svn: 103804
2010-05-14 21:17:29 +00:00
95f6ebcb37
Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what
...
the variable actually tracks.
N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.
llvm-svn: 103802
2010-05-14 21:14:32 +00:00
35dd005d22
Lowering of atomic instructions can result in operands being
...
used more than once. If ISel had put a kill flag on one of them,
it's not valid to transfer the kill flag to each new instance.
llvm-svn: 103799
2010-05-14 21:01:44 +00:00
e0a94bfe9f
Add support to preserve type info for the variables that are removed by the optimizer.
...
llvm-svn: 103798
2010-05-14 21:01:35 +00:00
670492c8ee
When verifying two-address instructions, check the following:
...
- Kill is implicit when use and def registers are identical.
- Only virtual registers can differ.
Add a -verify-fast-regalloc to run the verifier before the fast allocator.
llvm-svn: 103797
2010-05-14 20:28:32 +00:00
7bc111f5a9
Fix so "int3" is correctly accepted, added "into" and fixed "int" with an
...
argument, like "int $4", to not get an Assertion error.
llvm-svn: 103791
2010-05-14 19:16:02 +00:00
cfa7d02d6e
Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.
...
llvm-svn: 103790
2010-05-14 18:54:59 +00:00
2493ddfe42
MC/Mach-O/x86_64: Darwin's special "signed_N" relocation types should only be
...
used to replace a normal relocation, not a reference to a GOT entry.
llvm-svn: 103789
2010-05-14 18:53:40 +00:00
4d5c1061e3
Simplify the handling of physreg defs and uses in RegAllocFast.
...
This adds extra security against using clobbered physregs, and it adds kill
markers to physreg uses.
llvm-svn: 103784
2010-05-14 18:03:25 +00:00
30e3db2ba3
Set isTerminator on TRAP instructions.
...
llvm-svn: 103778
2010-05-14 16:46:02 +00:00
c56ca22616
Don't use isBarrier for the PowerPC sync instruction. isBarrier is for
...
control barriers, not memory ordering barriers.
llvm-svn: 103777
2010-05-14 16:42:16 +00:00
02d9947e60
Add mayLoad and mayStore flags to instructions which missed them.
...
llvm-svn: 103776
2010-05-14 16:34:55 +00:00
148e876ac2
XFAIL the test I added with vg_leak, apparently it is the first and only llc
...
-filetype=obj test, and -filetype=obj leaks a few objects. Added a FIXME, we
need to sort out the ownership model for the various MC objects.
llvm-svn: 103769
2010-05-14 07:47:51 +00:00
3439ed6324
Inline Asm: Ensure buffer is newline terminated to match how the text is printed.
...
- This is a hack, but I can't decide the best place to handle this. Chris?
llvm-svn: 103765
2010-05-14 04:31:50 +00:00
ceb5a7ada2
Enable opportunistic coalescing
...
llvm-svn: 103764
2010-05-14 04:30:51 +00:00
cd67c21407
Added a QQQQ register file to model 4-consecutive Q registers.
...
llvm-svn: 103760
2010-05-14 02:13:41 +00:00
9fb6bb07ca
Add AsmParser support for darwin tbss directive.
...
Nothing uses this yet.
llvm-svn: 103757
2010-05-14 01:50:28 +00:00
bc81885ff7
Fix a couple of typos.
...
llvm-svn: 103756
2010-05-14 01:38:54 +00:00
4bce748aa2
MC: Switch to completely lazy layout.
...
- The eliminates the last major algorithmic problem with MC.
llvm-svn: 103754
2010-05-14 00:51:14 +00:00
9abade1017
MC: Extend MCAsmLayout to explicitly track which fragments have been layed out, and enforce several invariants to LayoutFragment to ensure we only do layout in a sensible order.
...
llvm-svn: 103753
2010-05-14 00:37:21 +00:00
3eedc26e18
MC: Implicitly assign section addresses when the previous fragment is layed out.
...
llvm-svn: 103752
2010-05-14 00:37:17 +00:00
8f9d2266e6
MC: Switch MCFragment to storing the layout order index, not its index in the file.
...
llvm-svn: 103751
2010-05-14 00:37:14 +00:00
a99a23b061
MC: Change LayoutSection() to only do the section initializiation.
...
Also, elimminate MCAsmLayout::set*, which are no longer needed.
llvm-svn: 103750
2010-05-14 00:37:11 +00:00
ca21cc8b13
Fix comments.
...
llvm-svn: 103749
2010-05-14 00:21:45 +00:00
68c235bd4d
Trust kill flags from isel and later passes.
...
llvm-svn: 103748
2010-05-14 00:02:23 +00:00
41f8dc897e
Fix an embarrassing runtime regression for RegAllocFast.
...
This loop is quadratic in the capacity for a DenseMap:
while(!map.empty())
map.erase(map.begin());
Instead we now do a normal begin() - end() iteration followed by map.clear().
That also has the nice sideeffect of shrinking the map capacity on demand.
llvm-svn: 103747
2010-05-14 00:02:20 +00:00
670a4104a9
Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers.
...
llvm-svn: 103746
2010-05-13 23:55:47 +00:00
1ae94b9394
Implement a correct ui64->f32 conversion. The old
...
one was subject to double rounding in extreme cases.
llvm-svn: 103744
2010-05-13 23:50:42 +00:00
d74a564feb
Clean up RegAllocFast debug output
...
llvm-svn: 103739
2010-05-13 20:43:17 +00:00
b9f6ac094a
MC: Move Layout{Fragment,Section} into MCAsmLayout, and add LayoutFile().
...
llvm-svn: 103738
2010-05-13 20:40:12 +00:00
c90f51c00b
Teach MachineLICM and MachineSink how to clear kill flags conservatively
...
when they move instructions.
llvm-svn: 103737
2010-05-13 20:34:42 +00:00
2ca1bd119e
Add comment about the pseudo registers QQ, each of which is a pair of Q registers.
...
llvm-svn: 103731
2010-05-13 20:02:08 +00:00
208dc08c2b
Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers.
...
Do not use those for Thumb1 functions.
llvm-svn: 103730
2010-05-13 19:58:24 +00:00
82135e5a2f
CMake: fixes 64 bit Visual Studio IDE build. Fixes bug 4936.
...
Patch by Dimitry Andric!
llvm-svn: 103727
2010-05-13 19:34:06 +00:00
7767d2747b
Add a utility function for conservatively clearing kill flags, and make
...
use of it in MachineCSE.
llvm-svn: 103726
2010-05-13 19:24:00 +00:00
5b510c1474
An Instruction has a trivial kill only if its use is in the same
...
basic block.
llvm-svn: 103725
2010-05-13 19:19:32 +00:00
454ea716a3
MC: Factor out MCAssembler::ComputeFragmentSize.
...
llvm-svn: 103724
2010-05-13 18:35:06 +00:00
484c6fc825
MC: Add section layout order indices to MCSectionData.
...
llvm-svn: 103715
2010-05-13 15:17:26 +00:00
aa8bd69886
MC: Move ordinal calculation, to make sure fragments synthesized for layout get assigned ordinals properly.
...
llvm-svn: 103711
2010-05-13 08:43:37 +00:00
e73353c720
MC: Create dummy fragments to avoid ever having empty sections, which simplifies layout.
...
llvm-svn: 103710
2010-05-13 08:43:34 +00:00
e8845ef4db
MC: Add MCAsmLayout::FragmentReplaced() helper function.
...
llvm-svn: 103709
2010-05-13 08:43:31 +00:00
449df9698f
Properly set thread-local flag on globals during cpp emission
...
llvm-svn: 103702
2010-05-13 07:41:57 +00:00
2b3cbac0ee
Remove heinous tabs.
...
llvm-svn: 103700
2010-05-13 06:45:13 +00:00
d3c6dfe853
Replace the core comparison login in merge functions. We can now merge
...
vector<>::push_back() in:
int foo(vector<int> &a, vector<unsigned> &b) {
a.push_back(10);
b.push_back(11);
}
to two calls to the same push_back function, or fold away the two copies of
push_back() in:
struct T { int; };
struct S { char; };
vector<T*> t;
vector<S*> s;
void f(T *x) { t.push_back(x); }
void g(S *x) { s.push_back(x); }
but leave f() and g() separate, since they refer to two different global
variables.
llvm-svn: 103698
2010-05-13 05:48:45 +00:00
5a93253fc8
Fix -Asserts warning.
...
llvm-svn: 103697
2010-05-13 03:50:50 +00:00
Jakob Stoklund Olesen