c5e0ed109d
[Hexagon] Add trap1 instruction
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llvm-svn: 326492
2018-03-01 21:54:08 +00:00
22a21d4c5d
[Hexagon] Add guest registers
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llvm-svn: 326450
2018-03-01 17:03:26 +00:00
a8ab1b75cb
[Hexagon] Add support for Hexagon V65
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llvm-svn: 320404
2017-12-11 18:57:54 +00:00
8c53c95137
[Hexagon] Mark vector loads as predicable, update instruction mappings
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All loads of form V6_vL32b_{,cur,nt,tmp,nt_cur,nt_tmp}_{ai,pi,ppu} are
predicable on v62 (but not on v60). Mark them all as predicable in the
instruction definitions, and handle the v60 case in HII::isPredicable.
llvm-svn: 316098
2017-10-18 17:36:46 +00:00
557729761c
[Hexagon] Switch to parameterized register classes for HVX
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This removes the duplicate HVX instruction set for the 128-byte mode.
Single instruction set now works for both modes (64- and 128-byte).
llvm-svn: 313362
2017-09-15 15:46:05 +00:00
9c084fc55d
[Hexagon] Add intrinsics for data cache operations
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This is the LLVM part, adding definitions for
void @llvm.hexagon.Y2.dccleana(i8*)
void @llvm.hexagon.Y2.dccleaninva(i8*)
void @llvm.hexagon.Y2.dcinva(i8*)
void @llvm.hexagon.Y2.dczeroa(i8*)
void @llvm.hexagon.Y4.l2fetch(i8*, i32)
void @llvm.hexagon.Y5.l2fetch(i8*, i64)
The clang part will follow.
llvm-svn: 308032
2017-07-14 15:58:48 +00:00
2af5037d34
[Hexagon] Use automatically-generated scheduling information for HVX
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Patch by Jyotsna Verma.
llvm-svn: 302073
2017-05-03 20:10:36 +00:00
4a1c3f0aaa
[Hexagon] Replace CVI_VM_CUR_LD type with CVI_VM_LD
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A .cur instruction can be identified by checking isCVINew() && mayLoad().
Patch by Colin LeMahieu.
llvm-svn: 301829
2017-05-01 20:16:35 +00:00
058abf1a4a
[Hexagon] Change the vector scaling for vector offsets
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Keep full offset value on MI-level instructions, but have it scaled down
in the MC-level instructions.
llvm-svn: 299664
2017-04-06 17:28:21 +00:00
1aaf41af54
[Hexagon] Start using regmasks on calls
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Reapply r295371 with a fix for the Windows bot failures.
llvm-svn: 295504
2017-02-17 22:14:51 +00:00
6eab4044b9
Revert "[Hexagon] Start using regmasks on calls"
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This reverts commit r295371.
It broke windows bots:
http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio
llvm-svn: 295402
2017-02-17 02:08:58 +00:00
fb9503c080
[Hexagon] Start using regmasks on calls
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All the cool targets are doing it...
llvm-svn: 295371
2017-02-16 20:25:23 +00:00
f9015e62fd
[Hexagon] Introduce Hexagon V62
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llvm-svn: 294805
2017-02-10 23:46:45 +00:00
a72fad980c
[Hexagon] Replace instruction definitions with auto-generated ones
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llvm-svn: 294753
2017-02-10 15:33:13 +00:00
Krzysztof Parzyszek