50805a0b83
[AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VI
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See bug 32621: https://bugs.llvm.org//show_bug.cgi?id=32621
Reviewers: vpykhtin, SamWot, arsenm
Differential Revision: https://reviews.llvm.org/D35902
llvm-svn: 310251
2017-08-07 13:14:12 +00:00
4685b70a77
[AMDGPU] resubmit r308179: CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions
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llvm-svn: 308310
2017-07-18 14:23:26 +00:00
9a7442d088
Revert r308179 which causes tablegen to spam stderr on every build.
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Original commit log:
[AMDGPU] CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions
llvm-svn: 308270
2017-07-18 07:40:47 +00:00
a2b9e2f755
[AMDGPU] CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions
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Summary:
Previously, CodeGen checked first src operand type to determine if omod is supported by instruction. This isn't correct for some instructions: e.g. V_CMP_EQ_F32 has floating-point src operands but desn't support omod.
Changed .td files to check if dst operand instead of src operand.
Reviewers: arsenm, vpykhtin
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D35350
llvm-svn: 308179
2017-07-17 14:23:38 +00:00
dc4ac823ec
[AMDGPU][MC] Corrected V_*QSAD* instructions to check that dest register is different than any of the src
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See Bug 33279: https://bugs.llvm.org//show_bug.cgi?id=33279
Reviewers: artem.tamazov, vpykhtin
Differential Revision: https://reviews.llvm.org/D34003
llvm-svn: 305915
2017-06-21 14:41:34 +00:00
06f8d39424
AMDGPU : Fix mqsad_u32_u8 instruction incorrect data type.
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Differential Revision: http://reviews.llvm.org/D23700
llvm-svn: 281081
2016-09-09 19:31:51 +00:00
d93a34f714
[AMDGPU][llvm-mc] Support for 32-bit inline literals
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Patch by: Artem Tamazov
Summary:
Note: Support for 64-bit inline literals TBD
Added: Support of abs/neg modifiers for literals (incomplete; parsing TBD).
Added: Some TODO comments.
Reworked/clarity: rename isInlineImm() to isInlinableImm()
Reworked/robustness: disallow BitsToFloat() with undefined value in isInlinableImm()
Reworked/reuse: isSSrc32/64(), isVSrc32/64()
Tests added.
Reviewers: tstellarAMD, arsenm
Subscribers: vpykhtin, nhaustov, SamWot, arsenm
Projects: #llvm-amdgpu-spb
Differential Revision: http://reviews.llvm.org/D17204
llvm-svn: 261559
2016-02-22 19:17:56 +00:00
45bb48ea19
R600 -> AMDGPU rename
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llvm-svn: 239657
2015-06-13 03:28:10 +00:00
Dmitry Preobrazhensky