Commit Graph

3121 Commits

Author SHA1 Message Date
Juergen Ributzka 05c5a93283 [weak vtables] Place class definitions into anonymous namespaces to prevent weak vtables.
This patch places class definitions in implementation files into anonymous
namespaces to prevent weak vtables. This eliminates the need of providing an
out-of-line definition to pin the vtable explicitly to the file.

llvm-svn: 195092
2013-11-19 03:08:35 +00:00
Juergen Ributzka d12ccbd343 [weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

llvm-svn: 195064
2013-11-19 00:57:56 +00:00
Alexey Samsonov 49109a279c Revert r194865 and r194874.
This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
  Base *foo = new Child();
  delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.

llvm-svn: 194997
2013-11-18 09:31:53 +00:00
Ahmed Bougacha 31377593bc TableGen: Generate an enum for all named Operand types in tblgen'd InstrInfo.
llvm-svn: 194978
2013-11-17 21:24:41 +00:00
Owen Anderson b88cc2fc52 Small improvement to InstrinsicEmitter::EmitAttributes. This change removes the “pushing” and “clearing” of the SmallVector and instead uses const arrays to pass the attributeKinds to AttributeSet::get .
Patch by Aditya Nandakumar.

llvm-svn: 194899
2013-11-16 00:20:01 +00:00
Juergen Ributzka dbedae89b9 [weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

llvm-svn: 194865
2013-11-15 22:34:48 +00:00
Elena Demikhovsky dacddb0bab AVX-512: added VPCONFLICT instruction and intrinsics,
added EVEX_KZ to tablegen

llvm-svn: 193959
2013-11-03 13:46:31 +00:00
Andrew Trick 74f4c749cf Lower stackmap intrinsics directly to their target opcode in the DAG builder.
llvm-svn: 193769
2013-10-31 17:18:24 +00:00
Andrew Trick a2efd99bdf Enable variable arguments support for intrinsics.
llvm-svn: 193766
2013-10-31 17:18:11 +00:00
Andrew Trick d4d1d9c06e whitespace
llvm-svn: 193765
2013-10-31 17:18:07 +00:00
Ahmed Bougacha a70ecdc3ac TableGen: remove unused variable.
llvm-svn: 193527
2013-10-28 18:19:04 +00:00
Ahmed Bougacha 141075110c TableGen: Refactor DAG patterns to enable parsing one pattern at a time.
llvm-svn: 193526
2013-10-28 18:07:21 +00:00
Ahmed Bougacha bd2140018b TableGen: Refactor AsmWriterEmitter to keep AsmWriterInsts.
These used to be referenced by the CGI->AWI map (in AsmWriterEmitter), but
stored in a vector local to EmitPrintInstruction. Move the vector to
AsmWriterEmitter too.

llvm-svn: 193525
2013-10-28 18:07:17 +00:00
Peter Collingbourne a5906f06aa Typo.
llvm-svn: 193043
2013-10-20 03:19:25 +00:00
Craig Topper a422b09ae3 Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.
llvm-svn: 192567
2013-10-14 04:55:01 +00:00
Craig Topper 88adf2a49c Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly.
llvm-svn: 192525
2013-10-12 05:41:08 +00:00
Craig Topper aab53e7785 Mark some more instructions as CodeGenOnly. Remove filters from the disassembler.
llvm-svn: 192522
2013-10-12 04:46:18 +00:00
Will Dietz 981af0021b Add missing #include's to cctype when using isdigit/alpha/etc.
llvm-svn: 192519
2013-10-12 00:55:57 +00:00
Craig Topper 81034928c6 Remove another unnecessary filter from the disassembler.
llvm-svn: 192425
2013-10-11 06:59:57 +00:00
Craig Topper e1ceeb40c1 Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables.
llvm-svn: 192339
2013-10-10 04:26:52 +00:00
Craig Topper 2d0d180ab4 More x86 disassembler filtering cleanup.
llvm-svn: 192279
2013-10-09 06:12:53 +00:00
Craig Topper 043d749ba3 Remove some old filters from the x86 disassembler table builder.
llvm-svn: 192275
2013-10-09 05:02:29 +00:00
Craig Topper a984729f8a Remove unneeded MMX instruction definition by moving pattern to an equivalent instruction definition and removing the filtering from the disassembler table building.
llvm-svn: 192175
2013-10-08 06:30:39 +00:00
Craig Topper 72c8cd7bc3 Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse.
llvm-svn: 192171
2013-10-08 05:53:50 +00:00
Craig Topper 07ad1b23bb Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead.
llvm-svn: 192090
2013-10-07 07:19:47 +00:00
Craig Topper 2658d89728 Add disassembler support for long encodings for INC/DEC in 32-bit mode.
llvm-svn: 192086
2013-10-07 04:28:06 +00:00
Craig Topper a1bbc323fa Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon.
llvm-svn: 192026
2013-10-05 05:38:16 +00:00
Craig Topper d9a6cc031d Revert r191940 to see if it fixes the build bots.
llvm-svn: 191941
2013-10-04 05:52:17 +00:00
Craig Topper a2efe9ebc6 Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon.
llvm-svn: 191940
2013-10-04 05:22:20 +00:00
Craig Topper 9e3e38ae3f Add XOP disassembler support. Fixes PR13933.
llvm-svn: 191874
2013-10-03 05:17:48 +00:00
Pete Cooper d54381749d Add v4f16 to supported value types.
This is useful for some ARM intrinsics such as VCVTN which does a <4 x float> <-> <4 x half> conversion.

llvm-svn: 191870
2013-10-03 03:29:21 +00:00
Rafael Espindola 44fee4e0eb Remove several unused variables.
Patch by Alp Toker.

llvm-svn: 191757
2013-10-01 13:32:03 +00:00
Richard Sandiford 28942d4ca0 Fix pattern sort in DAGISelEmitter.cpp
The old code skipped one of the sorting criteria if either pattern had
no types.  This could lead to cycles of the form X < Y, Y < Z, Z < X.

llvm-svn: 191735
2013-10-01 09:49:01 +00:00
Craig Topper 009de6015f Filter out repeated sections from the X86 disassembler modRMTable. Saves about ~43K from a released build. Unfortunately the disassembler tables are still upwards of 800K.
llvm-svn: 191652
2013-09-30 06:23:19 +00:00
Craig Topper ed59dd34fd Various x86 disassembler fixes.
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.

llvm-svn: 191649
2013-09-30 02:46:36 +00:00
Andrew Trick b6854d80e3 Mark the x86 machine model as incomplete. PR17367.
Ideally, the machinel model is added at the time the instructions are
defined. But many instructions in X86InstrSSE.td still need a model.

Without this workaround the scheduler asserts because x86 already has
itinerary classes for these instructions, indicating they should be
modeled by the scheduler. Since we use the new machine model for other
instructions, it expects a new machine model for these too.

llvm-svn: 191391
2013-09-25 18:14:12 +00:00
Craig Topper 0ac6f9fc6a Fix doxygen comments to use correct function name.
llvm-svn: 191356
2013-09-25 06:40:22 +00:00
Craig Topper 95198f4a94 Replace EVT with MVT in CodeGenDAGAPatterns.cpp.
llvm-svn: 191355
2013-09-25 06:37:18 +00:00
Craig Topper 9836f5995a Fix formatting to match coding standards.
llvm-svn: 191280
2013-09-24 06:21:04 +00:00
Jiangning Liu 63dc840fc5 Initial support for Neon scalar instructions.
Patch by Ana Pazos.

1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.

llvm-svn: 191263
2013-09-24 02:47:27 +00:00
Craig Topper 51617c3d2c Add missing index comments to the left side of the DAG ISel matcher table for each individual case of SwitchOpcode/Type.
llvm-svn: 191181
2013-09-22 23:18:50 +00:00
Benjamin Kramer 8817cca5ce Provide basic type safety for array_pod_sort comparators.
This makes using array_pod_sort significantly safer. The implementation relies
on function pointer casting but that should be safe as we're dealing with void*
here.

llvm-svn: 191175
2013-09-22 14:09:50 +00:00
Tim Northover 9c30f7a4ff TableGen: fix constness of new comparison function.
libc++ didn't seem to like a non-const call operator.

llvm-svn: 190797
2013-09-16 17:33:40 +00:00
Tim Northover c74e691c27 TableGen: give asm match classes deterministic order.
TableGen was sorting the entries in some of its internal data
structures by pointer. This order filtered through to the final
matching table and affected the diagnostics produced on bad assembly
occasionally.

It also turns out STL algorithms are ridiculously easy to misuse on
containers with custom order methods. (No bugs before, or now that I
know of, but plenty in the middle).

This should fix the sanitizer bot, which ends up with weird pointers.

llvm-svn: 190793
2013-09-16 16:43:19 +00:00
Tim Northover f9aaafd97b AsmMatcher: emit subtarget feature enum in deterministic order.
llvm-svn: 190792
2013-09-16 16:43:16 +00:00
Benjamin Kramer 7d6052687e Replace some unnecessary vector copies with references.
llvm-svn: 190770
2013-09-15 22:04:42 +00:00
Joey Gouly 0e76fa7df5 Add an instruction deprecation feature to TableGen.
The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.

The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
  ComplexDeprecationPredicate<"MCR">

would mean you would have to define the following function:
  bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
                             std::string &Info)

Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.

The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.

llvm-svn: 190598
2013-09-12 10:28:05 +00:00
Benjamin Kramer 17c17bce2a llvm-tblgen: Mangle operand replacements into the strings in printAliasInstr.
Cuts down the bloat in the AArch64 asm writer a bit.

llvm-svn: 190527
2013-09-11 15:42:16 +00:00
Benjamin Kramer d77143f89a llvm-tblgen: Stabilize subreg index tables.
Otherwise SequenceToOffsetTable will sort by pointer and becomes non-deterministic.

llvm-svn: 190514
2013-09-11 11:22:26 +00:00
Vincent Lejeune 7deccf0f06 TableGen: Enumerate Schedule Model too.
llvm-svn: 189839
2013-09-03 19:43:28 +00:00