Commit Graph

424785 Commits

Author SHA1 Message Date
Daniel Grumberg 504736cedf [clang][extract-api] Don't emit symbols prefixed with an underscore
These symbols are understood to not be used for client API consumption
by convention so they should not appear in the generated symbol graph.

Differential Revision: https://reviews.llvm.org/D125678
2022-05-25 19:02:18 +01:00
Krzysztof Parzyszek 23bb550eeb DWARFVerifier: Change vector of IntervalMap to vector of unique_ptrs
This is a workaround for compilation issue on FreeBSD. See comments in
https://reviews.llvm.org/rG0d8cb8b399ad for more information.

This fixes https://github.com/llvm/llvm-project/issues/55414.

Differential Revision: https://reviews.llvm.org/D125611
2022-05-25 10:59:46 -07:00
Matthias Springer 0ee1c0388c [mlir][bufferize] Remove hoisting functionality from One-Shot Bufferize
The same functionality is already provided by `-buffer-hoisting` and `-buffer-loop-hoisting`.

Differential Revision: https://reviews.llvm.org/D126251
2022-05-25 19:56:18 +02:00
Sanjay Patel d3187dd5f0 [SLP] add minimum test for miscompile (PR55688); NFC 2022-05-25 13:52:47 -04:00
Philip Reames be2cb824d0 [riscv] Remove mutation of prior vsetvli from insertion dataflow
This moves mutation entirely out of the main algorithm.

The immediate trigger is that we hit another case of the same issue I thought we'd fixed in 72925d9. It turns out we hadn't considered the cross block case.

As a brief summary, the issue being fixed is that if we mutate a previous vsetvli in phase 3, there's a possibility that some later use of that vsetvli changes "compatibility". In the cross_block_mutate test, this later vsetvli occurs in another block (and is thus visit order dependent too!). This causes us to fail strict asserts. (To be explicit, the current on by default workaround should compensate. It's only when we turn that off that we have problems.)

Now, I want to explicitly call out an alternate workaround. We could leave the mutation in phase 3, and simplify restrict it to the case where the previous vsetvli's GPR result is unused. That covers the case we've actually seen. (I'll note that codegen regressions with a simple form of this were significant. We might have to check specifically for the use outside block case to keep them reasonable, which complicates the workaround slightly.)

Personally, I'm at the point where I want the mutation pulled out just for robustness sake. I'm worried there's yet one more form of this bug we haven't thought about.

The other motivation for this change is that it does give us a couple of minor codegen wins. None appear to be hugely significant, but improvements never hurt right?

Differential Revision: https://reviews.llvm.org/D125270
2022-05-25 10:51:14 -07:00
Aaron Ballman 9368bf9023 Removing this as part of the revert done in 69da3b6aea
This appears to have been added in a follow-up commit that I missed.
2022-05-25 13:45:17 -04:00
Aaron Ballman 69da3b6aea Revert "[OpenMP] atomic compare fail : Parser & AST support"
This reverts commit 232bf8189e.

It broke the sanitize buildbot: https://lab.llvm.org/buildbot/#/builders/5/builds/24074

It also reproduces on Windows debug builds as a crash.
2022-05-25 13:34:34 -04:00
Mike Rice ba3f85390b [OpenMP] Add diagnostic for unterminated 'omp [begin] declare target'
Warns when end-of-file is reached without seeing all matching
'omp end declare target' directives. The diagnostic shows the
location of the related begin directive.

Differential Revision: https://reviews.llvm.org/D126331
2022-05-25 10:34:07 -07:00
Joseph Huber 8a1984c25e [Clang][Docs] Document `-Xoffload-linker` flag
Summary:
I added the `-Xoffload-linker` flag and did not provide additional
documentation. This patch adds it.
2022-05-25 13:33:10 -04:00
Nicolai Hähnle affa1b1cc5 AMDGPU/GISel: Factor out AMDGPURegisterBankInfo::buildReadFirstLane
A later change will add a 3rd user, so factoring out the common code
seems useful.

Reorganizing the executeInWaterfallLoop causes some more COPYs to be
generated, but those all fold away during instruction selection.
Generating the comparisons uses generic instructions over machine
instructions now which admittedly shouldn't make a difference
(though it should make it easier to move the waterfall loop generation
to another place).

(Resubmit with missing test added.)

Differential Revision: https://reviews.llvm.org/D125324
2022-05-25 12:14:01 -05:00
Nicolai Hähnle afc90101a5 Revert "AMDGPU/GISel: Factor out AMDGPURegisterBankInfo::buildReadFirstLane"
This reverts commit 2a28467e53.
2022-05-25 12:03:23 -05:00
Zequan Wu a648724921 Reland "[llvm-pdbutil] Add options to only dump symbol record at specified offset and its parents or children with spcified depth."
This reverts commit cfb4e78252.
2022-05-25 09:57:35 -07:00
Kazu Hirata 4391625255 [lldb] Fix an unused function warning
This patch fixes:

  .../llvm-project/lldb/source/Host/common/PseudoTerminal.cpp:106:20:
  error: unused function 'use_ptsname' [-Werror,-Wunused-function]
2022-05-25 09:49:05 -07:00
Logan Chien 0c8fdd7230 [mlir] Fix Tensor_InsertSliceOp description
This commit fixes `Tensor_InsertSliceOp` `sizes` inputs/attributes
description.

Before this commit, the description says the `sizes` inputs/attributes
denote the size of the return type. But according to the
`InsertSliceOpConstantArgumentFolder` in
`lib/Dialect/Tensor/IR/TensorOps.cpp`, the `sizes` inputs/attributes
actually denote the size of the source type.

I had an off-line discussion with the authors of `TensorOps.td` and
`TensorOps.cpp`. We concluded that it was a typo in the Op description.

This commit updates the Op description to match the actual usage.

Differential Revision: https://reviews.llvm.org/D126264
2022-05-25 09:38:06 -07:00
Nicolai Hähnle 2a28467e53 AMDGPU/GISel: Factor out AMDGPURegisterBankInfo::buildReadFirstLane
A later change will add a 3rd user, so factoring out the common code
seems useful.

Reorganizing the executeInWaterfallLoop causes some more COPYs to be
generated, but those all fold away during instruction selection.
Generating the comparisons uses generic instructions over machine
instructions now which admittedly shouldn't make a difference
(though it should make it easier to move the waterfall loop generation
to another place).

Differential Revision: https://reviews.llvm.org/D125324
2022-05-25 11:35:02 -05:00
Takafumi Arakaki 18e6b8234a Allow pointer types for atomicrmw xchg
This adds support for pointer types for `atomic xchg` and let us write
instructions such as `atomicrmw xchg i64** %0, i64* %1 seq_cst`. This
is similar to the patch for allowing atomicrmw xchg on floating point
types: https://reviews.llvm.org/D52416.

Differential Revision: https://reviews.llvm.org/D124728
2022-05-25 16:20:26 +00:00
Craig Topper 172149e98c [RISCV] Preserve fast math flags in lowerVPOp.
Update test to check MIR after finalize-isel instead of debug output.

This is of course not the only place we should preserve FMF, but
it's the most obvious one.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D126306
2022-05-25 09:16:07 -07:00
Craig Topper 06fee478d2 [X86] Add isSimple check to the load combine in combineExtractVectorElt.
I think we need to be sure the load isn't volatile before we
duplicate and shrink it.

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D126353
2022-05-25 09:11:11 -07:00
Anubhab Ghosh 9da89651a8 [llvm-objcopy][ObjectYAML][mips] Add MIPS specific ELF section indexes
This fixes https://github.com/llvm/llvm-project/issues/53998
and displays correct information in obj2yaml for SHN_MIPS_*
sections according to
https://refspecs.linuxfoundation.org/elf/mipsabi.pdf

Reviewed By: jhenderson, MaskRay

Differential Revision: https://reviews.llvm.org/D123902
2022-05-25 09:01:12 -07:00
Martin Boehme 6f4644d194 [clang] Don't parse MS attributes in `ParseExportDeclaration()`.
As @rsmith commented on https://reviews.llvm.org/D111548: "That looks like it's
simply a bug as far as I can tell, and that call can be removed. MS attributes
will be parsed as part of the decl specifier sequence as needed and don't need
to be parsed as declaration attributes."

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D126062
2022-05-25 17:15:41 +02:00
Philip Reames 2a3b6f2cba [RISCV] Hoist VSETVLI vlmax, vtype out of scalable loops
This is a straight forward extension of the PRE transform introduced in D124869 to handle the VLMAX case.

The test changes here look quite positive. This surprised me until I realized that all the tests are using @llvm.vscale to figure out the VLMAX, not the llvm.riscv.vsetvlmax intrinsic. If they'd used the later, these would have been full redundancy cases and fully handled by the data flow. I'm not really sure if use of vscale here is representative or not. If it is, we should probably look at using VSETVLI to lower vscale rather than a raw read of vlenb and some math.

Differential Revision: https://reviews.llvm.org/D126338
2022-05-25 08:00:27 -07:00
Philip Reames dd336b6891 [RISCV] Restructure comment and add clarifying assert to getFrameIndexReference [NFC]
Differential Revision: https://reviews.llvm.org/D126088
2022-05-25 07:59:27 -07:00
Lei Zhang e0ea1fc6f8 [mlir][spirv] Fix capability check for 64-bit element types
Using 64-bit integer/float type in interface storage classes would
require Int64/Float64 capability, per the Vulkan spec:

```
shaderInt64 specifies whether 64-bit integers (signed and unsigned) are
supported in shader code. If this feature is not enabled, 64-bit integer
types must not be used in shader code. This also specifies whether
shader modules can declare the Int64 capability. Declaring and using
64-bit integers is enabled for all storage classes that SPIR-V allows
with the Int64 capability.
```

This is different from, say, 16-bit element types, where:

```
shaderInt16 specifies whether 16-bit integers (signed and unsigned) are
supported in shader code. If this feature is not enabled, 16-bit integer
types must not be used in shader code. This also specifies whether
shader modules can declare the Int16 capability. However, this only
enables a subset of the storage classes that SPIR-V allows for the Int16
SPIR-V capability: Declaring and using 16-bit integers in the Private,
Workgroup (for non-Block variables), and Function storage classes is
enabled, while declaring them in the interface storage classes (e.g.,
UniformConstant, Uniform, StorageBuffer, Input, Output, and
PushConstant) is not enabled.
```

Reviewed By: hanchung

Differential Revision: https://reviews.llvm.org/D126256
2022-05-25 10:57:31 -04:00
Lei Zhang 413fbb045d [mlir][scf] Retain existing attributes in scf.for transforms
These attributes can carry useful information, e.g., pipelines
might use them to organize and chain patterns.

Reviewed By: hanchung

Differential Revision: https://reviews.llvm.org/D126320
2022-05-25 10:53:02 -04:00
Joe Loser 5a2dbe49be
[libc++][test] Verify std::ranges::rbegin, crbegin, rend, crend are CPOs
Uncomment the tests to ensure `std::ranges::rbegin` and friends are indeed
customization points objects.

Differential Revision: https://reviews.llvm.org/D126325
2022-05-25 08:48:22 -06:00
Philip Reames a4a438f05a [riscv] Add coverage for fixed length vector loops using LMUL 2022-05-25 07:42:21 -07:00
Ivan Kosarev 046f901735 [TableGen] Undeprecate 'field' when used with the CodeEmitterGen backend.
Differential Revision: https://reviews.llvm.org/D126290
2022-05-25 15:15:19 +01:00
Michał Górny e40c4dd662 [llvm-rc] Avoid which(1) dependency in windres-prefix.test
Rely on lit substitution to provide the path to llvm-windres instead
of redundantly calling which(1) with the subtituted absolute path.
This fixes test failure on the happy systems without which(1) installed.

Differential Revision: https://reviews.llvm.org/D126366
2022-05-25 16:14:47 +02:00
Groverkss fb857ded70 [MLIR][Presburger] Add inverse to IntegerRelation
This patch adds support for obtaining inverse of a relation.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D126327
2022-05-25 19:37:52 +05:30
Nikita Popov 6346a026af [PhaseOrdering] Add test for unprofitable loop load PRE backedge splitting (NFC) 2022-05-25 16:06:41 +02:00
Groverkss 3c057ac2c2 [MLIR][Presburger] Add getDomainSet, getRangeSet to IntegerRelation
This patch adds support for obtaining a set corresponding to the domain/range
of the relation.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D126326
2022-05-25 19:35:56 +05:30
Louis Dionne 8383351d45 [libc++] Remove conditional include 2022-05-25 10:04:54 -04:00
Simon Moll 6e12711081 [VP][fix] Don't discard masks in reductions
When expanding VP reductions to non VP-code, the reduction pass was
ignoring the mask before. Fix this by keeping the mask and selecting
neutral elements where the mask is zero.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D126362
2022-05-25 15:54:45 +02:00
Paul Robinson d8dda57ae7 [PS5] Default to -fno-rtti 2022-05-25 06:48:21 -07:00
Louis Dionne d8afac7a2b [libc++] Use Python subprocess instead of libc++'s own utilities
Once we move off entirely from the legacy testing framework, this will
allow removing a bunch of code.

Differential Revision: https://reviews.llvm.org/D126303
2022-05-25 09:33:22 -04:00
Haojian Wu a17fc7fd86 Fix unused-variable warning, NFC. 2022-05-25 15:25:03 +02:00
Haojian Wu c673d67bc7 [AST] Dont invalidate a ref-type var decl if it has no initializer.
This would allow more AST nodes being preserved for broken code, and
have a more consistent valid bit for ref-type var decl (currently, a
ref-type var decl with a broken initializer is valid).

Per https://reviews.llvm.org/D76831#1973053, the initializer of a variable
should play no part in its "invalid" bit.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D122935
2022-05-25 15:14:35 +02:00
Nico Weber 788463e72a [pseudo-gen] Add -o flag, make --grammar required
Virtually all LLVM tools accept a `-o` flag, so add one. This will make it
possible to possibly add a --write-if-changed flag later. It also makes it
so that the file isn't partially written if the tool oesn't run successfully.

Marking --grammar as `Required` allows removing some manual
verification code for it.

Differential Revision: https://reviews.llvm.org/D126373
2022-05-25 09:11:42 -04:00
Ivan Kosarev b3c856d10c [MLIR][NFC] Fix the Conversion/MemRefToSPIRV/alloc.mlir test.
Caught with D125604.

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D126292
2022-05-25 13:58:19 +01:00
zhongyunde 58b76492c1 [tests] precommit tests for D126040
Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D126356
2022-05-25 20:39:04 +08:00
Vy Nguyen fae6bd7563 [lld-macho] Support -non_global_symbols_strip_list, -non_global_symbols_no_strip_list, -x
PR/55600

Differential Revision: https://reviews.llvm.org/D126046
2022-05-25 19:22:04 +07:00
Sanjay Patel d5ebba2aa6 [x86] add test with volatile load; NFC
Test for D126353
2022-05-25 08:19:29 -04:00
Aaron Ballman f96aa834d7 Test C DR conformance (part three of many)
This adds more of the tests for the first 100 DRs in C and updates
their status on the status page.
2022-05-25 08:18:16 -04:00
Nathan James 09ef6da8dc
[clang-tidy] Update docs for SimplifyDeMorganRelaxed
Forgot to add this to f3c1d28176
2022-05-25 13:12:20 +01:00
Nathan James f3c1d28176
[clang-tidy] Extend SimplifyBooleanExpr demorgan support.
Adds an option SimplifyDemorganRelaxed which, when enabled, will transform negated conjunctions or disjunctions when neither operand is a negation.
Default value is `false`.

Reviewed By: LegalizeAdulthood

Differential Revision: https://reviews.llvm.org/D126162
2022-05-25 13:09:00 +01:00
lorenzo chelini 1ad9b26622 [MLIR][Linalg] Adjust documentation (NFC)
Adjust docs for tensor.pad, tensor.collapse_shape and tensor.expand_shape.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D126370
2022-05-25 13:57:11 +02:00
Shraiysh Vaishay 512d06b045 [mlir][openmp] Add check for types of operands in omp.atomic.write
This patch makes sure that the address dereferences to value in
omp.atomic.write operation.

Reviewed By: kiranchandramohan, peixin

Differential Revision: https://reviews.llvm.org/D126272
2022-05-25 17:22:16 +05:30
Nico Weber c85688a22b [gn build] (manually) port some of cd2292ef82 2022-05-25 07:19:41 -04:00
David Green 18cb3b3506 [ARM] Fix vcvtb/t.f16 input liveness
The `vcvtb.f16.f32 Sd, Sn` (and vcvtt.f16.f32) instruction convert a f32
into a f16, writing either the top or bottom halves of the register.
That means that half of the input register Sd is used in the output.
This wasn't being modelled in the instructions, leading later analyses
to believe that the registers were dead where they were not, generating
invalid scheduling

Fix that be specifying the input Sda register for the instructions too,
allowing them to be set for cases like vector inserts. Most of the
changes are plumbing through the constraint string, cstr.

Differential Revision: https://reviews.llvm.org/D126118
2022-05-25 12:16:26 +01:00
Anastasia Stulova 730dc4e9bc [Clang] Added options for integrated backend.
Following the new flow for external object code emission,
provide flags to switch between integrated and external
backend similar to the integrated assembler options.

SPIR-V target is the only user of this functionality at
this point.

This patch also updated SPIR-V documentation to clarify
that integrated object code emission for SPIR-V is an
experimental feature.

Differential Revision: https://reviews.llvm.org/D125679
2022-05-25 12:07:33 +01:00