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4 Commits

Author SHA1 Message Date
Craig Topper 95bdabd338 [AVX512] Add patterns to implement stores of extracts of least signficant subvectors using XMM or YMM stores instead of the vector extract instructions. 
Similar is already done for AVX and we had lost it going to AVX512VL.

llvm-svn: 270383
 2016-05-22 23:44:33 +00:00
Craig Topper db960eddfa [AVX512] Add patterns for extracting subvectors and storing to memory. 
llvm-svn: 270334
 2016-05-21 22:50:14 +00:00
James Y Knight 7c905063c5 Make utils/update_llc_test_checks.py note that the assertions are 
autogenerated.

Also update existing test cases which appear to be generated by it and
weren't modified (other than addition of the header) by rerunning it.

llvm-svn: 253917
 2015-11-23 21:33:58 +00:00
Igor Breger defab3c1ef AVX512: vpextrb/w/d/q and vpinsrb/w/d/q implementation. 
This instructions doesn't have intrincis.
Added tests for lowering and encoding.

Differential Revision: http://reviews.llvm.org/D12317

llvm-svn: 249688
 2015-10-08 12:55:01 +00:00