Amara Emerson
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614b44bbe9
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This patch adds support for 16 bit floating point registers to the inline asm register selection on AArch64.
Without this patch, register allocation for the example below fails.
define half @test(half %a1, half %a2) #0 {
entry:
%0 = tail call half asm "sqrshl ${0:h}, ${1:h}, ${2:h}", "=w,w,w" (half %a1, half %a2) #1
ret half %0
}
Patch by Florian Hahn.
Differential Revision: https://reviews.llvm.org/D25080
llvm-svn: 286111
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2016-11-07 15:42:12 +00:00 |