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19391 Commits

Author SHA1 Message Date
Lang Hames f22f46bf25 Fixed natural stack alignment for Linux x86-32. Thanks Eli. 
llvm-svn: 141616
 2011-10-11 00:51:36 +00:00
Akira Hatanaka fa55bc27cb Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too. 
llvm-svn: 141615
 2011-10-11 00:44:20 +00:00
Akira Hatanaka e6ced5b3d5 Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot. 
llvm-svn: 141613
 2011-10-11 00:37:28 +00:00
Akira Hatanaka be68f3c348 Add definitions of 64-bit loads and stores. Add a patterns for unaligned 
zextloadi32 for which there is no corresponding pseudo or real instruction. 

llvm-svn: 141608
 2011-10-11 00:27:28 +00:00
Akira Hatanaka fd2d7dcc31 Change definitions of classes LoadM and StoreM in preparation for adding support 
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.

llvm-svn: 141603
 2011-10-11 00:11:12 +00:00
Bill Wendling 98703350d0 Simplify check that optional def is there and is CPSR. 
llvm-svn: 141602
 2011-10-11 00:10:41 +00:00
Lang Hames de7ab801cc Add a natural stack alignment field to TargetData, and prevent InstCombine from 
promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.

The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.

llvm-svn: 141599
 2011-10-10 23:42:08 +00:00
Jim Grosbach c11b7c3805 Simplify operand Kind checks a bit. 
llvm-svn: 141592
 2011-10-10 23:06:42 +00:00
Bill Wendling a7d697e4a6 Reapply r141365 now that PR11107 is fixed. 
llvm-svn: 141591
 2011-10-10 22:59:55 +00:00
Jim Grosbach 2957c88c0a Add a name to sub-operand for clarity. 
llvm-svn: 141590
 2011-10-10 22:55:05 +00:00
Bill Wendling 0a10cdc704 If the CPSR is defined by a copy, then we don't want to merge it into an IT 
block. E.g., if we have:

  movs  r1, r1
  rsb   r1, 0
  movs  r2, r2
  rsb   r2, 0

we don't want this to be converted to:

  movs  r1, r1
  movs  r2, r2
  itt   mi
  rsb   r1, 0
  rsb   r2, 0

PR11107 & <rdar://problem/10259534>

llvm-svn: 141589
 2011-10-10 22:52:53 +00:00
Eli Friedman 8ec0897db6 Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102. 
llvm-svn: 141585
 2011-10-10 22:28:47 +00:00
Benjamin Kramer 874c519337 X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge. 
llvm-svn: 141571
 2011-10-10 19:35:07 +00:00
Nadav Rotem 814598563f Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the 
instruction set has no 64-bit SRA support.

llvm-svn: 141570
 2011-10-10 19:31:45 +00:00
Benjamin Kramer 42c0330a79 X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) 
llvm-svn: 141563
 2011-10-10 18:34:56 +00:00
Bill Wendling 47aac51043 Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to 
hang, and possibly SPEC/CINT2006/464_h264ref.

llvm-svn: 141560
 2011-10-10 18:27:30 +00:00
Bill Wendling ea662bb32f When getting the number of bits necessary for addressing mode 
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.

llvm-svn: 141529
 2011-10-10 07:24:23 +00:00
Craig Topper a14c5723eb Put a bunch of calls to ToggleFeature behind proper if statements. 
llvm-svn: 141527
 2011-10-10 05:34:02 +00:00
Chad Rosier b60187ae74 Fix a regression from r138445. If we're loading from the frame/base pointer 
the tADDrSPi instruction can't be used.  Make sure we're updating the opcode
to tADDi3 in all cases.
rdar://10254707

llvm-svn: 141523
 2011-10-10 01:03:35 +00:00
Justin Holewinski dd40b0d792 PTX: Print .ptr kernel attributes if PTX version >= 2.2 
llvm-svn: 141508
 2011-10-09 15:42:02 +00:00
Craig Topper fe9179fa4f Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. 
llvm-svn: 141505
 2011-10-09 07:31:39 +00:00
Jakob Stoklund Olesen 513d1213cc Prevent potential NOREX bug. 
A GR8_NOREX virtual register is created when extrating a sub_8bit_hi
sub-register:

  %vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1
  TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2

If such a live range is ever split, its register class must not be
inflated to GR8.  The sub-register copy can only target GR8_NOREX.

I dont have a test case for this theoretical bug.

llvm-svn: 141500
 2011-10-08 20:20:03 +00:00
Jakob Stoklund Olesen 729abd360e Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies. 
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.

TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.

This fixes PR11088.

llvm-svn: 141499
 2011-10-08 18:28:28 +00:00
Nicolas Geoffray a0263e7aca Always check if a method or a type exist before trying to create it. 
llvm-svn: 141490
 2011-10-08 11:56:36 +00:00
Anton Korobeynikov e45373520d Disable ABS optimization for Thumb1 target, we don't have necessary instructions there. 
llvm-svn: 141481
 2011-10-08 08:38:45 +00:00
Akira Hatanaka 6be7d6c976 Simplify definition of FP move instructions. 
llvm-svn: 141476
 2011-10-08 03:50:18 +00:00
Akira Hatanaka 2365f90676 Define classes and multiclasses for FP binary instructions. 
llvm-svn: 141475
 2011-10-08 03:38:41 +00:00
Akira Hatanaka c7548dec7d Define multiclasses for FP-to-FP instructions. 
llvm-svn: 141474
 2011-10-08 03:29:22 +00:00
Akira Hatanaka 13ae13bdc2 Define classes for FP unary instructions and multiclasses for FP-to-fixed point 
conversion instructions. 

llvm-svn: 141473
 2011-10-08 03:19:38 +00:00
Akira Hatanaka 557c8e3443 Add patterns for unaligned load and store instructions and enable the 
instruction selector to generate them.

llvm-svn: 141471
 2011-10-08 02:24:10 +00:00
Jim Grosbach d0637bfc68 ARM NEON assembly parsing and encoding for VDUP(scalar). 
llvm-svn: 141446
 2011-10-07 23:56:00 +00:00
Jim Grosbach 6e5778f7b1 ARM prefix asmparser operand kind enums for readability. 
llvm-svn: 141438
 2011-10-07 23:24:09 +00:00
Bill Wendling 883ec97115 Take all of the invoke basic blocks and make the dispatch basic block their new 
successor. Remove the old landing pad from their successor list, because it's
now the successor of the dispatch block. Now that the landing pad blocks are no
longer the destination of invokes, we can mark them as normal basic blocks
instead of landing pads.

This more closely resembles what the CFG is actually doing.

llvm-svn: 141436
 2011-10-07 23:18:02 +00:00
Bill Wendling f9f5e455d4 Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emit 
it with the new SjLj emitter stuff. This way there's no need to emit that
kind-of-hacky intrinsic.

llvm-svn: 141419
 2011-10-07 22:08:37 +00:00
Bill Wendling 7ecfbd90ef Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented to 
do. This will be useful later on with the new SJLJ stuff.

llvm-svn: 141416
 2011-10-07 21:25:38 +00:00
Jakob Stoklund Olesen 464fcc0035 Constrain both operands on MOVZX32_NOREXrr8. 
This instruction is explicitly encoded without an REX prefix, so both
operands but be *_NOREX.

Also add an assertion to copyPhysReg() that fires when the MOV8rr_NOREX
constraints are not satisfied.

This fixes a miscompilation in 20040709-2 in the gcc test suite.

llvm-svn: 141410
 2011-10-07 20:15:54 +00:00
Jim Grosbach b8d9f51e4c Improve ARM assembly parser diagnostic for unexpected tokens. 
Consider:
  mov r8, r11 fred

Previously, we issued the not very informative:
x.s:6:1: error: unexpected token in argument list

^

Now we generate:
x.s:5:14: error: unexpected token in argument list
  mov r8, r11 fred
              ^

llvm-svn: 141380
 2011-10-07 18:27:04 +00:00
Evan Cheng 74db300f37 High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336 
llvm-svn: 141371
 2011-10-07 17:21:44 +00:00
Bob Wilson 8decdc472f Reenable tail calls for iOS 5.0 and later. 
llvm-svn: 141370
 2011-10-07 17:17:49 +00:00
Bob Wilson bc1589945d Reenable use of divmod compiler_rt functions for iOS 5.0 and later. 
llvm-svn: 141368
 2011-10-07 16:59:21 +00:00
Anton Korobeynikov 318d6bae80 Peephole optimization for ABS on ARM. 
Patch by Ana Pazos!

llvm-svn: 141365
 2011-10-07 16:15:08 +00:00
Craig Topper d9cfddc5cd Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. 
llvm-svn: 141358
 2011-10-07 07:02:24 +00:00
Craig Topper bf136764ae Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT. 
llvm-svn: 141354
 2011-10-07 05:53:50 +00:00
Craig Topper 5aebebe18d Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. 
llvm-svn: 141353
 2011-10-07 05:35:38 +00:00
Bill Wendling 8d50ea0f82 Use the correct vreg here. 
llvm-svn: 141342
 2011-10-06 23:41:14 +00:00
Bill Wendling b3d4678877 Generate the dispatch code for a 'thumb' function. This is very similar to the 
others. They take the call site value. Determine if it's a proper value. And
then jumps to the correct call site via a jump table.

llvm-svn: 141341
 2011-10-06 23:37:36 +00:00
Owen Anderson 6a5c150e9c Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue. 
llvm-svn: 141339
 2011-10-06 23:33:11 +00:00
Eli Friedman 1456cd20b4 Remove the old atomic instrinsics. autoupgrade functionality is included with this patch. 
llvm-svn: 141333
 2011-10-06 23:20:49 +00:00
Bill Wendling 5626c66a89 Generate the dispatch table for ARM mode. 
llvm-svn: 141327
 2011-10-06 22:53:00 +00:00
Bill Wendling 030b58e5c9 Refactor some of the code that sets up the entry block for SjLj EH. No functionality change. 
llvm-svn: 141323
 2011-10-06 22:18:16 +00:00