e600aba989
ARM conditional mov encoding fix.
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llvm-svn: 119354
2010-11-16 18:13:42 +00:00
3bd60eff26
- Remove dead patterns.
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- Add encodings to the *LDMIA_RET instrs. Probably not needed...
llvm-svn: 119323
2010-11-16 02:08:45 +00:00
a68e3a5397
Encode the multi-load/store instructions with their respective modes ('ia',
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'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
llvm-svn: 119310
2010-11-16 01:16:36 +00:00
38b469effd
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.
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llvm-svn: 119180
2010-11-15 20:47:07 +00:00
40a7f57d0d
Nuke redundant encoding bit set.
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llvm-svn: 119164
2010-11-15 18:17:24 +00:00
63274cbc5d
add fields to the .td files unconditionally, simplifying tblgen a bit.
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Switch the ARM backend to use 'let' instead of 'set' with this change.
llvm-svn: 119120
2010-11-15 05:19:05 +00:00
9430eb489c
Comment out the defms until they're activated.
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llvm-svn: 119000
2010-11-13 11:20:05 +00:00
705ec77ab5
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
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llvm-svn: 118999
2010-11-13 10:57:02 +00:00
c4c642832d
Convert the modes to lower case.
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llvm-svn: 118998
2010-11-13 10:43:34 +00:00
f2fa04acfc
Minor cleanups:
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- Get the opcode once.
- Add a ParserMatchClass to reglist.
llvm-svn: 118997
2010-11-13 10:40:19 +00:00
e69afc6bb7
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
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future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
llvm-svn: 118995
2010-11-13 09:09:38 +00:00
79ff5238e9
Conditional moves are slightly more expensive than moves.
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llvm-svn: 118985
2010-11-13 05:14:20 +00:00
2bcb8daa44
Add conditional move of large immediate.
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llvm-svn: 118968
2010-11-13 02:25:14 +00:00
1aa5863a3e
Swap multiclass operand order for consistency with other patterns.
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llvm-svn: 118965
2010-11-13 01:28:30 +00:00
69fd90e661
Continue ARM indexed load refactoring. Multiclass for LDR{B} pre/post indexed
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instructions.
llvm-svn: 118963
2010-11-13 01:07:20 +00:00
2f790749e8
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode
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flag for the LDRT/STRT family instructions as a side effect.
llvm-svn: 118955
2010-11-13 00:35:48 +00:00
9c40af415f
For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled with movi + orr.
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llvm-svn: 118945
2010-11-12 23:46:13 +00:00
f478cf9685
Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.
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llvm-svn: 118938
2010-11-12 23:03:38 +00:00
0fc8084a64
Add conditional mvn instructions.
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llvm-svn: 118935
2010-11-12 22:42:47 +00:00
e09122b46b
Zap a copy/paste-o bit of dead code.
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llvm-svn: 118926
2010-11-12 21:29:10 +00:00
31a7234a47
Refactor to parameterize some ARM load/store encoding patterns. Preparatory
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to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.
llvm-svn: 118925
2010-11-12 21:28:15 +00:00
3fd741191d
Fill in the default predication bits for ARM unconditional branch.
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llvm-svn: 118907
2010-11-12 18:13:26 +00:00
c33f28bf90
ARM fixup encoding for direct call instructions (BL).
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llvm-svn: 118829
2010-11-11 20:05:40 +00:00
9d6d77a9f4
Encoding of destination fixup for ARM branch and conditional branch
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instructions.
llvm-svn: 118801
2010-11-11 18:04:49 +00:00
68685e644f
Encoding for ARM LDRSH_POST.
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llvm-svn: 118794
2010-11-11 16:55:29 +00:00
f18b951e18
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
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llvm-svn: 118767
2010-11-11 01:55:59 +00:00
e967c0a795
Fix encoding of Ra register for ARM smla* instructions.
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llvm-svn: 118761
2010-11-11 01:27:41 +00:00
607efcbc3e
ARM STRH encoding information.
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llvm-svn: 118757
2010-11-11 01:09:40 +00:00
c4dd2349c7
Move LDM predicate operand encoding into base clase. Add STM missing STM
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encoding bits.
llvm-svn: 118738
2010-11-10 23:44:32 +00:00
cc4a491557
ARM LDM encoding for the mode (ia, ib, da, db) operand.
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llvm-svn: 118736
2010-11-10 23:38:36 +00:00
58ef598cd1
Fix ARM encoding of non-return LDM instructions.
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llvm-svn: 118732
2010-11-10 23:18:49 +00:00
e39a9fcc0e
Fix ARM encoding of LDM+Return instruction.
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llvm-svn: 118730
2010-11-10 23:12:48 +00:00
7e51095c23
Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.
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llvm-svn: 118600
2010-11-09 18:43:54 +00:00
dbfb5edbdb
Add encoder method for ARM load/store shifted register offset operands.
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llvm-svn: 118513
2010-11-09 17:20:53 +00:00
1b83ed5f7c
Revert r118457 and r118458. These won't hold for GPRs.
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llvm-svn: 118462
2010-11-09 00:30:18 +00:00
aeead4d1e1
reglist has two operands.
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llvm-svn: 118457
2010-11-08 23:50:20 +00:00
424601a9b3
Make RegList an ASM operand so that TableGen will generate code for it. This is
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an initial implementation and may change once reglists are fully fleshed out.
llvm-svn: 118390
2010-11-08 00:39:58 +00:00
21acf9fb38
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
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llvm-svn: 118237
2010-11-04 05:19:35 +00:00
8740ee3637
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
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llvm-svn: 118160
2010-11-03 06:34:55 +00:00
6f36042557
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
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llvm-svn: 118152
2010-11-03 05:14:24 +00:00
e84eb99cbb
The MC code couldn't handle ARM LDR instructions with negative offsets:
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vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
llvm-svn: 118144
2010-11-03 01:49:29 +00:00
c6af2b4066
Break ARM addrmode4 (load/store multiple base address) into its constituent
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parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
2010-11-03 01:01:43 +00:00
cc5dce89d4
Completely reject instructions that have an operand in their
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ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
llvm-svn: 118119
2010-11-02 23:40:41 +00:00
603bd8f54c
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
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with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
llvm-svn: 118094
2010-11-02 22:31:46 +00:00
a4b63e19d2
Rename encoder methods to match naming convention.
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llvm-svn: 118093
2010-11-02 22:28:01 +00:00
93a4d44ee6
Sort bit assignments. Cosmetic change only.
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llvm-svn: 118029
2010-11-02 17:59:04 +00:00
526ffd57d2
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
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llvm-svn: 117997
2010-11-02 01:24:55 +00:00
ad40234eff
Add correct NEON encodings for the "multiple single elements" form of vld.
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llvm-svn: 117984
2010-11-02 00:05:05 +00:00
dd9fbaa9c0
Add support for alignment operands on VLD1-lane instructions.
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This is another part of the fix for Radar 8599955.
llvm-svn: 117976
2010-11-01 23:40:51 +00:00
0190a649e8
Mark ARM subtarget features that are available for the assembler.
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llvm-svn: 117929
2010-11-01 16:59:54 +00:00
Jim Grosbach