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13533 Commits

Author SHA1 Message Date
Devang Patel 4dc76f2438 During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. 
[take 2]

llvm-svn: 135423
 2011-07-18 20:55:23 +00:00
Andrew Trick 7da2417c8a indvars: LinearFunctionTestReplace for non-canonical IVs. 
For -disable-iv-rewrite, perform LFTR without generating a new
"canonical" induction variable. Instead find the "best" existing
induction variable for use in the loop exit test and compute the final
value of that IV for use in the new loop exit test. In short,
convert to a simple eq/ne exit test as long as it's cheap to do so.

llvm-svn: 135420
 2011-07-18 20:32:31 +00:00
Akira Hatanaka 338879a7f4 Do not treat atomic.load.sub differently than other atomic binary intrinsics. 
llvm-svn: 135418
 2011-07-18 19:58:59 +00:00
Akira Hatanaka 27292638bd Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from 
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.

llvm-svn: 135415
 2011-07-18 18:52:12 +00:00
Jakob Stoklund Olesen c45d38e14a Fix a crash when building 177.mesa for armv6. 
When splitting a live range immediately before an LDR_POST instruction
that redefines the address register, make sure to use the correct value
number in leaveIntvBefore.

We need the value number entering the instruction.

<rdar://problem/9793765>

llvm-svn: 135413
 2011-07-18 18:47:13 +00:00
Bruno Cardoso Lopes 4208cace5f Add AVX 128-bit sqrt versions 
llvm-svn: 135404
 2011-07-18 17:51:40 +00:00
Nick Lewycky d8921f939c Delete empty unused file. 
llvm-svn: 135379
 2011-07-18 05:54:06 +00:00
Eric Christopher c56b9c75d5 More minor adjustments. 
llvm-svn: 135342
 2011-07-16 07:28:35 +00:00
Eli Friedman 0318036c4d Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873. 
llvm-svn: 135337
 2011-07-16 02:41:28 +00:00
Bruno Cardoso Lopes 4480040191 Add AVX 128-bit patterns for sint_to_fp 
llvm-svn: 135332
 2011-07-16 00:50:20 +00:00
Eric Christopher f5a8cc7ef8 Finish propagating %asmtmp->%1 change. 
llvm-svn: 135330
 2011-07-16 00:26:07 +00:00
Chris Lattner 8b4cf5e8a2 fix rdar://9776316 - type remapping needed for inline asm blobs, 
fixing some objc llvm-test crashes with LTO.

llvm-svn: 135324
 2011-07-15 23:18:40 +00:00
Bruno Cardoso Lopes 8df9cfc279 Fix a couple of things: 
1) Make non-legal 256-bit loads to be promoted to v4i64. This lets us
canonize the loads and handle things the same way we use to handle
for 128-bit registers. Despite of what one of the removed comments
explained, the load promotion would not mess with VPERM, it's only a
matter of doing the appropriate bitcasts when this instructions comes
to be introduced. Also make LOAD v8i32 legal.

2) Doing 1) exposed two bugs:
- v4i64 was being promoted to itself for several opcodes (introduced
in r124447 by David Greene) causing endless recursion and the stack to
explode.
- there was no support for allOnes BUILD_VECTORs and ANDNP would fail to
match because it was generating early target constant pools during
lowering.

3) The testcases are already checked-in, doing 1) exposed the
bugs in the current testcases.

4) Tidy up code to be more clear and explicit about AVX.

llvm-svn: 135313
 2011-07-15 22:24:33 +00:00
Eli Friedman 3846acc98e PR10370: Make sure we know how to relax push correctly on x86-64. 
llvm-svn: 135303
 2011-07-15 21:28:39 +00:00
Chad Rosier c1e40f8d26 A real testcase for r135286. 
llvm-svn: 135299
 2011-07-15 20:58:38 +00:00
Eric Christopher 32500bc68b Update these tests, no longer outputting names for the variables. 
llvm-svn: 135298
 2011-07-15 20:58:16 +00:00
Chad Rosier b45111556d Add testcase for r135286. 
llvm-svn: 135291
 2011-07-15 19:06:58 +00:00
Owen Anderson 454e1c7abb Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler. 
llvm-svn: 135290
 2011-07-15 18:46:47 +00:00
Jim Grosbach 03a8a16f32 ARM diagnostic when 's' suffix on mnemonic that can't set flags. 
For example, "mlss r0, r1, r2, r3".

The MLS instruction does not have a flag-setting variant.

llvm-svn: 135203
 2011-07-14 22:04:21 +00:00
Jim Grosbach 51849920f1 Add some testcases for ARM MLA/MLS instructions. 
llvm-svn: 135196
 2011-07-14 21:43:05 +00:00
Jim Grosbach 26e7449443 ARM MCRR/MCRR2 immediate operand range checking. 
llvm-svn: 135192
 2011-07-14 21:26:42 +00:00
Jim Grosbach d37d2025e9 ARM MCR/MCR2 assembly parsing operand constraints. 
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.

llvm-svn: 135189
 2011-07-14 21:19:17 +00:00
Jim Grosbach e336a290a6 Enable some tests we now handle correctly. 
llvm-svn: 135185
 2011-07-14 21:02:23 +00:00
Eric Christopher 92464be28c Check register class matching instead of width of type matching 
when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.

Fixes PR10352 and rdar://9777108

llvm-svn: 135180
 2011-07-14 20:13:52 +00:00
Bruno Cardoso Lopes 6778597deb Add 256-bit load/store recognition and matching in several places. 
llvm-svn: 135171
 2011-07-14 18:50:58 +00:00
Jim Grosbach 2f9aeeef3b Update ARM Assembly of LDM/STM. 
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.

llvm-svn: 135168
 2011-07-14 18:35:38 +00:00
Jim Grosbach d616cf3497 ARM ISB assembly parsing tests. 
llvm-svn: 135158
 2011-07-14 18:02:25 +00:00
Jim Grosbach b218202586 ARM ISB instruction assembly parsing. 
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.

llvm-svn: 135156
 2011-07-14 18:00:31 +00:00
Eric Christopher 0c666b4664 Add a testcase for r135123. 
Part of rdar://9761830

llvm-svn: 135133
 2011-07-14 06:23:09 +00:00
Benjamin Kramer 15cd5a3f12 Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient. 
llvm-svn: 135126
 2011-07-14 01:38:42 +00:00
Jim Grosbach e6f8b1fac6 ARM tests for EOR instruction parsing and encoding. 
llvm-svn: 135119
 2011-07-14 00:22:21 +00:00
Jim Grosbach f34e35da1c Remove duplicate tests. 
llvm-svn: 135117
 2011-07-14 00:19:19 +00:00
Jim Grosbach a0958d7abf ARM Assembler support for DSB instruction. 
Add instalias for default 'sy' option. Add tests.

llvm-svn: 135116
 2011-07-14 00:18:13 +00:00
Jim Grosbach 44c3f08e85 ARM Assembler support for DMB instruction. 
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".

llvm-svn: 135109
 2011-07-13 23:40:38 +00:00
Jim Grosbach 507ba77465 ARM Assembler support for DBG instruction. 
Add range checking and testing for parsing and encoding of DBG instruction.

llvm-svn: 135102
 2011-07-13 22:59:38 +00:00
Bruno Cardoso Lopes 3c4d652210 We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases. 
llvm-svn: 135099
 2011-07-13 22:28:55 +00:00
Jim Grosbach 307de01867 ARM parsing and encoding tests for CMN/CMP. 
llvm-svn: 135098
 2011-07-13 22:26:58 +00:00
Jim Grosbach 9559d360e5 Shuffle ARM assembly tests a bit. 
llvm-svn: 135095
 2011-07-13 22:19:10 +00:00
Jim Grosbach 31756c2283 Range checking for CDP[2] immediates. 
llvm-svn: 135092
 2011-07-13 22:01:08 +00:00
Bruno Cardoso Lopes 9613b64916 Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more 
general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.

llvm-svn: 135088
 2011-07-13 21:36:51 +00:00
Eli Friedman 344ec79715 Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile. 
<rdar://problem/9763308>

llvm-svn: 135084
 2011-07-13 21:29:53 +00:00
Jim Grosbach adb29b6dbb Fix predicates for Thumb co-processor instructions. 
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

llvm-svn: 135081
 2011-07-13 21:14:23 +00:00
Jim Grosbach ec8989115d Testcases for ARM assembly BX/BXJ instructions. 
llvm-svn: 135078
 2011-07-13 20:25:46 +00:00
Jim Grosbach 2371a3f14a Testcases for ARM assembly BLX/BL instructions. 
llvm-svn: 135072
 2011-07-13 20:11:04 +00:00
Jim Grosbach 975b641ee8 Range checking for 16-bit immediates in ARM assembly. 
llvm-svn: 135071
 2011-07-13 20:10:10 +00:00
Evan Cheng 4a40a747ba Change test case, one that actually failed before my commit. 
llvm-svn: 135064
 2011-07-13 19:19:44 +00:00
Jim Grosbach c845e55374 Add tests for ARM parsing of 'BKPT' instruction. 
llvm-svn: 135063
 2011-07-13 19:17:36 +00:00
Jim Grosbach 43b45e2790 Fix copy-pasto. 
llvm-svn: 135062
 2011-07-13 19:16:30 +00:00
Jim Grosbach 4f0f2ac757 Add tests for ARM parsing of 'BIC' instruction. 
llvm-svn: 135061
 2011-07-13 19:12:32 +00:00
Jim Grosbach 6cfb1573bf Add some FIXMEs. 
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.

llvm-svn: 135060
 2011-07-13 19:10:23 +00:00