97a2a5c4dc
Associate a MemOperand with LDWCP nodes introduced during ISel.
...
This information is required if we want LDWCP to be hoisted out of loops.
llvm-svn: 139495
2011-09-12 14:43:23 +00:00
a098436b32
Split the init.trampoline intrinsic, which currently combines GCC's
...
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.
llvm-svn: 139140
2011-09-06 13:37:06 +00:00
6e3c83eb1c
Add Uses=[SP] to call instructions. This fixes a miscompilation with a
...
variable sized alloca.
llvm-svn: 138433
2011-08-24 13:32:43 +00:00
56f3b70225
Add intrinsics for SETEV, GETED, GETET.
...
llvm-svn: 137938
2011-08-18 13:00:48 +00:00
0cc000ef29
Fix crash with varargs function with no named parameters.
...
llvm-svn: 136623
2011-08-01 16:45:59 +00:00
f1b800998a
Add intrinsics for the zext / sext instructions.
...
llvm-svn: 135476
2011-07-19 13:28:50 +00:00
252c43ee88
Add intrinsics for the testct, testwct instructions.
...
llvm-svn: 135475
2011-07-19 13:00:40 +00:00
707f0beae1
Add intrinsics for the peek and endin instructions.
...
llvm-svn: 135474
2011-07-19 12:50:25 +00:00
5756c16cdf
make the asmparser reject function and type redefinitions. 'Merging' hasn't been
...
needed since llvm-gcc 3.4 days.
llvm-svn: 133248
2011-06-17 07:06:44 +00:00
2f14b0bb1d
Add XCore intrinsic for crc8.
...
llvm-svn: 132340
2011-05-31 16:24:49 +00:00
542f9a2bcf
Add XCore intrinsic for crc32.
...
llvm-svn: 132336
2011-05-31 14:47:36 +00:00
36d027f7f6
Convert test to FileCheck.
...
llvm-svn: 132335
2011-05-31 14:00:05 +00:00
d3b2f44c9d
Fix register-dependent XCore tests
...
llvm-svn: 130816
2011-05-04 01:01:41 +00:00
f4c9754d5c
Fix Mips, Sparc, and XCore tests that were dependent on register allocation.
...
Add an extra run with -regalloc=basic to keep them honest.
llvm-svn: 128654
2011-03-31 18:42:43 +00:00
9a827b30ab
Add XCore intrinsics for initializing / starting / synchronizing threads.
...
llvm-svn: 128633
2011-03-31 15:13:13 +00:00
6120962d7d
Add XCore intrinsic for setpsc.
...
llvm-svn: 127821
2011-03-17 18:42:05 +00:00
c871eff3f5
Add XCore intrinsics for setclk, setrdy.
...
llvm-svn: 127761
2011-03-16 21:56:00 +00:00
d4346f2388
Add checkevent intrinsic to check if any resources owned by the current thread
...
can event.
llvm-svn: 127741
2011-03-16 18:34:00 +00:00
5f1a26ea39
On the XCore the scavenging slot should be closest to the SP.
...
llvm-svn: 127680
2011-03-15 15:10:11 +00:00
3a68eb150b
Add XCore intrinsics for getps, setps, setsr and clrsr.
...
llvm-svn: 127678
2011-03-15 13:45:47 +00:00
1885d21700
Fix mistyped CHECK lines.
...
llvm-svn: 127366
2011-03-09 22:07:31 +00:00
62f759791a
Be nice to Xcore and the XMOS assembler and avoid quoting section names
...
that contain only letters, digits and the characters "_" and ".".
llvm-svn: 127028
2011-03-04 20:03:14 +00:00
852ab890b5
Bug#9033: For the ELF assembler output, always quote the section name.
...
llvm-svn: 126963
2011-03-03 22:31:08 +00:00
42f52e737e
Add XCore intrinsic for eeu instruction.
...
llvm-svn: 126384
2011-02-24 13:39:18 +00:00
bfa5cc0e08
Add XCore intrinsic for clre instruction.
...
llvm-svn: 126322
2011-02-23 18:52:05 +00:00
4995b05f56
Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable
...
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.
llvm-svn: 126320
2011-02-23 18:35:59 +00:00
2c610aa3ed
Add XCore intrinsic for the setv instruction.
...
llvm-svn: 126315
2011-02-23 16:46:37 +00:00
aab96995f6
Add XCore intrinsic for settw instruction.
...
llvm-svn: 126313
2011-02-23 14:45:03 +00:00
1ae65c7cb8
Add XCore intrinsics for various instructions on ports.
...
llvm-svn: 126132
2011-02-21 18:23:30 +00:00
d9dde78c27
Add intrinsic for setc instruction on the XCore.
...
llvm-svn: 125186
2011-02-09 13:22:12 +00:00
a31b9c2f7c
Add XCore intrinsics for resource instructions.
...
llvm-svn: 124794
2011-02-03 13:14:25 +00:00
8607a67d37
Add support for trampolines on the XCore.
...
llvm-svn: 124722
2011-02-02 14:57:41 +00:00
272e084bca
Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.
...
llvm-svn: 124587
2011-01-31 17:41:44 +00:00
ec517cdf24
Update tests.
...
llvm-svn: 123591
2011-01-16 18:02:57 +00:00
c24048a718
If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.
...
llvm-svn: 121059
2010-12-06 22:39:26 +00:00
f3e9a48584
Enable machine sinking critical edge splitting. e.g.
...
define double @foo(double %x, double %y, i1 %c) nounwind {
%a = fdiv double %x, 3.2
%z = select i1 %c, double %a, double %y
ret double %z
}
Was:
_foo:
divsd LCPI0_0(%rip), %xmm0
testb $1, %dil
jne LBB0_2
movaps %xmm1, %xmm0
LBB0_2:
ret
Now:
_foo:
testb $1, %dil
je LBB0_2
divsd LCPI0_0(%rip), %xmm0
ret
LBB0_2:
movaps %xmm1, %xmm0
ret
This avoids the divsd when early exit is taken.
rdar://8454886
llvm-svn: 114372
2010-09-20 22:52:00 +00:00
4fee6f3bdd
Start function numbering at 0.
...
llvm-svn: 101638
2010-04-17 16:29:15 +00:00
f118f9788b
Split big test into multiple directories to cater to
...
those who don't build all targets.
llvm-svn: 100688
2010-04-07 20:43:35 +00:00
9efbbcbe45
fix AsmPrinter::GetBlockAddressSymbol to always return a unique
...
label instead of trying to form one based on the BB name (which
causes collisions if the name is empty). This fixes PR6608
llvm-svn: 98495
2010-03-14 17:53:23 +00:00
4780109254
Add dag combine to simplify lmul(x, 0, a, b)
...
llvm-svn: 98258
2010-03-11 16:26:35 +00:00
54a2c32670
Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit
...
expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all
operands are zero extended.
llvm-svn: 98168
2010-03-10 18:12:27 +00:00
1a396d53ed
Fold add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if the intermediate
...
results are unused elsewhere.
llvm-svn: 98157
2010-03-10 16:19:31 +00:00
f57aea3d38
Prefer LMUL to MACCU as LMUL has no tied operands.
...
llvm-svn: 98153
2010-03-10 13:27:10 +00:00
0012bc1e41
Custom lower (S|U)MUL_LOHI -> MACC(S|U)
...
llvm-svn: 98152
2010-03-10 13:20:07 +00:00
54dfa01adc
Lower add (mul a, b), c into MACCU / MACCS nodes which translate
...
directly to the maccu / maccs instructions. We handle this in
ExpandADDSUB since after type legalisation it is messy to
recognise these operations.
llvm-svn: 98150
2010-03-10 11:41:08 +00:00
e35eabdd69
Convert test to FileCheck.
...
llvm-svn: 98148
2010-03-10 11:24:03 +00:00
c420c4cb4e
In cases where the carry / borrow unused converted ladd / lsub
...
to an add or a sub.
llvm-svn: 98059
2010-03-09 16:34:25 +00:00
f4e76cf44d
Add DAG combine for ladd / lsub.
...
llvm-svn: 98057
2010-03-09 16:07:47 +00:00
333300e0df
Fix XCoreTargetLowering::isLegalAddressingMode() to handle VoidTy.
...
Previously LoopStrengthReduce would sometimes be unable to find
a legal formula, causing an assertion failure.
llvm-svn: 97226
2010-02-26 16:44:51 +00:00
f578196968
Lower BR_JT on the XCore to a jump into a series of jump instructions.
...
llvm-svn: 96942
2010-02-23 13:25:07 +00:00
Richard Osborne