4 Commits

Author	SHA1	Message	Date
Sanjay Patel	9342a34bbd	use update_llc_test_checks.py to tighten checking; remove unnecessary testing params ... llvm-svn: 234024	2015-04-03 17:09:37 +00:00
David Blaikie	a79ac14fa6	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction ... Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794	2015-02-27 21:17:42 +00:00
Craig Topper	72c8cd7bc3	Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. ... llvm-svn: 192171	2013-10-08 05:53:50 +00:00
Bruno Cardoso Lopes	46b9cde019	Add a AVX version of a simple i64 -> f64 bitcast. This could be ... triggered using llc with -O0, which wouldn't let it be folded and expose the lack of this pattern. llvm-svn: 139320	2011-09-08 21:52:33 +00:00