29705333e5
The x86-64 red zone is now being used.
...
llvm-svn: 64535
2009-02-14 03:30:05 +00:00
c2fde91703
Teach x86 target -soft-float.
...
llvm-svn: 64496
2009-02-13 22:36:38 +00:00
3a8bd17fdb
Remove non-DebugLoc versions of BuildMI from IA64, Mips.
...
llvm-svn: 64438
2009-02-13 02:34:39 +00:00
9bba902c83
Remove non-DebugLoc versions of BuildMI from X86.
...
There were some that might even matter in X86FastISel.
llvm-svn: 64437
2009-02-13 02:33:27 +00:00
57097d2a26
missed file
...
llvm-svn: 64436
2009-02-13 02:32:04 +00:00
215a925766
Remove non-DebugLoc versions of buildMI from Sparc.
...
llvm-svn: 64435
2009-02-13 02:31:35 +00:00
635f2a69d9
Remove non-DebugLoc versions of BuildMI from Alpha and Cell.
...
llvm-svn: 64433
2009-02-13 02:30:42 +00:00
460bfeba8c
Remove refs to non-DebugLoc version of BuildMI from XCore, PIC16.
...
llvm-svn: 64432
2009-02-13 02:29:03 +00:00
e9f623e27c
Remove refs to non-DebugLoc version of BuildMI from PowerPC.
...
llvm-svn: 64431
2009-02-13 02:27:39 +00:00
b851a7853a
and one more file
...
llvm-svn: 64430
2009-02-13 02:26:21 +00:00
7647da67ea
Remove refs to non-DebugLoc versions of BuildMI from ARM.
...
llvm-svn: 64429
2009-02-13 02:25:56 +00:00
65c0fd4c44
Revert this. It was breaking stuff.
...
llvm-svn: 64428
2009-02-13 02:16:35 +00:00
1c21ac3066
Turn off the old way of handling debug information in the code generator. Use
...
the new way, where all of the information is passed on SDNodes and machine
instructions.
llvm-svn: 64427
2009-02-13 02:01:04 +00:00
baca6ed65e
Check in missing file.
...
llvm-svn: 64410
2009-02-12 23:24:44 +00:00
6b8c76a910
Eliminate a couple of non-DebugLoc BuildMI variants.
...
Modify callers.
llvm-svn: 64409
2009-02-12 23:08:38 +00:00
655775293f
Arrange to print constants that match "n" and "i" constraints
...
in inline asm as signed (what gcc does). Add partial support
for x86-specific "e" and "Z" constraints, with appropriate
signedness for printing.
llvm-svn: 64400
2009-02-12 20:58:09 +00:00
844deb73f4
fix PR3538 for ARM.
...
llvm-svn: 64384
2009-02-12 17:38:23 +00:00
4d4c702d5f
fix PR3538 for PPC
...
llvm-svn: 64383
2009-02-12 17:37:15 +00:00
aed3a4215b
fix the X86 backend to just drop llvm.declare nodes for VLAs instead of
...
leaving them in the DAG and then getting selection errors. This is a
fix for PR3538.
llvm-svn: 64382
2009-02-12 17:33:11 +00:00
f6d609a227
Move debug loc info along when the spiller creates new instructions.
...
llvm-svn: 64342
2009-02-12 00:02:55 +00:00
27b508db9b
Propagate DebugLoc info for spiller call-backs.
...
llvm-svn: 64329
2009-02-11 21:51:19 +00:00
27f85854f9
Don't try to set an EFLAGS operand to dead if no instruction was created.
...
This fixes a bug introduced by r61215.
llvm-svn: 64316
2009-02-11 19:50:24 +00:00
589a539423
Handle llvm.x86.sse2.maskmov.dqu in 64-bit.
...
llvm-svn: 64240
2009-02-10 22:06:28 +00:00
df15f13c34
80 col violations.
...
llvm-svn: 64237
2009-02-10 21:39:44 +00:00
c3f7b82628
Function temporaries can not overlap with retval or args.See the comment in source code to know the reason. Anything having .auto. in its name is local to a function in nature irrespective of the linkage specified. print static local variables in module level IDATA section.
...
llvm-svn: 64199
2009-02-10 04:20:26 +00:00
e5ade4a9a1
Implement FpSET_ST1_*.
...
llvm-svn: 64186
2009-02-09 23:32:07 +00:00
a950e99dee
Use doxygen comment syntax.
...
llvm-svn: 64150
2009-02-09 18:12:09 +00:00
64dfcacd5f
Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
...
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.
llvm-svn: 64124
2009-02-09 07:14:22 +00:00
1aca40e349
add a note.
...
llvm-svn: 64093
2009-02-08 20:44:19 +00:00
9c310711bb
Use getDebugLoc forwarder instead of getNode()->getDebugLoc.
...
No functional change.
llvm-svn: 64026
2009-02-07 19:59:05 +00:00
747e55bc9a
Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing
...
ScheduleDAG's TLI member to use const.
llvm-svn: 64018
2009-02-07 16:15:20 +00:00
4ea526268c
Needs this file too.
...
llvm-svn: 63993
2009-02-07 00:56:46 +00:00
62fd95d6ec
Get rid of the last non-DebugLoc versions of getNode!
...
Many targets build placeholder nodes for special operands, e.g.
GlobalBaseReg on X86 and PPC for the PIC base. There's no
sensible way to associate debug info with these. I've left
them built with getNode calls with explicit DebugLoc::getUnknownLoc operands.
I'm not too happy about this but don't see a good improvement;
I considered adding a getPseudoOperand or something, but it
seems to me that'll just make it harder to read.
llvm-svn: 63992
2009-02-07 00:55:49 +00:00
4e3e3deed3
Refactor some repeated logic into a separate function.
...
llvm-svn: 63989
2009-02-07 00:43:41 +00:00
78fe44ed52
Make a comment a doxygen comment.
...
llvm-svn: 63988
2009-02-07 00:42:54 +00:00
84935759d5
Remove more non-DebugLoc getNode variants. Use
...
getCALLSEQ_{END,START} to permit passing no DebugLoc
there. UNDEF doesn't logically have DebugLoc; add
getUNDEF to encapsulate this.
llvm-svn: 63978
2009-02-06 23:05:02 +00:00
400dc2e2e4
Remove more non-DebugLoc versions of getNode.
...
llvm-svn: 63969
2009-02-06 21:50:26 +00:00
b6b0aa2449
Record debug location information in the Dwarf writer.
...
A simple test program shows that debugging works. :-)
llvm-svn: 63968
2009-02-06 21:45:08 +00:00
af8f994681
Use .size and .type on ELF systems; this helps tools that map
...
addresses to symbols.
llvm-svn: 63962
2009-02-06 21:15:52 +00:00
ab8e4425a3
Eliminate remaining non-DebugLoc version of getTargetNode.
...
llvm-svn: 63951
2009-02-06 19:16:40 +00:00
48d6bb9924
Print globl directive for variables with external linkage (global variables).
...
llvm-svn: 63943
2009-02-06 18:24:59 +00:00
066757eea1
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
...
llvm-svn: 63938
2009-02-06 17:43:24 +00:00
b5f0ec3eb7
Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook.
...
llvm-svn: 63936
2009-02-06 17:17:30 +00:00
2c4cf2752d
get rid of some non-DebugLoc getTargetNode variants.
...
llvm-svn: 63909
2009-02-06 02:08:06 +00:00
9f3f72f144
Get rid of one more non-DebugLoc getNode and
...
its corresponding getTargetNode. Lots of
caller changes.
llvm-svn: 63904
2009-02-06 01:31:28 +00:00
f80493bbfd
Remove a non-DebugLoc version of getNode.
...
llvm-svn: 63889
2009-02-05 22:07:54 +00:00
64fdacc27f
A few more isAsCheapAsAMove.
...
llvm-svn: 63852
2009-02-05 08:42:55 +00:00
b842d529a3
Reapply 63765. Patches for clang and llvm-gcc to follow.
...
llvm-svn: 63812
2009-02-05 01:49:45 +00:00
12c572b6fa
Get rid of 3 non-DebugLoc getNode variants.
...
llvm-svn: 63808
2009-02-05 01:01:16 +00:00
7ae8c8b108
Remove non-DebugLoc versions of getMergeValues, ZeroExtendInReg.
...
llvm-svn: 63800
2009-02-05 00:20:09 +00:00
f08a47bb70
Remove non-DebugLoc forms of CopyToReg and CopyFromReg.
...
Adjust callers.
llvm-svn: 63789
2009-02-04 23:02:30 +00:00
ae616c2c61
Reverting 63765. This broke the build of both clang
...
and llvm-gcc.
llvm-svn: 63786
2009-02-04 22:47:25 +00:00
021052a705
Remove non-DebugLoc versions of getLoad and getStore.
...
Adjust the many callers of those versions.
llvm-svn: 63767
2009-02-04 20:06:27 +00:00
6ae3aa83d0
New feature: add support for target intrinsics being defined in the
...
target directories themselves. This also means that VMCore no longer
needs to know about every target's list of intrinsics. Future work
will include converting the PowerPC target to this interface as an
example implementation.
llvm-svn: 63765
2009-02-04 19:47:21 +00:00
e84a7911c4
Bill implemented this.
...
llvm-svn: 63752
2009-02-04 19:09:07 +00:00
553fd7e1eb
add a note, this is why we're faster at SciMark-MonteCarlo with
...
SSE disabled.
llvm-svn: 63751
2009-02-04 19:08:01 +00:00
556d14d483
Minor code cleanups; no functionality change.
...
llvm-svn: 63740
2009-02-04 17:28:58 +00:00
679073b420
Remove non-DebugLoc forms of the exotic forms
...
of Lod and Sto; patch uses.
llvm-svn: 63716
2009-02-04 02:34:38 +00:00
f2bb6f09a3
Remove some more non-DebugLoc versions of construction
...
functions, with callers adjusted to fit.
llvm-svn: 63705
2009-02-04 01:48:28 +00:00
85263882aa
Remove a few non-DebugLoc versions of node creation
...
functions.
llvm-svn: 63703
2009-02-04 01:17:06 +00:00
4379a795fe
Fixes a case where we generate an incorrect mask for pshfhw in the presence
...
of undefs and incorrectly determining if we have punpckldq.
llvm-svn: 63702
2009-02-04 01:16:59 +00:00
bbf13f54e0
Patch up omissions in DebugLoc propagation.
...
llvm-svn: 63693
2009-02-04 00:33:20 +00:00
0404dc11af
Need this file too.
...
llvm-svn: 63674
2009-02-03 22:26:34 +00:00
abf66b8343
Add some DL propagation to places that didn't
...
have it yet. More coming.
llvm-svn: 63673
2009-02-03 22:26:09 +00:00
14f2d9dcbd
DebugLoc propgation
...
llvm-svn: 63664
2009-02-03 21:48:12 +00:00
1eb1ef2cfd
DebugLoc propagation. done with file.
...
llvm-svn: 63656
2009-02-03 20:21:25 +00:00
66e03e6f7b
DebugLoc propagation. 2/3 through file.
...
llvm-svn: 63650
2009-02-03 19:33:06 +00:00
561d1226b6
Tevert part of the x86 subtarget logic changes: when -march=x86-64
...
is given, override the subtarget settings and enable 64-bit support.
This restores the earlier behavior, and fixes regressions on
Non-64-bit-capable x86-32 hosts.
This isn't necessarily the best approach, but the most obvious
alternative is to require -mcpu=x86-64 or -mattr=+64bit to be used
with -march=x86-64 when the host doesn't have 64-bit support. This
makes things little more consistent, but it's less convenient, and
it has the practical drawback of requiring lots of test changes, so
I opted for the above approach for now.
llvm-svn: 63642
2009-02-03 18:53:21 +00:00
e3c78361d3
Create DebugLoc information in FastISel. Several temporary methods were
...
created. Specifically, those BuildMIs which use
"DebugLoc::getUnknownLoc()". I'll remove them soon.
llvm-svn: 63584
2009-02-03 00:55:04 +00:00
7403751e16
Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has
...
SSE2, however it's possible to disable SSE2, and the subtarget support
code thinks that if 64-bit implies SSE2 and SSE2 is disabled then
64-bit should also be disabled. Instead, just mark all the 64-bit
subtargets as explicitly supporting SSE2.
Also, move the code that makes -march=x86-64 enable 64-bit support by
default to only apply when there is no explicit subtarget. If you
need to specify a subtarget and you want 64-bit code, you'll need to
select a subtarget that supports 64-bit code.
llvm-svn: 63575
2009-02-03 00:04:43 +00:00
e83866065b
Only force SSE level if it is not correct.
...
Add an assert to check HasX86_64 status.
llvm-svn: 63552
2009-02-02 21:57:34 +00:00
5dbd26ae0f
remove #if 0 code on Bill's request.
...
llvm-svn: 63542
2009-02-02 20:23:02 +00:00
50aeb12d80
Made the common case of default address space directive as non-virtual for performance reasons. Provide a single virtual interface for directives of all sizes in non-default address spaces.
...
llvm-svn: 63521
2009-02-02 16:53:06 +00:00
dc636c4080
ADD / SUB / SMUL / UMUL with overflow second result top bits must be zero.
...
llvm-svn: 63509
2009-02-02 09:15:04 +00:00
4988c597b3
Add comment.
...
llvm-svn: 63506
2009-02-02 08:19:07 +00:00
50e15bdf81
Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the condition. It's normally transformed by the dag combiner, unless the condition is set by a arithmetic op with overflow.
...
llvm-svn: 63505
2009-02-02 08:07:36 +00:00
a2d1f35e9a
Implement -mno-sse: if SSE is disabled on x86-64, don't store XMM on stack for
...
var-args, and don't allow FP return values
llvm-svn: 63495
2009-02-01 18:15:56 +00:00
3ed768868d
Fix PR3453 and probably a bunch of other potential
...
crashes or wrong code with codegen of large integers:
eliminate the legacy getIntegerVTBitMask and
getIntegerVTSignBit methods, which returned their
value as a uint64_t, so couldn't handle huge types.
llvm-svn: 63494
2009-02-01 18:06:53 +00:00
555a375bb6
Make LowerCallTo and LowerArguments take a DebugLoc
...
argument. Adjust all callers and overloaded versions.
llvm-svn: 63444
2009-01-30 23:10:59 +00:00
8fb81f1b3d
Get rid of the non-DebugLoc-ified getNOT() method.
...
llvm-svn: 63442
2009-01-30 23:03:19 +00:00
c10d810303
Fixed the comment. No functionality change.
...
llvm-svn: 63387
2009-01-30 09:01:44 +00:00
082174cb78
Use sublw for comparison with literals instead of subwf.
...
llvm-svn: 63382
2009-01-30 07:55:25 +00:00
cbb20a6ee1
When PerformBuildVectorCombine, avoid creating a X86ISD::VZEXT_LOAD of
...
an illegal type.
llvm-svn: 63380
2009-01-30 07:07:40 +00:00
964a29f671
Enable emitting of constant values in non-default address space as well. The APIs emitting constants now take an additional parameter signifying the address space in which to emit. The APIs like getData8BitsDirective() etc are made virtual enabling targets to be able to define appropirate directivers for various sizes and address spaces.
...
llvm-svn: 63377
2009-01-30 04:25:10 +00:00
e58ab79f33
Make x86's BT instruction matching more thorough, and add some
...
dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.
llvm-svn: 63266
2009-01-29 01:59:02 +00:00
9150f735fa
Fixed lowering of v816 shuffles.
...
llvm-svn: 63252
2009-01-28 23:11:14 +00:00
5a913d61e3
Rename getAnalysisToUpdate to getAnalysisIfAvailable.
...
llvm-svn: 63198
2009-01-28 13:14:17 +00:00
f31f288863
The memory alignment requirement on some of the mov{h|l}p{d|s} patterns are 16-byte. That is overly strict. These instructions read / write f64 memory locations without alignment requirement.
...
llvm-svn: 63195
2009-01-28 08:35:02 +00:00
5a685a52c1
Add shuffle splat pattern for x86 sse shifts.
...
llvm-svn: 63193
2009-01-28 08:12:05 +00:00
e4510972a6
Suppress a compile time warning.
...
llvm-svn: 63161
2009-01-28 00:53:34 +00:00
70d4c08cfe
Treat [1 x i8] zeroinitializer as a C string, placing such stuff into
...
mergeable string section. I don't see any bad impact of such decision
(rather then placing it into mergeable const section, as it was before),
but at least Darwin linker won't complain anymore.
The problem in LLVM is that we don't have special type for string constants
(like gcc does). Even more, we have two separate types: ConstatArray for non-null
strings and ConstantAggregateZero for null stuff.... It's a bit weird :)
llvm-svn: 63142
2009-01-27 22:29:24 +00:00
0ca1e7c6b6
Reformat the allocation-order arrays to a more conventional style.
...
llvm-svn: 63121
2009-01-27 19:25:38 +00:00
13f18e853f
Respect the DisableRedZone flag on PowerPC.
...
llvm-svn: 63119
2009-01-27 19:19:28 +00:00
f77f0ce21a
Simplify findNonImmUse; return the result using the return value
...
instead of via a by-reference argument. No functionality change.
llvm-svn: 63118
2009-01-27 19:04:30 +00:00
1bc8af207e
Implement multiple with overflow by 2 with an add instruction.
...
llvm-svn: 63090
2009-01-27 03:30:42 +00:00
7740523a89
Eliminate unnecessary operands-list traversals.
...
llvm-svn: 63088
2009-01-27 02:37:43 +00:00
75cee3a93c
Enable the red zone on x86-64 by default.
...
llvm-svn: 63078
2009-01-27 00:58:47 +00:00
1cd2a2c9f8
Fix the Red Zone calculation for functions with frame pointers.
...
Don't use the Red Zone when dynamic stack realignment is needed.
This could be implemented, but most x86-64 ABIs don't require
dynamic stack realignment so it isn't urgent.
llvm-svn: 63074
2009-01-27 00:40:06 +00:00
49483188c3
CellSPU:
...
- Update DWARF debugging support.
llvm-svn: 63059
2009-01-26 22:33:37 +00:00
3789a13c30
Make the Dwarf macro information section optional; CellSPU's assembler
...
doesn't support it. The default is set to 'true', so this should not
impact any other target backends.
llvm-svn: 63058
2009-01-26 22:32:51 +00:00
b6d36e1d14
Implement Red Zone utilization on x86-64. This is currently
...
disabled by default; I'll enable it when I hook it up with
the llvm-gcc flag which controls it.
llvm-svn: 63056
2009-01-26 22:22:31 +00:00
6c7e85142b
Enhance logic in X86DAGToDAGISel::PreprocessForRMW which move load inside callseq_start to allow it to be folded into a call. It was not considering the cases where a token factor is between the load and the callseq_start.
...
llvm-svn: 63022
2009-01-26 18:43:34 +00:00
8e4ac9b71a
Take the next steps in making SDUse more consistent with LLVM Use, and
...
tidy up SDUse and related code.
- Replace the operator= member functions with a set method, like
LLVM Use has, and variants setInitial and setNode, which take
care up updating use lists, like LLVM Use's does. This simplifies
code that calls these functions.
- getSDValue() is renamed to get(), as in LLVM Use, though most
places can either use the implicit conversion to SDValue or the
convenience functions instead.
- Fix some more node vs. value terminology issues.
Also, eliminate the one remaining use of SDOperandPtr, and
SDOperandPtr itself.
llvm-svn: 62995
2009-01-26 04:35:06 +00:00
95b2a206ee
Untabify code.
...
llvm-svn: 62991
2009-01-26 03:37:41 +00:00
9e3e4a9219
CellSPU:
...
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll
- Fix select_bits.ll test
- Capitulate to the DAGCombiner and move i64 constant loads to instruction
selection (SPUISelDAGtoDAG.cpp).
<rant>DAGCombiner will insert all kinds of 64-bit optimizations after
operation legalization occurs and now we have to do most of the work that
instruction selection should be doing twice (once to determine if v2i64
build_vector can be handled by SelectCode(), which then runs all of the
predicates a second time to select the necessary instructions.) But,
CellSPU is a good citizen.</rant>
llvm-svn: 62990
2009-01-26 03:31:40 +00:00
624801e87e
Fix a typo
...
llvm-svn: 62989
2009-01-26 03:15:54 +00:00
a2550a8e96
De-identifying per sabre review
...
llvm-svn: 62988
2009-01-26 03:15:31 +00:00
5eca265519
Map address space 256 to gs; similar mappings could be supported for the
...
other x86 segments. address space 0 is stack/default, 1-255 are reserved for
client use.
llvm-svn: 62980
2009-01-26 01:24:32 +00:00
8a51d8c8f7
Support pattern matching various x86 sse shifts.
...
llvm-svn: 62979
2009-01-26 00:52:55 +00:00
80b283c1cd
silence a warning when assertions are disabled.
...
llvm-svn: 62976
2009-01-25 23:08:00 +00:00
692ed0f67d
should have removed the + when manually applying a patch!
...
llvm-svn: 62973
2009-01-25 20:29:34 +00:00
97be2f5840
revert this patch for now, because Codegen does still want to generate SSE code,
...
for example in the case of va-args. XFAIL associated tests.
llvm-svn: 62972
2009-01-25 20:21:24 +00:00
a23c73bbdc
If user explicitly asks not to use SSE, don't force it. This fixes LLVM part of PR3402.
...
llvm-svn: 62967
2009-01-25 17:58:56 +00:00
1c7c019229
Private linkage support for PPC / Darwin.
...
llvm-svn: 62955
2009-01-25 06:32:01 +00:00
b09b0242ca
Fix an indent and a typo.
...
llvm-svn: 62940
2009-01-24 22:12:48 +00:00
3cedd4dc64
add note about possible GEP improvement with fields of size 0.
...
llvm-svn: 62925
2009-01-24 19:30:25 +00:00
832959536a
hopefully address PR3379 by making the P modifier work in x86 inline asm.
...
llvm-svn: 62887
2009-01-23 22:33:40 +00:00
c58900504b
Add SelectionDAG::getNOT method to construct bitwise NOT operations,
...
corresponding to the "not" and "vnot" PatFrags. Use the new method
in some places where it seems appropriate.
llvm-svn: 62768
2009-01-22 17:39:32 +00:00
4a0bf66eb8
Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.
...
llvm-svn: 62762
2009-01-22 09:10:11 +00:00
705ac7082b
add a note
...
llvm-svn: 62760
2009-01-22 07:16:03 +00:00
31dd016f81
Recognize inline asm for bswap on x86-64 GLIBC. This allows it
...
to be supported in the JIT.
llvm-svn: 62730
2009-01-21 23:40:54 +00:00
ec5eb161fd
Also favors NOT64r.
...
llvm-svn: 62710
2009-01-21 19:45:31 +00:00
a326520190
fix warning in release-asserts mode and spelling of assert.
...
llvm-svn: 62699
2009-01-21 18:38:18 +00:00
b43c8996f2
Fix a recent regression. ClrOpcode is not set for i8; for i8, if
...
we want to clear %ah to zero before a division, just use a
zero-extending mov to %al. This fixes PR3366.
llvm-svn: 62691
2009-01-21 14:50:16 +00:00
335ea6cf2a
Fixed build warnings. Restoring changes done in 62600, they were lost in 62655.
...
llvm-svn: 62681
2009-01-21 09:02:46 +00:00
be7e41481b
Cleanup whitespace and comments, and tweak some
...
prototypes, in operand type legalization. No
functionality change.
llvm-svn: 62680
2009-01-21 09:00:29 +00:00
f737337707
Implement LowerOperationWrapper for legalizer.
...
Also a few signed comparison fixes.
llvm-svn: 62665
2009-01-21 05:44:05 +00:00
ed7d79fce4
CellSPU:
...
- Ensure that (operation) legalization emits proper FDIV libcall when needed.
- Fix various bugs encountered during llvm-spu-gcc build, along with various
cleanups.
- Start supporting double precision comparisons for remaining libgcc2 build.
Discovered interesting DAGCombiner feature, which is currently solved via
custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner
insists on inserting one anyway.)
- Update README.
llvm-svn: 62664
2009-01-21 04:58:48 +00:00
201501995f
Favors generating "not" over "xor -1". For example.
...
unsigned test(unsigned a) {
return ~a;
}
llvm used to generate:
movl $4294967295, %eax
xorl 4(%esp), %eax
Now it generates:
movl 4(%esp), %eax
notl %eax
It's 3 bytes shorter.
llvm-svn: 62661
2009-01-21 02:09:05 +00:00
c544cb0eca
Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
...
llvm-svn: 62600
2009-01-20 19:12:24 +00:00
83d2e066c1
Add a README entry noticed while investigating PR3216.
...
llvm-svn: 62558
2009-01-20 01:07:33 +00:00
44cc554311
DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it.
...
llvm-svn: 62519
2009-01-19 19:06:11 +00:00
0346c04f39
Fix 80 col violations.
...
llvm-svn: 62518
2009-01-19 18:57:29 +00:00
6c02498215
Handle ISD::DECLARE with PIC relocation model.
...
llvm-svn: 62516
2009-01-19 18:31:51 +00:00
8f367e53c7
Minor tweak to LowerUINT_TO_FP_i32. Bias (after scalar_to_vector) has two uses so we should make it the second source operand of ISD::OR so 2-address pass won't have to be smart about commuting.
...
%reg1024<def> = MOVSDrm %reg0, 1, %reg0, <cp#0>, Mem:LD(8,8) [ConstantPool + 0]
%reg1025<def> = MOVSD2PDrr %reg1024
%reg1026<def> = MOVDI2PDIrm <fi#-1>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack-1 + 0]
%reg1027<def> = ORPSrr %reg1025<kill>, %reg1026<kill>
%reg1028<def> = MOVPD2SDrr %reg1027<kill>
%reg1029<def> = SUBSDrr %reg1028<kill>, %reg1024<kill>
%reg1030<def> = CVTSD2SSrr %reg1029<kill>
MOVSSmr <fi#0>, 1, %reg0, 0, %reg1030<kill>, Mem:ST(4,4) [FixedStack0 + 0]
%reg1031<def> = LD_Fp32m80 <fi#0>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack0 + 0]
RET %reg1031<kill>, %ST0<imp-use,kill>
The reason 2-addr pass isn't smart enough to commute the ORPSrr is because it can't look pass the MOVSD2PDrr instruction.
llvm-svn: 62505
2009-01-19 08:19:57 +00:00
7e9ef4d776
Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
...
optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself.
llvm-svn: 62504
2009-01-19 08:08:22 +00:00
f9291cf43c
Extend thi
...
llvm-svn: 62415
2009-01-17 07:40:19 +00:00
bf38a5e540
Fix MatchAddress bug that's preventing negative displacement from being folded in 64-bit mode.
...
llvm-svn: 62413
2009-01-17 07:09:27 +00:00
dd40f26877
Temporarily revert my last change. It is causing a bootstrap failure.
...
llvm-svn: 62405
2009-01-17 04:23:51 +00:00
4d5275905e
Implement a special algorithm for converting uint_to_fp for i32 values on
...
X86. This code:
void f() {
uint32_t x;
float y = (float)x;
}
used to be:
movl %eax, -8(%ebp)
movl [2^52 double], -4(%ebp)
movsd -8(%ebp), %xmm0
subsd [2^52 double], %xmm0
cvtsd2ss %xmm0, %xmm0
Is now:
movsd [2^52 double], %xmm0
movsd %xmm0, %xmm1
movd %ecx, %xmm2
orps %xmm2, %xmm1
subsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm0
This is faster on X86. Note that there's an extra load of %xmm0 into %xmm1. That
will be fixed in a later coalescer fix.
llvm-svn: 62404
2009-01-17 03:56:04 +00:00
90cc7050f2
CMake: Add lib/Target/IA64/IA64Subtarget.cpp
...
llvm-svn: 62394
2009-01-17 01:50:32 +00:00
41e9f6a854
Fix PPC ISD::Declare isel and eliminate the need for PPCTargetLowering::LowerGlobalAddress to check if isVerifiedDebugInfoDesc() is true. Given the recent changes, it would falsely return true for a lot of GlobalAddressSDNode's.
...
llvm-svn: 62373
2009-01-16 22:57:32 +00:00
703a6c7274
Give IA64 a TargetSubtarget subclass, so that it can
...
implement getSubtargetImpl.
llvm-svn: 62369
2009-01-16 22:49:36 +00:00
e04334730e
Add support for non-zero __builtin_return_address values on X86.
...
llvm-svn: 62338
2009-01-16 19:25:27 +00:00
d243c0e3d9
ARMCompilationCallback should not save / restore vfp registers if vfp is not available.
...
llvm-svn: 62299
2009-01-16 02:16:37 +00:00
ceac7c34f1
Initial hazard recognizer support in post-pass scheduling. This includes
...
a new toy hazard recognizier heuristic which attempts to direct the
scheduler to avoid clumping large groups of loads or stores too densely.
llvm-svn: 62291
2009-01-16 01:33:36 +00:00
7e105f0b12
Generalize the HazardRecognizer interface so that it can be used
...
to support MachineInstr-based scheduling in addition to
SDNode-based scheduling.
llvm-svn: 62284
2009-01-15 22:18:12 +00:00
f2831d6cd1
Fix Alpha test and support for private linkage.
...
llvm-svn: 62282
2009-01-15 21:51:46 +00:00
ebfafee903
Expand insert/extract of a <4 x i32> with a variable index.
...
llvm-svn: 62281
2009-01-15 21:10:20 +00:00
6de96a1b5d
Add the private linkage.
...
llvm-svn: 62279
2009-01-15 20:18:42 +00:00
619ef48a52
Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
...
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.
To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.
llvm-svn: 62275
2009-01-15 19:20:50 +00:00
dbb22a4483
Add load-folding table entries for BT*ri8 instructions.
...
llvm-svn: 62267
2009-01-15 17:57:09 +00:00
0ad43ca6e5
Make getWidenVectorType const.
...
llvm-svn: 62265
2009-01-15 17:34:08 +00:00
02b93136e9
Const-qualify getPreIndexedAddressParts and friends.
...
llvm-svn: 62259
2009-01-15 16:29:45 +00:00
40119780a8
Don't fold address calculations which use negative offsets into
...
the ADDRspii addressing mode.
llvm-svn: 62258
2009-01-15 11:32:30 +00:00
502b91a35c
Update the operands used when building LDAWSP instructions to match the .td
...
changes in the last commit.
llvm-svn: 62257
2009-01-15 11:18:53 +00:00
a292fc6d6b
- Convert remaining i64 custom lowering into custom instruction emission
...
sequences in SPUDAGToDAGISel.cpp and SPU64InstrInfo.td, killing custom
DAG node types as needed.
- i64 mul is now a legal instruction, but emits an instruction sequence
that stretches tblgen and the imagination, as well as violating laws of
several small countries and most southern US states (just kidding, but
looking at a function with 80+ parameters is really weird and just plain
wrong.)
- Update tests as needed.
llvm-svn: 62254
2009-01-15 04:41:47 +00:00
4359325ba8
Add pseudo instructions to the XCore for (load|store|load address) of a
...
frame index. eliminateFrameIndex will replace these instructions with
(LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use.
This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame
pointer elimination. However since they were marked as implicitly using
SP they could not be rematerialised.
llvm-svn: 62238
2009-01-14 18:26:46 +00:00
b0a78f8fa1
fix memleaks
...
llvm-svn: 62198
2009-01-13 23:35:49 +00:00
a63bede3c6
BT appears to be available on all >= i386 chips.
...
llvm-svn: 62196
2009-01-13 23:27:15 +00:00
d3942af5cb
Don't use a BT instruction if the AND has multiple uses.
...
llvm-svn: 62195
2009-01-13 23:25:30 +00:00
b8f5ba6781
Disable the register+memory forms of the bt instructions for now. Thanks
...
to Eli for pointing out that these forms don't ignore the high bits of
their index operands, and as such are not immediately suitable for use
by isel.
llvm-svn: 62194
2009-01-13 23:23:30 +00:00
0fdf71cb9d
Add bt instructions that take immediate operands.
...
llvm-svn: 62180
2009-01-13 20:33:23 +00:00
eb2591bbdd
Fix a few more JIT encoding issues in the BT instructions.
...
llvm-svn: 62179
2009-01-13 20:32:45 +00:00
45da8b779c
Checking in conditionals, function call, arrays and libcalls implementation.
...
llvm-svn: 62174
2009-01-13 19:18:47 +00:00
1a579351d2
make -march=cpp handle the nocapture attribute, make it assert if it
...
sees attributes it doesn't know.
llvm-svn: 62155
2009-01-13 07:22:22 +00:00
5c6e1e3b7d
Use DebugInfo interface to lower dbg_* intrinsics.
...
llvm-svn: 62127
2009-01-13 00:35:13 +00:00
dc020f9c3c
Rename getABITypeSize to getTypePaddedSize, as
...
suggested by Chris.
llvm-svn: 62099
2009-01-12 20:38:59 +00:00
5a272e79e5
80 col violation.
...
llvm-svn: 62024
2009-01-10 03:33:22 +00:00
5cbf223916
Removed trailing whitespace from Makefiles.
...
llvm-svn: 61991
2009-01-09 16:44:42 +00:00
bdc0f8b627
Add load-folding table entries for MOVDQA.
...
llvm-svn: 61972
2009-01-09 02:40:34 +00:00
e907a0a527
Whitespace and other minor adjustments to make SSE instructions have
...
the same formatting as their corresponding SSE2 instructions, for
consistency.
llvm-svn: 61971
2009-01-09 02:27:34 +00:00
f646668799
Convert DwarfWriter into a pass.
...
Now Users request DwarfWriter through getAnalysisUsage() instead of creating an instance of DwarfWriter object directly.
llvm-svn: 61955
2009-01-08 23:40:34 +00:00
6c2ee50e28
add some more crazy strlen and memcpy stuff I noticed in spec.
...
llvm-svn: 61918
2009-01-08 07:34:55 +00:00
7cb3ae0505
add some notes about strlen craziness in eon.
...
llvm-svn: 61917
2009-01-08 06:52:57 +00:00
b51cdfadda
Fix off-by-one error in traversing an array; this fixes a test.
...
The error was reported by gcc-4.3.0 during compilation.
llvm-svn: 61896
2009-01-07 23:07:29 +00:00
8e8d1da35a
Add patterns to match conditional moves with loads folded
...
into their left operand, rather than their right. Do this
by commuting the operands and inverting the condition.
llvm-svn: 61842
2009-01-07 01:00:24 +00:00
1e6e9a8b9b
Add load-folding table entries for cmovno too.
...
llvm-svn: 61841
2009-01-07 00:44:53 +00:00
7e47cc7cda
Define instructions for cmovo and cmovno.
...
llvm-svn: 61836
2009-01-07 00:35:10 +00:00
33e6fcd56f
X86_COND_C and X86_COND_NC are alternate mnemonics for
...
X86_COND_B and X86_COND_AE, respectively.
llvm-svn: 61835
2009-01-07 00:15:08 +00:00
beac19e299
Revert r42653 and forward-port the code that lets INC64_32r be
...
converted to LEA64_32r in x86's convertToThreeAddress. This
replaces code like this:
movl %esi, %edi
inc %edi
with this:
lea 1(%rsi), %edi
which appears to be beneficial.
llvm-svn: 61830
2009-01-06 23:34:46 +00:00
494daa7435
CellSPU:
...
- Add preliminary support for v2i32; load/store generates the right code but
there's a lot work to be done to make this vector type operational.
llvm-svn: 61829
2009-01-06 23:10:38 +00:00
6ad9b39a09
CellSPU: Update the README
...
llvm-svn: 61785
2009-01-06 03:51:14 +00:00
6887caf11c
CellSPU:
...
- Fix bugs 3194, 3195: i128 load/stores produce correct code (although, we
need to ensure that i128 is 16-byte aligned in real life), and 128 zero-
extends are supported.
- New td file: SPU128InstrInfo.td: this is where all new i128 support should
be put in the future.
- Continue to hammer on i64 operations and test cases; ensure that the only
remaining problem will be i64 mul.
llvm-svn: 61784
2009-01-06 03:36:14 +00:00
f9b5ba7bcb
Revert r61415 and r61484. Duncan was correct that these weren't needed.
...
llvm-svn: 61765
2009-01-05 22:53:45 +00:00
906152a20f
Tidy up #includes, deleting a bunch of unnecessary #includes.
...
llvm-svn: 61715
2009-01-05 17:59:02 +00:00
56a8bb670f
squash warnings.
...
llvm-svn: 61707
2009-01-05 17:31:22 +00:00
c3b09c3baa
Atom and Core i7 do not have same model number after all.
...
llvm-svn: 61686
2009-01-05 08:45:01 +00:00
74f249517e
CellSPU:
...
- Teach SPU64InstrInfo.td about the remaining signed comparisons, update tests
accordingly.
llvm-svn: 61672
2009-01-05 04:05:53 +00:00
a664240476
CellSPU:
...
- Fix (brcond (setq ...)) bug, where BRNZ should have been used vice BRZ.
- Kill unused/unnecessary nodes in SPUNodes.td
- Beef out the i64operations.c test harness to use a lot of unaligned
loads, test loops and LLVM loop/basic block optimizations; run the
test harness successfully on real Cell hardware.
llvm-svn: 61664
2009-01-05 01:34:35 +00:00
6e100a62b1
Add Intel processors core i7 and atom.
...
llvm-svn: 61603
2009-01-03 04:24:44 +00:00
9a3ec1b208
Fix PR3210: Detect more Intel processors. Patch by Torok Edwin.
...
llvm-svn: 61602
2009-01-03 04:04:46 +00:00
6a1f6279ad
CellSPU:
...
- Remove custom lowering for BRCOND
- Add remaining functionality for branches in SPUInstrInfo, such as branch
condition reversal and load/store folding. Updated BrCond test to reflect
branch reversal.
llvm-svn: 61597
2009-01-03 00:27:53 +00:00
6d24def98a
- Make copyRegToReg use the "LR" assembler synonym for "OR". Makes finding
...
register copies a little easier to pick out from the output.
- Fix bug 3192.
llvm-svn: 61591
2009-01-02 20:52:08 +00:00
4c91aa3418
Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.
...
llvm-svn: 61557
2009-01-02 05:35:45 +00:00
13f3a33f44
Fix x86 CPU id detection to identify Penryn (and future processors).
...
llvm-svn: 61556
2009-01-02 05:29:20 +00:00
1671a309fd
Use movaps / movd to extract vector element 0 even with sse4.1. It's still cheaper than pextrw especially if the value is in memory.
...
llvm-svn: 61555
2009-01-02 05:29:08 +00:00
8feb694e8f
Fix PR3274: when promoting the condition of a BRCOND node,
...
promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType. In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).
llvm-svn: 61542
2009-01-01 15:52:00 +00:00
a41422566b
add a note
...
llvm-svn: 61513
2008-12-31 00:54:13 +00:00
41236c0cf3
- Start moving target-dependent nodes that could be represented by an
...
instruction sequence and cannot ordinarily be simplified by DAGcombine
into the various target description files or SPUDAGToDAGISel.cpp.
This makes some 64-bit operations legal.
- Eliminate target-dependent ISD enums.
- Update tests.
llvm-svn: 61508
2008-12-30 23:28:25 +00:00
03f2af79b8
Linux wants the FDE initial location and address range to be forced to 32-bit.
...
Darwin doesn't. Make this optional for platforms.
llvm-svn: 61484
2008-12-29 22:12:11 +00:00
a27b796fec
Fixed spelling, removed trailing whitespace.
...
llvm-svn: 61477
2008-12-29 20:08:23 +00:00
b8ee30de6d
- Various '#if 0' cleanups.
...
- Move v4i32, i32 mul into SPUInstrInfo.td, with a few more instruction
cleanups there as well.
- Make SMUL_LOHI, UMUL_LOHI competely illegal for Cell SPU, to better
assist Chris to see the problem in bug 3101.
llvm-svn: 61464
2008-12-29 03:23:36 +00:00
8233527b05
- Remove Tilmann's custom truncate lowering: it completely hosed over
...
DAGcombine's ability to find reasons to remove truncates when they were not
needed. Consequently, the CellSPU backend would produce correct, but _really
slow and horrible_, code.
Replaced with instruction sequences that do the equivalent truncation in
SPUInstrInfo.td.
- Re-examine how unaligned loads and stores work. Generated unaligned
load code has been tested on the CellSPU hardware; see the i32operations.c
and i64operations.c in CodeGen/CellSPU/useful-harnesses. (While they may be
toy test code, it does prove that some real world code does compile
correctly.)
- Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc
fault because i64 ult is not yet implemented.)
- Added i64 eq and neq for setcc and select/setcc; started new instruction
information file for them in SPU64InstrInfo.td. Additional i64 operations
should be added to this file and not to SPUInstrInfo.td.
llvm-svn: 61447
2008-12-27 04:51:36 +00:00
2a7c988627
Add a simple pattern for matching 'bt'.
...
llvm-svn: 61426
2008-12-25 05:34:37 +00:00
1b8c9f795a
Fix some JIT encodings.
...
llvm-svn: 61425
2008-12-25 01:32:49 +00:00
d1dfdab973
BT memory operands load from their address operand.
...
llvm-svn: 61424
2008-12-25 01:27:10 +00:00
8175f27d3f
translateX86CC can never fail. Simplify it based on this.
...
llvm-svn: 61423
2008-12-24 23:53:05 +00:00
d6bd7e9372
Darwin likes for the EH frame to be non-local.
...
llvm-svn: 61420
2008-12-24 08:05:17 +00:00
066b5f6724
GCC doesn't emit DW_EH_PE_sdata4 for the FDE encoding on Darwin. I'm not sure
...
about other platforms.
llvm-svn: 61415
2008-12-24 05:25:49 +00:00
198b8e78c3
Fix a compiler-abort on a testcase where the stack-pointer is added to
...
a symbolic constant. This is unlikely to be intentional, but it
shouldn't crash the compiler.
llvm-svn: 61408
2008-12-24 00:27:51 +00:00
4b46b74ece
indentation
...
llvm-svn: 61407
2008-12-24 00:11:37 +00:00
e9988b661d
simplify some control flow and reduce indentation, no functionality change.
...
llvm-svn: 61404
2008-12-23 23:42:27 +00:00
25a767d7f4
Add instruction patterns and encodings for the x86 bt instructions.
...
llvm-svn: 61400
2008-12-23 22:45:23 +00:00
3d188347a4
Silence unused variable warnings.
...
llvm-svn: 61392
2008-12-23 21:56:28 +00:00
12f2490489
Clean up the atomic opcodes in SelectionDAG.
...
This removes all the _8, _16, _32, and _64 opcodes and replaces each
group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode
is now used to carry the size information. In tablegen, the size-specific
opcodes are replaced by size-independent opcodes that utilize the
ability to compose them with predicates.
This shrinks the per-opcode tables and makes the code that handles
atomics much more concise.
llvm-svn: 61389
2008-12-23 21:37:04 +00:00
8a35adf3a5
add some notes for simplifylibcalls optimizations
...
llvm-svn: 61385
2008-12-23 20:52:52 +00:00
ec95070ca3
Fixed code generation for v8i16 and v16i8 splats on X86.
...
Fixed lowering of v8i16 shuffles for v8i16 when we fall back to extract/insert.
llvm-svn: 61365
2008-12-23 04:03:27 +00:00
d72358cba8
Make the fuse-failed debug output human-readable.
...
llvm-svn: 61356
2008-12-23 00:19:20 +00:00
ab316350bf
Fix fast-isel to not emit invalid assembly when presented with a
...
constant shift count that doesn't fit in the shift instruction's
immediate field. This fixes PR3242.
llvm-svn: 61281
2008-12-20 17:19:40 +00:00
b289d4163b
Move the patterns which have i8 immediates before the patterns
...
that have i32 immediates so that they get selected first. This
currently only matters in the JIT, as assemblers will
automatically use the smallest encoding.
llvm-svn: 61250
2008-12-19 18:25:21 +00:00
9c148c8fc2
Fix some release-assert warnings
...
llvm-svn: 61244
2008-12-19 17:03:38 +00:00
770b4b830a
Fix bug 3202.
...
The EH_frame and .eh symbols are now private, except for darwin9 and earlier.
The patch also fixes the definition of PrivateGlobalPrefix on pcc linux.
llvm-svn: 61242
2008-12-19 10:55:56 +00:00
69cd963b9a
When emitting instructions that define EFLAGS and the EFLAGS value isn't
...
used, mark the defs as dead.
llvm-svn: 61215
2008-12-18 22:03:42 +00:00
975f78ae79
When setting up the frame pointer, add it as a live-in register to all
...
non-entry blocks, so that it doesn't appear use-before-def anywhere.
llvm-svn: 61214
2008-12-18 22:01:52 +00:00
998fd29ce1
Fixed x86 code generation of multiple for v2i64. It was incorrect for SSE4.1.
...
llvm-svn: 61211
2008-12-18 21:42:19 +00:00
49c44fa014
Mark the x86 fp stack registers as "reserved". This tells LiveVariables
...
and the RegisterScavenger not to expect traditional liveness
techniques are applicable to these registers, since we don't fully
modify the effects of push and pop after stackification.
llvm-svn: 61179
2008-12-18 01:05:09 +00:00
b9a012156b
Add initial support for back-scheduling address computations,
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especially in the case of addresses computed from loop induction
variables.
llvm-svn: 61075
2008-12-16 03:35:01 +00:00
5d196e64f1
add some more notes.
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llvm-svn: 61033
2008-12-15 08:32:28 +00:00
81ee731852
Add a testcase for GCC PR 23455, which lpre handles now. Add some
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comments about why we're not getting other cases.
llvm-svn: 61032
2008-12-15 07:49:24 +00:00
3c2c36b590
gvn now hoists this load out of the hot non-call path.
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llvm-svn: 61028
2008-12-15 06:34:48 +00:00
a66e9f4218
silence warning when asserts disabled.
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llvm-svn: 61014
2008-12-14 21:38:24 +00:00
c3d36efbb5
silence warning when asserts disabled.
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llvm-svn: 61013
2008-12-14 21:37:33 +00:00
c4499feb1a
- Use patterns instead of creating completely new instruction matching patterns,
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which are identical to the original patterns.
- Change the multiply with overflow so that we distinguish between signed and
unsigned multiplication. Currently, unsigned multiplication with overflow
isn't working!
llvm-svn: 60963
2008-12-12 21:15:41 +00:00
dd6f3dbd05
Don't make use of an illegal type (i64) when
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lowering f64 function arguments.
llvm-svn: 60944
2008-12-12 08:05:40 +00:00
9c2d26d208
Added support for SELECT v8i8 v4i16 for X86 (MMX)
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Added support for TRUNC v8i16 to v8i8 for X86 (MMX)
llvm-svn: 60916
2008-12-12 01:25:51 +00:00
1a317678bc
Redo the arithmetic with overflow architecture. I was changing the semantics of
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ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace
the intrinsic with an ISD::SADDO node. Then custom lower that into an
X86ISD::ADD node with a associated SETCC that checks the correct condition code
(overflow or carry). Then that gets lowered into the correct X86::ADDOvf
instruction.
Similar for SUB and MUL instructions.
llvm-svn: 60915
2008-12-12 00:56:36 +00:00
a52c3b4b8b
Fix a 80 col. violation.
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llvm-svn: 60901
2008-12-11 22:02:02 +00:00
d5021730c8
Preliminary ARM debug support based on patch by Mikael of FlexyCore.
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llvm-svn: 60851
2008-12-10 21:54:21 +00:00
01fa50ca4f
Some code clean up.
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llvm-svn: 60850
2008-12-10 21:49:05 +00:00
517d05fd00
Only perform SETO/SETC to JO/JC conversion if extractvalue is coming from an arithmetic with overflow instruction.
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llvm-svn: 60844
2008-12-10 19:44:24 +00:00
0b77319742
Fix MachineCodeEmitter to use uintptr_t instead of intptr_t. This avoids some overflow issues. Patch by Thomas Jablin.
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llvm-svn: 60828
2008-12-10 02:32:19 +00:00
f482f379ef
Whitespace changes.
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llvm-svn: 60826
2008-12-10 02:01:32 +00:00
56fe52e287
move an entry, add some notes, remove a completed item (IMPLICIT_DEF)
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llvm-svn: 60821
2008-12-10 01:30:48 +00:00
a2495508cd
CellSPU:
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- Fix bug 3185, with misc other cleanups.
- Needed to implement SPUInstrInfo::InsertBranch(). CAUTION: Not sure what
gets or needs to get passed to InsertBranch() to insert a conditional
branch. This will abort for now until a good test case shows up.
llvm-svn: 60811
2008-12-10 00:15:19 +00:00
8008cb9a77
Implement fast-isel conversion of a branch instruction that's branching on an
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overflow/carry from the "arithmetic with overflow" intrinsics. It searches the
machine basic block from bottom to top to find the SETO/SETC instruction that is
its conditional. If an instruction modifies EFLAGS before it reaches the
SETO/SETC instruction, then it defaults to the normal instruction emission.
llvm-svn: 60807
2008-12-09 23:19:12 +00:00
db8ec2d75a
Add sub/mul overflow intrinsics. This currently doesn't have a
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target-independent way of determining overflow on multiplication. It's very
tricky. Patch by Zoltan Varga!
llvm-svn: 60800
2008-12-09 22:08:41 +00:00
3812542a2c
Handle a compiler warning.
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llvm-svn: 60755
2008-12-09 09:58:11 +00:00
e25d3417f5
Correct my English.
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llvm-svn: 60753
2008-12-09 07:55:31 +00:00
8deac5db5a
CellSPU:
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- Change default scheduling preference to list-burr, which produces somewhat
better code than the default. Could also use list-tdrr, but need to ask
dev list about the appropriate handy mnemonic before commiting.
llvm-svn: 60738
2008-12-09 03:37:19 +00:00
Dan Gohman