12da8ce3d2
Introduce new linkage types linkonce_odr, weak_odr, common_odr
...
and extern_weak_odr. These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global. In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time. This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function. If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body. The
code generators on the other hand map weak and weak_odr linkage
to the same thing.
llvm-svn: 66339
2009-03-07 15:45:40 +00:00
ff659b5b86
Arithmetic instructions don't set EFLAGS bits OF and CF bits
...
the same say the "test" instruction does in overflow cases,
so eliminating the test is only safe when those bits aren't
needed, as is the case for COND_E and COND_NE, or if it
can be proven that no overflow will occur. For now, just
restrict the optimization to COND_E and COND_NE and don't
do any overflow analysis.
llvm-svn: 66318
2009-03-07 01:58:32 +00:00
c719d73eec
Don't use plain INC32 and DEC32 on x86-64; it needs
...
INC64_32r and INC64_16r, because these instructions are encoded
differently on x86-64. This fixes JIT regressions on x86-64 in
kimwitu++ and others.
llvm-svn: 66207
2009-03-05 21:32:23 +00:00
e014b193c9
When creating X86ISD::INC and X86ISD::DEC nodes, only add one operand.
...
The extra operand didn't appear to cause any trouble, but it was
erroneous regardless.
llvm-svn: 66206
2009-03-05 21:29:28 +00:00
2c2f192c74
Fix the "test" optimization to recognize "dec" as an add of
...
negative one, as subtracts of immediates are canonicalized
to adds.
llvm-svn: 66180
2009-03-05 19:32:48 +00:00
55d7b2ac4f
Re-apply 66008, now that the unfoldMemoryOperand bug is fixed.
...
llvm-svn: 66058
2009-03-04 19:44:21 +00:00
f8920d0c75
Correct this comment.
...
llvm-svn: 66057
2009-03-04 19:24:25 +00:00
cc329b567d
When using MachineInstr operand indices on SDNodes, the number
...
of MachineInstr def operands must be subtracted out. This bug
was uncovered by the recent x86 EFLAGS optimization. Before
that, the only instructions that ever needed unfolding were
things like CMP32rm, where NumDefs is zero.
llvm-svn: 66056
2009-03-04 19:23:38 +00:00
9edd616b59
Fix PR3666: isel calls to constant addresses.
...
llvm-svn: 66024
2009-03-04 06:48:53 +00:00
6728f892be
Revert r66004 for now; it's causing a variety of test failures.
...
llvm-svn: 66008
2009-03-04 03:54:19 +00:00
fe8d71f42a
Teach the x86 backend to eliminate "test" instructions by using the EFLAGS
...
result from add, sub, inc, and dec instructions in simple cases.
llvm-svn: 66004
2009-03-04 02:33:24 +00:00
b8905c4e2c
Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs.
...
llvm-svn: 65996
2009-03-04 01:41:49 +00:00
3a72265d41
Add '(implicit EFLAGS)' for AND, OR, XOR, NEG, INC, and DEC
...
instructions. These aren't used yet.
llvm-svn: 65965
2009-03-03 19:53:46 +00:00
530e038940
Use early exit to reduce indentation. No functional change.
...
llvm-svn: 65962
2009-03-03 19:26:27 +00:00
92b551bc2b
Fix a bunch of Doxygen syntax issues. Escape special characters,
...
and put @file directives on their own comment line.
llvm-svn: 65920
2009-03-03 02:55:14 +00:00
85cefe8567
Generalize BuildVectorSDNode::isConstantSplat to use APInts and handle
...
arbitrary vector sizes. Add an optional MinSplatBits parameter to specify
a minimum for the splat element size. Update the PPC target to use the
revised interface.
llvm-svn: 65899
2009-03-02 23:24:16 +00:00
d8ea0e144e
Combine PPC's GetConstantBuildVectorBits and isConstantSplat functions to a new
...
method in a BuildVectorSDNode "pseudo-class".
llvm-svn: 65747
2009-03-01 01:13:55 +00:00
d844dc305e
Added another darwin subtarget
...
llvm-svn: 65662
2009-02-28 00:25:30 +00:00
000421eade
Refactor TLS code and add some tests. The tests and expected results are:
...
pic | declaration | linkage | visibility |
!pic | declaration | external | default | tls1.ll tls2.ll | local exec
pic | declaration | external | default | tls1-pic.ll tls2-pic.ll | general dynamic
!pic | !declaration | external | default | tls3.ll tls4.ll | initial exec
pic | !declaration | external | default | tls3-pic.ll tls4-pic.ll | general dynamic
!pic | declaration | external | hidden | tls7.ll tls8.ll | local exec
pic | declaration | external | hidden | X | local dynamic
!pic | !declaration | external | hidden | tls9.ll tls10.ll | local exec
pic | !declaration | external | hidden | X | local dynamic
!pic | declaration | internal | default | tls5.ll tls6.ll | local exec
pic | declaration | internal | default | X | local dynamic
The ones marked with an X have not been implemented since local dynamic is not implemented.
llvm-svn: 65632
2009-02-27 13:37:18 +00:00
4609dbe222
Alignment values for i64 and f64 on ppc64 were wrong,
...
possibly for the reason suggested by the comment.
No wonder it didn't work very well. This unblocks
bootstrap with assertions on ppc.
llvm-svn: 65601
2009-02-27 00:56:35 +00:00
40abb7b5d0
ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified.
...
llvm-svn: 65499
2009-02-26 03:12:02 +00:00
a49de9de2e
Revert BuildVectorSDNode related patches: 65426, 65427, and 65296.
...
llvm-svn: 65482
2009-02-25 22:49:59 +00:00
5c10a3aa7f
Add a totally synthetic situation I came up with while looking at a bug in
...
related code.
llvm-svn: 65437
2009-02-25 06:52:48 +00:00
bb878288cb
Remove all "cached" data from BuildVectorSDNode, preferring to retrieve
...
results via reference parameters.
This patch also appears to fix Evan's reported problem supplied as a
reduced bugpoint test case.
llvm-svn: 65426
2009-02-25 03:12:50 +00:00
c5437ea429
Overhaul my earlier submission due to feedback. It's a large patch, but most of
...
them are generic changes.
- Use the "fast" flag that's already being passed into the asm printers instead
of shoving it into the DwarfWriter.
- Instead of calling "MI->getParent()->getParent()" for every MI, set the
machine function when calling "runOnMachineFunction" in the asm printers.
llvm-svn: 65379
2009-02-24 08:30:20 +00:00
318d7376ba
Fast-isel can't do TLS yet, so it should fall back to SDISel
...
if it sees TLS addresses.
llvm-svn: 65341
2009-02-23 22:03:08 +00:00
9f8fddeed8
Only v1i16 (i.e. _m64) is returned via RAX / RDX.
...
llvm-svn: 65313
2009-02-23 09:03:22 +00:00
e684da3e5d
Generate better code for v8i16 shuffles on SSE2
...
Generate better code for v16i8 shuffles on SSE2 (avoids stack)
Generate pshufb for v8i16 and v16i8 shuffles on SSSE3 where it is fewer uops.
Document the shuffle matching logic and add some FIXMEs for later further
cleanups.
New tests that test the above.
Examples:
New:
_shuf2:
pextrw $7, %xmm0, %eax
punpcklqdq %xmm1, %xmm0
pshuflw $128, %xmm0, %xmm0
pinsrw $2, %eax, %xmm0
Old:
_shuf2:
pextrw $2, %xmm0, %eax
pextrw $7, %xmm0, %ecx
pinsrw $2, %ecx, %xmm0
pinsrw $3, %eax, %xmm0
movd %xmm1, %eax
pinsrw $4, %eax, %xmm0
ret
=========
New:
_shuf4:
punpcklqdq %xmm1, %xmm0
pshufb LCPI1_0, %xmm0
Old:
_shuf4:
pextrw $3, %xmm0, %eax
movsd %xmm1, %xmm0
pextrw $3, %xmm1, %ecx
pinsrw $4, %ecx, %xmm0
pinsrw $5, %eax, %xmm0
========
New:
_shuf1:
pushl %ebx
pushl %edi
pushl %esi
pextrw $1, %xmm0, %eax
rolw $8, %ax
movd %xmm0, %ecx
rolw $8, %cx
pextrw $5, %xmm0, %edx
pextrw $4, %xmm0, %esi
pextrw $3, %xmm0, %edi
pextrw $2, %xmm0, %ebx
movaps %xmm0, %xmm1
pinsrw $0, %ecx, %xmm1
pinsrw $1, %eax, %xmm1
rolw $8, %bx
pinsrw $2, %ebx, %xmm1
rolw $8, %di
pinsrw $3, %edi, %xmm1
rolw $8, %si
pinsrw $4, %esi, %xmm1
rolw $8, %dx
pinsrw $5, %edx, %xmm1
pextrw $7, %xmm0, %eax
rolw $8, %ax
movaps %xmm1, %xmm0
pinsrw $7, %eax, %xmm0
popl %esi
popl %edi
popl %ebx
ret
Old:
_shuf1:
subl $252, %esp
movaps %xmm0, (%esp)
movaps %xmm0, 16(%esp)
movaps %xmm0, 32(%esp)
movaps %xmm0, 48(%esp)
movaps %xmm0, 64(%esp)
movaps %xmm0, 80(%esp)
movaps %xmm0, 96(%esp)
movaps %xmm0, 224(%esp)
movaps %xmm0, 208(%esp)
movaps %xmm0, 192(%esp)
movaps %xmm0, 176(%esp)
movaps %xmm0, 160(%esp)
movaps %xmm0, 144(%esp)
movaps %xmm0, 128(%esp)
movaps %xmm0, 112(%esp)
movzbl 14(%esp), %eax
movd %eax, %xmm1
movzbl 22(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm1, %xmm2
movzbl 42(%esp), %eax
movd %eax, %xmm1
movzbl 50(%esp), %eax
movd %eax, %xmm3
punpcklbw %xmm1, %xmm3
punpcklbw %xmm2, %xmm3
movzbl 77(%esp), %eax
movd %eax, %xmm1
movzbl 84(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm1, %xmm2
movzbl 104(%esp), %eax
movd %eax, %xmm1
punpcklbw %xmm1, %xmm0
punpcklbw %xmm2, %xmm0
movaps %xmm0, %xmm1
punpcklbw %xmm3, %xmm1
movzbl 127(%esp), %eax
movd %eax, %xmm0
movzbl 135(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm0, %xmm2
movzbl 155(%esp), %eax
movd %eax, %xmm0
movzbl 163(%esp), %eax
movd %eax, %xmm3
punpcklbw %xmm0, %xmm3
punpcklbw %xmm2, %xmm3
movzbl 188(%esp), %eax
movd %eax, %xmm0
movzbl 197(%esp), %eax
movd %eax, %xmm2
punpcklbw %xmm0, %xmm2
movzbl 217(%esp), %eax
movd %eax, %xmm4
movzbl 225(%esp), %eax
movd %eax, %xmm0
punpcklbw %xmm4, %xmm0
punpcklbw %xmm2, %xmm0
punpcklbw %xmm3, %xmm0
punpcklbw %xmm1, %xmm0
addl $252, %esp
ret
llvm-svn: 65311
2009-02-23 08:49:38 +00:00
9ee052bcdc
Propagate debug loc info through prologue/epilogue.
...
llvm-svn: 65298
2009-02-23 00:42:30 +00:00
9d31aca679
Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR
...
instruction. The class also consolidates the code for detecting constant
splats that's shared across PowerPC and the CellSPU backends (and might be
useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for
generating new BUILD_VECTOR nodes.
llvm-svn: 65296
2009-02-22 23:36:09 +00:00
2448aa1d8d
Add a note.
...
llvm-svn: 65275
2009-02-22 08:13:45 +00:00
e4ffc030e2
Be bug compatible with gcc by returning MMX values in RAX.
...
llvm-svn: 65274
2009-02-22 08:05:12 +00:00
91193c0094
Do not consider MMX_MOVD64rr a move instructions. The source register is in GR32, the destination is VR64. They are not compatible.
...
llvm-svn: 65273
2009-02-22 08:04:23 +00:00
42aae86590
Drop bunch of half-working stuff in the ext_weak linkage support.
...
Now we're using one gross, but quite robust hack :) (previous ones
did not work, for example, when ext_weak symbol was used deep inside
constant expression in the initializer).
The proper fix of this problem will require some quite huge asmprinter
changes and that's why was postponed. This fixes PR3629 by the way :)
llvm-svn: 65230
2009-02-21 11:53:32 +00:00
82aa14fae8
Make sure this doesn't access .end() too.
...
llvm-svn: 65213
2009-02-21 01:11:36 +00:00
81ebf9a578
Make sure we don't dereference the .end() of the container.
...
llvm-svn: 65211
2009-02-21 01:07:26 +00:00
56759ee658
Propagate more debug loc infos. This also includes some code cleaning.
...
llvm-svn: 65207
2009-02-21 00:43:56 +00:00
5191934371
We need to propagate the debug location information even when dealing with the
...
prologue/epilogue.
llvm-svn: 65206
2009-02-21 00:32:08 +00:00
2a9bad5ac1
Support return of MMX values in 64-bit mode.
...
llvm-svn: 65152
2009-02-20 20:43:02 +00:00
87d5ca083b
add note about sin
...
llvm-svn: 65137
2009-02-20 18:42:06 +00:00
0f4c581c4a
Put code that generates debug labels into TableGen so that it can be used by
...
everyone.
llvm-svn: 64978
2009-02-18 23:12:06 +00:00
8cab4c44bb
Add explicit keywords.
...
llvm-svn: 64915
2009-02-18 16:37:45 +00:00
18d85e7403
Add support to the JIT for true non-lazy operation. When a call to a function
...
that has not been JIT'd yet, the callee is put on a list of pending functions
to JIT. The call is directed through a stub, which is updated with the address
of the function after it has been JIT'd. A new interface for allocating and
updating empty stubs is provided.
Add support for removing the ModuleProvider the JIT was created with, which
would otherwise invalidate the JIT's PassManager, which is initialized with the
ModuleProvider's Module.
Add support under a new ExecutionEngine flag for emitting the infomration
necessary to update Function and GlobalVariable stubs after JITing them, by
recording the address of the stub and the name of the GlobalValue. This allows
code to be copied from one address space to another, where libraries may live
at different virtual addresses, and have the stubs updated with their new
correct target addresses.
llvm-svn: 64906
2009-02-18 08:31:02 +00:00
2af1f85f1f
Factor out the code to add a MachineOperand to a MachineInstrBuilder.
...
llvm-svn: 64891
2009-02-18 05:45:50 +00:00
a40d5e14ab
GV with null value initializer shouldn't go to BSS if it's meant for a mergeable strings section. Currently it only checks for Darwin. Someone else please check if it should apply to other targets as well.
...
llvm-svn: 64877
2009-02-18 02:19:52 +00:00
cf0da6c597
Remove trailing whitespace to reduce later commit patch noise.
...
(Note: Eventually, commits like this will be handled via a pre-commit hook that
does this automagically, as well as expand tabs to spaces and look for 80-col
violations.)
llvm-svn: 64827
2009-02-17 22:15:04 +00:00
cba4b6f83d
add a horrible note
...
llvm-svn: 64719
2009-02-17 01:16:14 +00:00
3c50922ea0
--- Merging (from foreign repository) r64714 into '.':
...
U include/llvm/CodeGen/DebugLoc.h
U lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
Enable debug location generation at -Os. This goes with the reapplication of the
r63639 patch.
llvm-svn: 64715
2009-02-17 01:04:54 +00:00
2a4553ba5f
Delete trailing whitespace.
...
llvm-svn: 64694
2009-02-16 23:14:14 +00:00
f6ccacba36
MachineLICM now handles these cases.
...
llvm-svn: 64620
2009-02-15 23:24:52 +00:00
29705333e5
The x86-64 red zone is now being used.
...
llvm-svn: 64535
2009-02-14 03:30:05 +00:00
c2fde91703
Teach x86 target -soft-float.
...
llvm-svn: 64496
2009-02-13 22:36:38 +00:00
3a8bd17fdb
Remove non-DebugLoc versions of BuildMI from IA64, Mips.
...
llvm-svn: 64438
2009-02-13 02:34:39 +00:00
9bba902c83
Remove non-DebugLoc versions of BuildMI from X86.
...
There were some that might even matter in X86FastISel.
llvm-svn: 64437
2009-02-13 02:33:27 +00:00
57097d2a26
missed file
...
llvm-svn: 64436
2009-02-13 02:32:04 +00:00
215a925766
Remove non-DebugLoc versions of buildMI from Sparc.
...
llvm-svn: 64435
2009-02-13 02:31:35 +00:00
635f2a69d9
Remove non-DebugLoc versions of BuildMI from Alpha and Cell.
...
llvm-svn: 64433
2009-02-13 02:30:42 +00:00
460bfeba8c
Remove refs to non-DebugLoc version of BuildMI from XCore, PIC16.
...
llvm-svn: 64432
2009-02-13 02:29:03 +00:00
e9f623e27c
Remove refs to non-DebugLoc version of BuildMI from PowerPC.
...
llvm-svn: 64431
2009-02-13 02:27:39 +00:00
b851a7853a
and one more file
...
llvm-svn: 64430
2009-02-13 02:26:21 +00:00
7647da67ea
Remove refs to non-DebugLoc versions of BuildMI from ARM.
...
llvm-svn: 64429
2009-02-13 02:25:56 +00:00
65c0fd4c44
Revert this. It was breaking stuff.
...
llvm-svn: 64428
2009-02-13 02:16:35 +00:00
1c21ac3066
Turn off the old way of handling debug information in the code generator. Use
...
the new way, where all of the information is passed on SDNodes and machine
instructions.
llvm-svn: 64427
2009-02-13 02:01:04 +00:00
baca6ed65e
Check in missing file.
...
llvm-svn: 64410
2009-02-12 23:24:44 +00:00
6b8c76a910
Eliminate a couple of non-DebugLoc BuildMI variants.
...
Modify callers.
llvm-svn: 64409
2009-02-12 23:08:38 +00:00
655775293f
Arrange to print constants that match "n" and "i" constraints
...
in inline asm as signed (what gcc does). Add partial support
for x86-specific "e" and "Z" constraints, with appropriate
signedness for printing.
llvm-svn: 64400
2009-02-12 20:58:09 +00:00
844deb73f4
fix PR3538 for ARM.
...
llvm-svn: 64384
2009-02-12 17:38:23 +00:00
4d4c702d5f
fix PR3538 for PPC
...
llvm-svn: 64383
2009-02-12 17:37:15 +00:00
aed3a4215b
fix the X86 backend to just drop llvm.declare nodes for VLAs instead of
...
leaving them in the DAG and then getting selection errors. This is a
fix for PR3538.
llvm-svn: 64382
2009-02-12 17:33:11 +00:00
f6d609a227
Move debug loc info along when the spiller creates new instructions.
...
llvm-svn: 64342
2009-02-12 00:02:55 +00:00
27b508db9b
Propagate DebugLoc info for spiller call-backs.
...
llvm-svn: 64329
2009-02-11 21:51:19 +00:00
27f85854f9
Don't try to set an EFLAGS operand to dead if no instruction was created.
...
This fixes a bug introduced by r61215.
llvm-svn: 64316
2009-02-11 19:50:24 +00:00
589a539423
Handle llvm.x86.sse2.maskmov.dqu in 64-bit.
...
llvm-svn: 64240
2009-02-10 22:06:28 +00:00
df15f13c34
80 col violations.
...
llvm-svn: 64237
2009-02-10 21:39:44 +00:00
c3f7b82628
Function temporaries can not overlap with retval or args.See the comment in source code to know the reason. Anything having .auto. in its name is local to a function in nature irrespective of the linkage specified. print static local variables in module level IDATA section.
...
llvm-svn: 64199
2009-02-10 04:20:26 +00:00
e5ade4a9a1
Implement FpSET_ST1_*.
...
llvm-svn: 64186
2009-02-09 23:32:07 +00:00
a950e99dee
Use doxygen comment syntax.
...
llvm-svn: 64150
2009-02-09 18:12:09 +00:00
64dfcacd5f
Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
...
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.
llvm-svn: 64124
2009-02-09 07:14:22 +00:00
1aca40e349
add a note.
...
llvm-svn: 64093
2009-02-08 20:44:19 +00:00
9c310711bb
Use getDebugLoc forwarder instead of getNode()->getDebugLoc.
...
No functional change.
llvm-svn: 64026
2009-02-07 19:59:05 +00:00
747e55bc9a
Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing
...
ScheduleDAG's TLI member to use const.
llvm-svn: 64018
2009-02-07 16:15:20 +00:00
4ea526268c
Needs this file too.
...
llvm-svn: 63993
2009-02-07 00:56:46 +00:00
62fd95d6ec
Get rid of the last non-DebugLoc versions of getNode!
...
Many targets build placeholder nodes for special operands, e.g.
GlobalBaseReg on X86 and PPC for the PIC base. There's no
sensible way to associate debug info with these. I've left
them built with getNode calls with explicit DebugLoc::getUnknownLoc operands.
I'm not too happy about this but don't see a good improvement;
I considered adding a getPseudoOperand or something, but it
seems to me that'll just make it harder to read.
llvm-svn: 63992
2009-02-07 00:55:49 +00:00
4e3e3deed3
Refactor some repeated logic into a separate function.
...
llvm-svn: 63989
2009-02-07 00:43:41 +00:00
78fe44ed52
Make a comment a doxygen comment.
...
llvm-svn: 63988
2009-02-07 00:42:54 +00:00
84935759d5
Remove more non-DebugLoc getNode variants. Use
...
getCALLSEQ_{END,START} to permit passing no DebugLoc
there. UNDEF doesn't logically have DebugLoc; add
getUNDEF to encapsulate this.
llvm-svn: 63978
2009-02-06 23:05:02 +00:00
400dc2e2e4
Remove more non-DebugLoc versions of getNode.
...
llvm-svn: 63969
2009-02-06 21:50:26 +00:00
b6b0aa2449
Record debug location information in the Dwarf writer.
...
A simple test program shows that debugging works. :-)
llvm-svn: 63968
2009-02-06 21:45:08 +00:00
af8f994681
Use .size and .type on ELF systems; this helps tools that map
...
addresses to symbols.
llvm-svn: 63962
2009-02-06 21:15:52 +00:00
ab8e4425a3
Eliminate remaining non-DebugLoc version of getTargetNode.
...
llvm-svn: 63951
2009-02-06 19:16:40 +00:00
48d6bb9924
Print globl directive for variables with external linkage (global variables).
...
llvm-svn: 63943
2009-02-06 18:24:59 +00:00
066757eea1
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
...
llvm-svn: 63938
2009-02-06 17:43:24 +00:00
b5f0ec3eb7
Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook.
...
llvm-svn: 63936
2009-02-06 17:17:30 +00:00
2c4cf2752d
get rid of some non-DebugLoc getTargetNode variants.
...
llvm-svn: 63909
2009-02-06 02:08:06 +00:00
9f3f72f144
Get rid of one more non-DebugLoc getNode and
...
its corresponding getTargetNode. Lots of
caller changes.
llvm-svn: 63904
2009-02-06 01:31:28 +00:00
f80493bbfd
Remove a non-DebugLoc version of getNode.
...
llvm-svn: 63889
2009-02-05 22:07:54 +00:00
64fdacc27f
A few more isAsCheapAsAMove.
...
llvm-svn: 63852
2009-02-05 08:42:55 +00:00
b842d529a3
Reapply 63765. Patches for clang and llvm-gcc to follow.
...
llvm-svn: 63812
2009-02-05 01:49:45 +00:00
12c572b6fa
Get rid of 3 non-DebugLoc getNode variants.
...
llvm-svn: 63808
2009-02-05 01:01:16 +00:00
7ae8c8b108
Remove non-DebugLoc versions of getMergeValues, ZeroExtendInReg.
...
llvm-svn: 63800
2009-02-05 00:20:09 +00:00
f08a47bb70
Remove non-DebugLoc forms of CopyToReg and CopyFromReg.
...
Adjust callers.
llvm-svn: 63789
2009-02-04 23:02:30 +00:00
ae616c2c61
Reverting 63765. This broke the build of both clang
...
and llvm-gcc.
llvm-svn: 63786
2009-02-04 22:47:25 +00:00
021052a705
Remove non-DebugLoc versions of getLoad and getStore.
...
Adjust the many callers of those versions.
llvm-svn: 63767
2009-02-04 20:06:27 +00:00
6ae3aa83d0
New feature: add support for target intrinsics being defined in the
...
target directories themselves. This also means that VMCore no longer
needs to know about every target's list of intrinsics. Future work
will include converting the PowerPC target to this interface as an
example implementation.
llvm-svn: 63765
2009-02-04 19:47:21 +00:00
e84a7911c4
Bill implemented this.
...
llvm-svn: 63752
2009-02-04 19:09:07 +00:00
553fd7e1eb
add a note, this is why we're faster at SciMark-MonteCarlo with
...
SSE disabled.
llvm-svn: 63751
2009-02-04 19:08:01 +00:00
556d14d483
Minor code cleanups; no functionality change.
...
llvm-svn: 63740
2009-02-04 17:28:58 +00:00
679073b420
Remove non-DebugLoc forms of the exotic forms
...
of Lod and Sto; patch uses.
llvm-svn: 63716
2009-02-04 02:34:38 +00:00
f2bb6f09a3
Remove some more non-DebugLoc versions of construction
...
functions, with callers adjusted to fit.
llvm-svn: 63705
2009-02-04 01:48:28 +00:00
85263882aa
Remove a few non-DebugLoc versions of node creation
...
functions.
llvm-svn: 63703
2009-02-04 01:17:06 +00:00
4379a795fe
Fixes a case where we generate an incorrect mask for pshfhw in the presence
...
of undefs and incorrectly determining if we have punpckldq.
llvm-svn: 63702
2009-02-04 01:16:59 +00:00
bbf13f54e0
Patch up omissions in DebugLoc propagation.
...
llvm-svn: 63693
2009-02-04 00:33:20 +00:00
0404dc11af
Need this file too.
...
llvm-svn: 63674
2009-02-03 22:26:34 +00:00
abf66b8343
Add some DL propagation to places that didn't
...
have it yet. More coming.
llvm-svn: 63673
2009-02-03 22:26:09 +00:00
14f2d9dcbd
DebugLoc propgation
...
llvm-svn: 63664
2009-02-03 21:48:12 +00:00
1eb1ef2cfd
DebugLoc propagation. done with file.
...
llvm-svn: 63656
2009-02-03 20:21:25 +00:00
66e03e6f7b
DebugLoc propagation. 2/3 through file.
...
llvm-svn: 63650
2009-02-03 19:33:06 +00:00
561d1226b6
Tevert part of the x86 subtarget logic changes: when -march=x86-64
...
is given, override the subtarget settings and enable 64-bit support.
This restores the earlier behavior, and fixes regressions on
Non-64-bit-capable x86-32 hosts.
This isn't necessarily the best approach, but the most obvious
alternative is to require -mcpu=x86-64 or -mattr=+64bit to be used
with -march=x86-64 when the host doesn't have 64-bit support. This
makes things little more consistent, but it's less convenient, and
it has the practical drawback of requiring lots of test changes, so
I opted for the above approach for now.
llvm-svn: 63642
2009-02-03 18:53:21 +00:00
e3c78361d3
Create DebugLoc information in FastISel. Several temporary methods were
...
created. Specifically, those BuildMIs which use
"DebugLoc::getUnknownLoc()". I'll remove them soon.
llvm-svn: 63584
2009-02-03 00:55:04 +00:00
7403751e16
Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has
...
SSE2, however it's possible to disable SSE2, and the subtarget support
code thinks that if 64-bit implies SSE2 and SSE2 is disabled then
64-bit should also be disabled. Instead, just mark all the 64-bit
subtargets as explicitly supporting SSE2.
Also, move the code that makes -march=x86-64 enable 64-bit support by
default to only apply when there is no explicit subtarget. If you
need to specify a subtarget and you want 64-bit code, you'll need to
select a subtarget that supports 64-bit code.
llvm-svn: 63575
2009-02-03 00:04:43 +00:00
e83866065b
Only force SSE level if it is not correct.
...
Add an assert to check HasX86_64 status.
llvm-svn: 63552
2009-02-02 21:57:34 +00:00
5dbd26ae0f
remove #if 0 code on Bill's request.
...
llvm-svn: 63542
2009-02-02 20:23:02 +00:00
50aeb12d80
Made the common case of default address space directive as non-virtual for performance reasons. Provide a single virtual interface for directives of all sizes in non-default address spaces.
...
llvm-svn: 63521
2009-02-02 16:53:06 +00:00
dc636c4080
ADD / SUB / SMUL / UMUL with overflow second result top bits must be zero.
...
llvm-svn: 63509
2009-02-02 09:15:04 +00:00
4988c597b3
Add comment.
...
llvm-svn: 63506
2009-02-02 08:19:07 +00:00
50e15bdf81
Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the condition. It's normally transformed by the dag combiner, unless the condition is set by a arithmetic op with overflow.
...
llvm-svn: 63505
2009-02-02 08:07:36 +00:00
a2d1f35e9a
Implement -mno-sse: if SSE is disabled on x86-64, don't store XMM on stack for
...
var-args, and don't allow FP return values
llvm-svn: 63495
2009-02-01 18:15:56 +00:00
3ed768868d
Fix PR3453 and probably a bunch of other potential
...
crashes or wrong code with codegen of large integers:
eliminate the legacy getIntegerVTBitMask and
getIntegerVTSignBit methods, which returned their
value as a uint64_t, so couldn't handle huge types.
llvm-svn: 63494
2009-02-01 18:06:53 +00:00
555a375bb6
Make LowerCallTo and LowerArguments take a DebugLoc
...
argument. Adjust all callers and overloaded versions.
llvm-svn: 63444
2009-01-30 23:10:59 +00:00
8fb81f1b3d
Get rid of the non-DebugLoc-ified getNOT() method.
...
llvm-svn: 63442
2009-01-30 23:03:19 +00:00
c10d810303
Fixed the comment. No functionality change.
...
llvm-svn: 63387
2009-01-30 09:01:44 +00:00
082174cb78
Use sublw for comparison with literals instead of subwf.
...
llvm-svn: 63382
2009-01-30 07:55:25 +00:00
cbb20a6ee1
When PerformBuildVectorCombine, avoid creating a X86ISD::VZEXT_LOAD of
...
an illegal type.
llvm-svn: 63380
2009-01-30 07:07:40 +00:00
964a29f671
Enable emitting of constant values in non-default address space as well. The APIs emitting constants now take an additional parameter signifying the address space in which to emit. The APIs like getData8BitsDirective() etc are made virtual enabling targets to be able to define appropirate directivers for various sizes and address spaces.
...
llvm-svn: 63377
2009-01-30 04:25:10 +00:00
e58ab79f33
Make x86's BT instruction matching more thorough, and add some
...
dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.
llvm-svn: 63266
2009-01-29 01:59:02 +00:00
9150f735fa
Fixed lowering of v816 shuffles.
...
llvm-svn: 63252
2009-01-28 23:11:14 +00:00
5a913d61e3
Rename getAnalysisToUpdate to getAnalysisIfAvailable.
...
llvm-svn: 63198
2009-01-28 13:14:17 +00:00
f31f288863
The memory alignment requirement on some of the mov{h|l}p{d|s} patterns are 16-byte. That is overly strict. These instructions read / write f64 memory locations without alignment requirement.
...
llvm-svn: 63195
2009-01-28 08:35:02 +00:00
5a685a52c1
Add shuffle splat pattern for x86 sse shifts.
...
llvm-svn: 63193
2009-01-28 08:12:05 +00:00
e4510972a6
Suppress a compile time warning.
...
llvm-svn: 63161
2009-01-28 00:53:34 +00:00
70d4c08cfe
Treat [1 x i8] zeroinitializer as a C string, placing such stuff into
...
mergeable string section. I don't see any bad impact of such decision
(rather then placing it into mergeable const section, as it was before),
but at least Darwin linker won't complain anymore.
The problem in LLVM is that we don't have special type for string constants
(like gcc does). Even more, we have two separate types: ConstatArray for non-null
strings and ConstantAggregateZero for null stuff.... It's a bit weird :)
llvm-svn: 63142
2009-01-27 22:29:24 +00:00
0ca1e7c6b6
Reformat the allocation-order arrays to a more conventional style.
...
llvm-svn: 63121
2009-01-27 19:25:38 +00:00
13f18e853f
Respect the DisableRedZone flag on PowerPC.
...
llvm-svn: 63119
2009-01-27 19:19:28 +00:00
f77f0ce21a
Simplify findNonImmUse; return the result using the return value
...
instead of via a by-reference argument. No functionality change.
llvm-svn: 63118
2009-01-27 19:04:30 +00:00
1bc8af207e
Implement multiple with overflow by 2 with an add instruction.
...
llvm-svn: 63090
2009-01-27 03:30:42 +00:00
7740523a89
Eliminate unnecessary operands-list traversals.
...
llvm-svn: 63088
2009-01-27 02:37:43 +00:00
75cee3a93c
Enable the red zone on x86-64 by default.
...
llvm-svn: 63078
2009-01-27 00:58:47 +00:00
1cd2a2c9f8
Fix the Red Zone calculation for functions with frame pointers.
...
Don't use the Red Zone when dynamic stack realignment is needed.
This could be implemented, but most x86-64 ABIs don't require
dynamic stack realignment so it isn't urgent.
llvm-svn: 63074
2009-01-27 00:40:06 +00:00
49483188c3
CellSPU:
...
- Update DWARF debugging support.
llvm-svn: 63059
2009-01-26 22:33:37 +00:00
3789a13c30
Make the Dwarf macro information section optional; CellSPU's assembler
...
doesn't support it. The default is set to 'true', so this should not
impact any other target backends.
llvm-svn: 63058
2009-01-26 22:32:51 +00:00
b6d36e1d14
Implement Red Zone utilization on x86-64. This is currently
...
disabled by default; I'll enable it when I hook it up with
the llvm-gcc flag which controls it.
llvm-svn: 63056
2009-01-26 22:22:31 +00:00
6c7e85142b
Enhance logic in X86DAGToDAGISel::PreprocessForRMW which move load inside callseq_start to allow it to be folded into a call. It was not considering the cases where a token factor is between the load and the callseq_start.
...
llvm-svn: 63022
2009-01-26 18:43:34 +00:00
8e4ac9b71a
Take the next steps in making SDUse more consistent with LLVM Use, and
...
tidy up SDUse and related code.
- Replace the operator= member functions with a set method, like
LLVM Use has, and variants setInitial and setNode, which take
care up updating use lists, like LLVM Use's does. This simplifies
code that calls these functions.
- getSDValue() is renamed to get(), as in LLVM Use, though most
places can either use the implicit conversion to SDValue or the
convenience functions instead.
- Fix some more node vs. value terminology issues.
Also, eliminate the one remaining use of SDOperandPtr, and
SDOperandPtr itself.
llvm-svn: 62995
2009-01-26 04:35:06 +00:00
95b2a206ee
Untabify code.
...
llvm-svn: 62991
2009-01-26 03:37:41 +00:00
9e3e4a9219
CellSPU:
...
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll
- Fix select_bits.ll test
- Capitulate to the DAGCombiner and move i64 constant loads to instruction
selection (SPUISelDAGtoDAG.cpp).
<rant>DAGCombiner will insert all kinds of 64-bit optimizations after
operation legalization occurs and now we have to do most of the work that
instruction selection should be doing twice (once to determine if v2i64
build_vector can be handled by SelectCode(), which then runs all of the
predicates a second time to select the necessary instructions.) But,
CellSPU is a good citizen.</rant>
llvm-svn: 62990
2009-01-26 03:31:40 +00:00
624801e87e
Fix a typo
...
llvm-svn: 62989
2009-01-26 03:15:54 +00:00
a2550a8e96
De-identifying per sabre review
...
llvm-svn: 62988
2009-01-26 03:15:31 +00:00
5eca265519
Map address space 256 to gs; similar mappings could be supported for the
...
other x86 segments. address space 0 is stack/default, 1-255 are reserved for
client use.
llvm-svn: 62980
2009-01-26 01:24:32 +00:00
8a51d8c8f7
Support pattern matching various x86 sse shifts.
...
llvm-svn: 62979
2009-01-26 00:52:55 +00:00
80b283c1cd
silence a warning when assertions are disabled.
...
llvm-svn: 62976
2009-01-25 23:08:00 +00:00
692ed0f67d
should have removed the + when manually applying a patch!
...
llvm-svn: 62973
2009-01-25 20:29:34 +00:00
97be2f5840
revert this patch for now, because Codegen does still want to generate SSE code,
...
for example in the case of va-args. XFAIL associated tests.
llvm-svn: 62972
2009-01-25 20:21:24 +00:00
a23c73bbdc
If user explicitly asks not to use SSE, don't force it. This fixes LLVM part of PR3402.
...
llvm-svn: 62967
2009-01-25 17:58:56 +00:00
1c7c019229
Private linkage support for PPC / Darwin.
...
llvm-svn: 62955
2009-01-25 06:32:01 +00:00
b09b0242ca
Fix an indent and a typo.
...
llvm-svn: 62940
2009-01-24 22:12:48 +00:00
3cedd4dc64
add note about possible GEP improvement with fields of size 0.
...
llvm-svn: 62925
2009-01-24 19:30:25 +00:00
832959536a
hopefully address PR3379 by making the P modifier work in x86 inline asm.
...
llvm-svn: 62887
2009-01-23 22:33:40 +00:00
c58900504b
Add SelectionDAG::getNOT method to construct bitwise NOT operations,
...
corresponding to the "not" and "vnot" PatFrags. Use the new method
in some places where it seems appropriate.
llvm-svn: 62768
2009-01-22 17:39:32 +00:00
4a0bf66eb8
Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.
...
llvm-svn: 62762
2009-01-22 09:10:11 +00:00
705ac7082b
add a note
...
llvm-svn: 62760
2009-01-22 07:16:03 +00:00
31dd016f81
Recognize inline asm for bswap on x86-64 GLIBC. This allows it
...
to be supported in the JIT.
llvm-svn: 62730
2009-01-21 23:40:54 +00:00
ec5eb161fd
Also favors NOT64r.
...
llvm-svn: 62710
2009-01-21 19:45:31 +00:00
a326520190
fix warning in release-asserts mode and spelling of assert.
...
llvm-svn: 62699
2009-01-21 18:38:18 +00:00
b43c8996f2
Fix a recent regression. ClrOpcode is not set for i8; for i8, if
...
we want to clear %ah to zero before a division, just use a
zero-extending mov to %al. This fixes PR3366.
llvm-svn: 62691
2009-01-21 14:50:16 +00:00
335ea6cf2a
Fixed build warnings. Restoring changes done in 62600, they were lost in 62655.
...
llvm-svn: 62681
2009-01-21 09:02:46 +00:00
be7e41481b
Cleanup whitespace and comments, and tweak some
...
prototypes, in operand type legalization. No
functionality change.
llvm-svn: 62680
2009-01-21 09:00:29 +00:00
f737337707
Implement LowerOperationWrapper for legalizer.
...
Also a few signed comparison fixes.
llvm-svn: 62665
2009-01-21 05:44:05 +00:00
ed7d79fce4
CellSPU:
...
- Ensure that (operation) legalization emits proper FDIV libcall when needed.
- Fix various bugs encountered during llvm-spu-gcc build, along with various
cleanups.
- Start supporting double precision comparisons for remaining libgcc2 build.
Discovered interesting DAGCombiner feature, which is currently solved via
custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner
insists on inserting one anyway.)
- Update README.
llvm-svn: 62664
2009-01-21 04:58:48 +00:00
201501995f
Favors generating "not" over "xor -1". For example.
...
unsigned test(unsigned a) {
return ~a;
}
llvm used to generate:
movl $4294967295, %eax
xorl 4(%esp), %eax
Now it generates:
movl 4(%esp), %eax
notl %eax
It's 3 bytes shorter.
llvm-svn: 62661
2009-01-21 02:09:05 +00:00
c544cb0eca
Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
...
llvm-svn: 62600
2009-01-20 19:12:24 +00:00
83d2e066c1
Add a README entry noticed while investigating PR3216.
...
llvm-svn: 62558
2009-01-20 01:07:33 +00:00
44cc554311
DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it.
...
llvm-svn: 62519
2009-01-19 19:06:11 +00:00
0346c04f39
Fix 80 col violations.
...
llvm-svn: 62518
2009-01-19 18:57:29 +00:00
6c02498215
Handle ISD::DECLARE with PIC relocation model.
...
llvm-svn: 62516
2009-01-19 18:31:51 +00:00
8f367e53c7
Minor tweak to LowerUINT_TO_FP_i32. Bias (after scalar_to_vector) has two uses so we should make it the second source operand of ISD::OR so 2-address pass won't have to be smart about commuting.
...
%reg1024<def> = MOVSDrm %reg0, 1, %reg0, <cp#0>, Mem:LD(8,8) [ConstantPool + 0]
%reg1025<def> = MOVSD2PDrr %reg1024
%reg1026<def> = MOVDI2PDIrm <fi#-1>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack-1 + 0]
%reg1027<def> = ORPSrr %reg1025<kill>, %reg1026<kill>
%reg1028<def> = MOVPD2SDrr %reg1027<kill>
%reg1029<def> = SUBSDrr %reg1028<kill>, %reg1024<kill>
%reg1030<def> = CVTSD2SSrr %reg1029<kill>
MOVSSmr <fi#0>, 1, %reg0, 0, %reg1030<kill>, Mem:ST(4,4) [FixedStack0 + 0]
%reg1031<def> = LD_Fp32m80 <fi#0>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack0 + 0]
RET %reg1031<kill>, %ST0<imp-use,kill>
The reason 2-addr pass isn't smart enough to commute the ORPSrr is because it can't look pass the MOVSD2PDrr instruction.
llvm-svn: 62505
2009-01-19 08:19:57 +00:00
7e9ef4d776
Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
...
optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself.
llvm-svn: 62504
2009-01-19 08:08:22 +00:00
f9291cf43c
Extend thi
...
llvm-svn: 62415
2009-01-17 07:40:19 +00:00
bf38a5e540
Fix MatchAddress bug that's preventing negative displacement from being folded in 64-bit mode.
...
llvm-svn: 62413
2009-01-17 07:09:27 +00:00
dd40f26877
Temporarily revert my last change. It is causing a bootstrap failure.
...
llvm-svn: 62405
2009-01-17 04:23:51 +00:00
4d5275905e
Implement a special algorithm for converting uint_to_fp for i32 values on
...
X86. This code:
void f() {
uint32_t x;
float y = (float)x;
}
used to be:
movl %eax, -8(%ebp)
movl [2^52 double], -4(%ebp)
movsd -8(%ebp), %xmm0
subsd [2^52 double], %xmm0
cvtsd2ss %xmm0, %xmm0
Is now:
movsd [2^52 double], %xmm0
movsd %xmm0, %xmm1
movd %ecx, %xmm2
orps %xmm2, %xmm1
subsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm0
This is faster on X86. Note that there's an extra load of %xmm0 into %xmm1. That
will be fixed in a later coalescer fix.
llvm-svn: 62404
2009-01-17 03:56:04 +00:00
90cc7050f2
CMake: Add lib/Target/IA64/IA64Subtarget.cpp
...
llvm-svn: 62394
2009-01-17 01:50:32 +00:00
41e9f6a854
Fix PPC ISD::Declare isel and eliminate the need for PPCTargetLowering::LowerGlobalAddress to check if isVerifiedDebugInfoDesc() is true. Given the recent changes, it would falsely return true for a lot of GlobalAddressSDNode's.
...
llvm-svn: 62373
2009-01-16 22:57:32 +00:00
703a6c7274
Give IA64 a TargetSubtarget subclass, so that it can
...
implement getSubtargetImpl.
llvm-svn: 62369
2009-01-16 22:49:36 +00:00
e04334730e
Add support for non-zero __builtin_return_address values on X86.
...
llvm-svn: 62338
2009-01-16 19:25:27 +00:00
d243c0e3d9
ARMCompilationCallback should not save / restore vfp registers if vfp is not available.
...
llvm-svn: 62299
2009-01-16 02:16:37 +00:00
ceac7c34f1
Initial hazard recognizer support in post-pass scheduling. This includes
...
a new toy hazard recognizier heuristic which attempts to direct the
scheduler to avoid clumping large groups of loads or stores too densely.
llvm-svn: 62291
2009-01-16 01:33:36 +00:00
7e105f0b12
Generalize the HazardRecognizer interface so that it can be used
...
to support MachineInstr-based scheduling in addition to
SDNode-based scheduling.
llvm-svn: 62284
2009-01-15 22:18:12 +00:00
f2831d6cd1
Fix Alpha test and support for private linkage.
...
llvm-svn: 62282
2009-01-15 21:51:46 +00:00
ebfafee903
Expand insert/extract of a <4 x i32> with a variable index.
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llvm-svn: 62281
2009-01-15 21:10:20 +00:00
6de96a1b5d
Add the private linkage.
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llvm-svn: 62279
2009-01-15 20:18:42 +00:00
Duncan Sands