Commit Graph

88872 Commits

Author SHA1 Message Date
Jim Grosbach 4d5dc3e7e5 cortex m4 has floating point support, but only single precision.
llvm-svn: 110810
2010-08-11 15:44:15 +00:00
Daniel Dunbar 468f5cb8ea Remove wpa 'example', it isn't being maintained.
llvm-svn: 110809
2010-08-11 15:21:41 +00:00
Dan Gohman f3d783a6d2 Temporarily disable some failing tests, until they can be
properly investigated.

llvm-svn: 110808
2010-08-11 15:09:00 +00:00
Benjamin Kramer e8394df11b Random temporary string cleanup.
llvm-svn: 110807
2010-08-11 14:47:12 +00:00
Douglas Gregor 13e6587313 If name lookup finds different type declarations in different scopes
that actually refer to the same underlying type, it is not an
ambiguity; add uniquing support based on the canonical type of type
declarations. Fixes <rdar://problem/8296180>.

llvm-svn: 110806
2010-08-11 14:45:53 +00:00
Howard Hinnant 08b0997cc1 Modified the definition of std::foward to address National Body Comment US 90
llvm-svn: 110805
2010-08-11 14:05:55 +00:00
Douglas Gregor 20975b25c3 Fix a thinko in the creation of temporary files for the precompiled preamble
llvm-svn: 110804
2010-08-11 13:06:56 +00:00
Douglas Gregor 1c28331b57 Speculatively revert r110610 " Make ObjCInterfaceDecl redeclarable,
and create separate decl nodes for forward declarations and the
definition," which appears to be causing significant Objective-C
breakage.

llvm-svn: 110803
2010-08-11 12:19:30 +00:00
Bill Wendling 6a98131468 Consider this code snippet:
float t1(int argc) {
  return (argc == 1123) ? 1.234f : 2.38213f;
}

We would generate truly awful code on ARM (those with a weak stomach should look
away):

_t1:
  movw   r1, #1123
  movs   r2, #1
  movs   r3, #0
  cmp    r0, r1
  mov.w  r0, #0
  it     eq
  moveq  r0, r2
  movs   r1, #4
  cmp    r0, #0
  it     ne
  movne  r3, r1
  adr    r0, #LCPI1_0
  ldr    r0, [r0, r3]
  bx     lr

The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".

I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.

Now we generate this, which looks optimal to me:

_t1:
  movw   r1, #1123
  movs   r2, #0
  cmp    r0, r1
  adr    r0, #LCPI0_0
  it     eq
  moveq  r2, #4
  ldr    r0, [r0, r2]
  bx     lr
  .align  2
LCPI0_0:
  .long   1075344593  @ float 2.382130e+00
  .long   1067316150  @ float 1.234000e+00

llvm-svn: 110799
2010-08-11 08:43:16 +00:00
Evan Cheng 5190f09291 Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.
llvm-svn: 110798
2010-08-11 07:17:46 +00:00
Evan Cheng 163b624b4e ArchV7M implies HW division instructions.
llvm-svn: 110797
2010-08-11 07:00:16 +00:00
Evan Cheng 1c3c0009bd ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON.
llvm-svn: 110796
2010-08-11 06:57:53 +00:00
Evan Cheng 40921a4e62 Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.)
llvm-svn: 110795
2010-08-11 06:51:54 +00:00
Daniel Dunbar 188b47b214 MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form.
llvm-svn: 110794
2010-08-11 06:37:20 +00:00
Daniel Dunbar 75d26be81a MC/ARM: Split mnemonic on '.' characters.
llvm-svn: 110793
2010-08-11 06:37:16 +00:00
Daniel Dunbar 4a863e6cf7 MC/ARM: Fill in ARMOperand::dump a bit.
llvm-svn: 110792
2010-08-11 06:37:12 +00:00
Daniel Dunbar 2eca0252c3 llvm-mc: Add -show-inst-operands, for dumping the parsed instruction representation before matching.
llvm-svn: 110791
2010-08-11 06:37:09 +00:00
Daniel Dunbar ebace2248f MCAsmParser: Add dump() hook to MCParsedAsmOperand.
llvm-svn: 110790
2010-08-11 06:37:04 +00:00
Daniel Dunbar 69f024b855 tblgen/AsmMatcher: Treat '.' in assembly strings as a token separator.
llvm-svn: 110789
2010-08-11 06:36:59 +00:00
Daniel Dunbar d8042b7bd7 MC/ARM: Add an ARMOperand class for condition codes.
llvm-svn: 110788
2010-08-11 06:36:53 +00:00
Evan Cheng 91033bed94 Really control isel of barrier instructions with cpu feature.
llvm-svn: 110787
2010-08-11 06:36:31 +00:00
Evan Cheng 49e02fc414 Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit
instructions: dmb, dsb, isb, msr, and mrs.

llvm-svn: 110786
2010-08-11 06:30:38 +00:00
Evan Cheng 6e809de90c - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.

llvm-svn: 110785
2010-08-11 06:22:01 +00:00
Zhongxing Xu 8de0a3d8c3 MemRegion can refer to ASTContext without external help.
llvm-svn: 110784
2010-08-11 06:10:55 +00:00
Daniel Dunbar 5cd4d0f9ac MC/ARM: Switch to using the generated match functions instead of stub implementations.
llvm-svn: 110783
2010-08-11 05:24:50 +00:00
Daniel Dunbar 56e77c409b MC/ARM: Enable generation of the ARM asm matcher, not that it can do much.
llvm-svn: 110782
2010-08-11 05:09:20 +00:00
Daniel Dunbar 07cc87438f ARM: Mark some disassembler only instructions as not available for matching --
for some reason they have a very odd MCInst form where the operands overlap, but
I haven't dug in to find out why yet.

llvm-svn: 110781
2010-08-11 04:46:13 +00:00
Daniel Dunbar 740c50385c ARM: Quote $p in an asm string.
llvm-svn: 110780
2010-08-11 04:46:10 +00:00
Daniel Dunbar 1326056108 tblgen/AsmMatcher: Downgrade instructions with tied operands to a debug-only warning, for now.
llvm-svn: 110779
2010-08-11 04:46:08 +00:00
Owen Anderson 0bd61240e9 Improve indentation.
llvm-svn: 110778
2010-08-11 04:24:25 +00:00
Sean Callanan 2235f32bbd Added support for persistent variables to the
expression parser.  It is now possible to type:

(lldb) expr int $i = 5; $i + 1
(int) 6
(lldb) expr $i + 2
(int) 7

The skeleton for automatic result variables is
also implemented.  The changes affect:

- the process, which now contains a 
  ClangPersistentVariables object that holds
  persistent variables associated with it
- the expression parser, which now uses
  the persistent variables during variable
  lookup
- TaggedASTType, where I loaded some commonly
  used tags into a header so that they are
  interchangeable between different clients of
  the class

llvm-svn: 110777
2010-08-11 03:57:18 +00:00
Daniel Dunbar 00012c869f tests: Add a missing -Xclang.
llvm-svn: 110776
2010-08-11 02:32:03 +00:00
Daniel Dunbar 9034aa36c7 ARM: Recognize single precision float register names.
- We don't recognize double or NEON register names yet -- we don't have the
   infrastructure to generate the right clobbers for them.

llvm-svn: 110775
2010-08-11 02:17:20 +00:00
Daniel Dunbar 256e1f3ad0 ARM: Swap which registers we consider real / aliases to match LLVM and llvm-gcc.
llvm-svn: 110774
2010-08-11 02:17:11 +00:00
Douglas Gregor 836a7e8468 Improve our handling of user-defined conversions when computing
implicit conversion sequences. In particular, model the "standard
conversion" from a class to its own type (or a base type) directly as
a standard conversion in the normal path *without* trying to determine
if there is a valid copy constructor. This appears to match the intent
of C++ [over.best.ics]p6 and more closely matches GCC and EDG.

As part of this, model non-lvalue reference initialization via
user-defined conversion in overloading the same way we handle it in
InitializationSequence, separating the "general user-defined
conversion" and "conversion to compatible class type" cases.

The churn in the overload-call-copycon.cpp test case is because the
test case was originally wrong; it assumed that we should do more
checking for copy constructors that we actually should, which affected
overload resolution.

Fixes PR7055. Bootstrapped okay.

llvm-svn: 110773
2010-08-11 02:15:33 +00:00
Bruno Cardoso Lopes 8c9c9c77c8 Remove AVX 256-bit cast intrinsics now that clang is using __builtin_shufflevector for those
llvm-svn: 110772
2010-08-11 02:15:33 +00:00
Bruno Cardoso Lopes 65954ffc69 Remove 256-bit cast built-ins and make the AVX intrinsic call llvm __builtin_shufflevector with the appropriate arguments
llvm-svn: 110771
2010-08-11 02:14:38 +00:00
John McCall ca7993f572 Make this test a little less dependent on exact optimizer results.
llvm-svn: 110770
2010-08-11 02:06:44 +00:00
Bruno Cardoso Lopes 4134f97e56 Remove AVX 256-bit unpack and interleave intrinsics now that clang is using __builtin_shufflevector for those
llvm-svn: 110769
2010-08-11 01:44:11 +00:00
Bruno Cardoso Lopes a4f1930b75 Remove 256-bit unpack built-ins and make the AVX intrinsic call llvm __builtin_shufflevector with the appropriate arguments
llvm-svn: 110768
2010-08-11 01:43:24 +00:00
Bruno Cardoso Lopes 90b238c68b Remove AVX 256-bit shuffle intrinsics now that clang is using __builtin_shufflevector for those
llvm-svn: 110767
2010-08-11 01:18:26 +00:00
Bruno Cardoso Lopes e712a135b7 Remove 256-bit shuffle built-ins and make the AVX intrinsic call llvm __builtin_shufflevector with the appropriate arguments
llvm-svn: 110766
2010-08-11 01:17:34 +00:00
Bill Wendling 79937dfc5b Update test to match output of optimize compares for ARM.
llvm-svn: 110765
2010-08-11 01:05:02 +00:00
John Thompson 46667afccd Fix for pr7869, inline asm mult-alt constraints.
llvm-svn: 110764
2010-08-11 00:58:20 +00:00
Oscar Fuentes 945f64ebac CMake: corrections on LLVM.cmake external services.
llvm-svn: 110763
2010-08-11 00:51:32 +00:00
Bill Wendling 79553bad50 Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds.
llvm-svn: 110762
2010-08-11 00:23:00 +00:00
Bill Wendling 920f74aaab Mark ARM compare instructions as isCompare.
llvm-svn: 110761
2010-08-11 00:22:27 +00:00
John McCall cebe0ca75e Fix a bug in @finally emission in both the fragile and non-fragile EH schemes
where we weren't accounting for the possibility that a @finally block might
have internal cleanups and therefore might write to the cleanup destination slot.

Fixes <rdar://problem/8293901>.

llvm-svn: 110760
2010-08-11 00:16:14 +00:00
Rafael Espindola ccab1dddd1 Make it possible to set the cpu used for codegen.
llvm-svn: 110759
2010-08-11 00:15:13 +00:00
Dan Gohman f7495f286a When analyzing loop exit conditions combined with and and or, don't
make any assumptions about when the two conditions will agree on when
to permit the loop to exit. This fixes PR7845.

llvm-svn: 110758
2010-08-11 00:12:36 +00:00