Commit Graph

345547 Commits

Author SHA1 Message Date
Mehdi Amini 4d506da91c Fix `warning: extra ‘;’` (NFC) 2020-03-18 14:22:10 +00:00
Mehdi Amini f3e297d90f Fix build with gcc 7.5 by adding a "redundant move"
The constructor of Expected<T> expects as T&&, but gcc-7.5 does not
infer an rvalue in this context apparently.
2020-03-18 14:22:10 +00:00
Roman Lebedev 85334b030a
[NFCI][SCEV] Avoid recursion in SCEVExpander::isHighCostExpansion*()
Summary:
As noted in [[ https://bugs.llvm.org/show_bug.cgi?id=45201 | PR45201 ]],
[[ https://bugs.llvm.org/show_bug.cgi?id=10090 | PR10090 ]] SCEV doesn't
always avoid recursive algorithms, and that causes issues with
large expression depths and/or smaller stack sizes.

In `SCEVExpander::isHighCostExpansion*()` case, the refactoring to avoid
recursion is rather idiomatic. We simply need to place the root expr
into a vector, and iterate over vector elements accounting for the cost
of each one, adding new exprs at the end of the vector,
thus achieving recursion-less traversal.

The order in which we will visit exprs doesn't matter here,
so we will be fine with the most basic approach of using SmallVector
and inserting/extracting from the back, which accidentally is the same
depth-first traversal that we were doing previously recursively.

Reviewers: mkazantsev, reames, wmi, ekatz

Reviewed By: mkazantsev

Subscribers: hiraditya, javed.absar, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76273
2020-03-18 17:10:54 +03:00
Oliver Stannard 73cea83a6f [IPRA][ARM] Spill extra registers at -Oz
When optimising for code size at the expense of performance, it is often
worth saving and restoring some of r0-r3, if IPRA will be able to take
advantage of them. This doesn't cost any extra code size if we already
have a PUSH/POP pair, and increases the number of available registers
across any calls to the function.

We already have an optimisation which tries fold the subtract/add of the
SP into the PUSH/POP by using extra registers, which somewhat conflicts
with this. I've made the new optimisation less aggressive in cases where
the existing one is likely to trigger, which gives better results than
either of these optimisations by themselves.

Differential revision: https://reviews.llvm.org/D69936
2020-03-18 13:51:16 +00:00
Guillaume Chatelet d000655a8c [Alignment][NFC] Deprecate getMaxAlignment
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: jholewinski, arsenm, dschuff, jyknight, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76348
2020-03-18 14:48:45 +01:00
Kang Zhang 96b70809d9 [NFC][PowerPC] Add a new MIR file to test if-converter pass 2020-03-18 13:39:49 +00:00
Danila Malyutin 2aaafaf500 [NFC] Add missing REQUIRES clause to a test 2020-03-18 16:35:10 +03:00
Michael Liao 4cf01ed75e [hip] Revise `GlobalDecl` constructors. NFC.
Summary:
- https://reviews.llvm.org/D68578 revises the `GlobalDecl` constructors
  to ensure all GPU kernels have `ReferenceKenelKind` initialized
  properly with an explicit constructor and static one. But, there are
  lots of places using the implicit constructor triggering the assertion
  on non-GPU kernels. That's found in compilation of many tests and
  workloads.
- Fixing all of them may change more code and, more importantly, all of
  them assumes the default kernel reference kind. This patch changes
  that constructor to tell `CUDAGlobalAttr` and construct `GlobalDecl`
  properly.

Reviewers: yaxunl

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76344
2020-03-18 09:33:39 -04:00
Oliver Stannard 6739805e24 [ARM] Track epilogue instructions with FrameDestroy flag (NFC)
Rather than trying to work out which instructions are part of the
epilogue by examining them, we can just mark them with the FrameDestroy
flag, like we do in the AArch64 backend.
2020-03-18 13:32:59 +00:00
Kazuaki Ishizaki a8901a0354 [mlir] NFC: Fix trivial typos in documents
Fix trivial typos

Reviewers: mravishankar, antiagainst, ftynse

Reviewed By: ftynse

Subscribers: ftynse, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, Joonsoo, bader, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76347
2020-03-18 22:20:17 +09:00
Med Ismail Bennani db31e2e1e6
[lldb/Target] Support more than 2 symbols in StackFrameRecognizer
This patch changes the way the StackFrame Recognizers match a certain
frame.

Until now, recognizers could be registered with a function
name but also an alternate symbol.
This change is motivated by a test failure for the Assert frame
recognizer on Linux. Depending the version of the libc, the abort
function (triggered by an assertion), could have more than two
signatures (i.e. `raise`, `__GI_raise` and `gsignal`).

Instead of only checking the default symbol name and the alternate one,
lldb will iterate over a list of symbols to match against.

rdar://60386577

Differential Revision: https://reviews.llvm.org/D76188

Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
2020-03-18 14:15:58 +01:00
Alexey Bataev b09cce07c7 [OPENMP50]Codegen for detach clause.
Implemented codegen for detach clause in task directives.
2020-03-18 09:01:17 -04:00
Francesco Petrogalli 9bdcd9bf44 [llvm][SVE] Addressing mode for FF/NF loads.
Summary:
This patch adds addressing mode computation for the following SVE
instructions:

* ldff1{s}<T1> { <Zt>.<T2> }, <Pg>/Z, [<Xn|SP>{, <Xm>{, lsl #imm}}]
* ldnf1{s}<T1> { <Zt>.<T2> }, <Pg>/Z, [<Xn|SP>{, #<imm>, mul vl}]

Reviewers: andwar, sdesmalen, rengolin, efriedma

Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76209
2020-03-18 12:46:07 +00:00
Sander de Smalen 4788ca450f [AArch64][SVE] Change pointer type of nontemporal load/store intrinsics
Summary:
This fixes a discrepancy between the non-temporal loads/store
intrinsics and other SVE load intrinsics (such as nf/ff), so
that Clang can use the same code to generate these intrinsics.

Reviewers: andwar, kmclaughlin, rengolin, efriedma

Reviewed By: efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76237
2020-03-18 12:44:51 +00:00
Danila Malyutin 940ba1465b Fix possible assertion when using PBQP with debug info
Skip debug instructions before calling functions not expecting them.
In particular, LIS.getInstructionIndex(*mi) would fail if mi was a debg instr.

Differential Revision: https://reviews.llvm.org/D76129
2020-03-18 15:29:42 +03:00
David Stenberg a0a3a9c5a8 [DebugInfo] Fix multi-byte entry values in call site values
Summary:
In D67768/D67492 I added support for entry values having blocks larger
than one byte, but I now noticed that the DIE implementation I added there
was broken. The takeNodes() function, that moves the entry value block
from a temporary buffer to the output buffer, would destroy the input
iterator when transferring the first node, meaning that only that node
was moved.

In practice, this meant that when emitting a call site value using a
DW_OP_entry_value operation with a DWARF register number larger than 31,
that multi-byte DW_OP_regx expression would be truncated.

Reviewers: djtodoro, aprantl, vsk

Reviewed By: djtodoro

Subscribers: llvm-commits

Tags: #debug-info, #llvm

Differential Revision: https://reviews.llvm.org/D76279
2020-03-18 13:23:17 +01:00
Florian Hahn 0db7244295 [SCCP] Precommit some additional tests for integer ranges. 2020-03-18 11:34:04 +00:00
Simon Pilgrim f4e495a18e [InstCombine][X86] simplifyX86varShift - convert variable in-range per-element shift amounts to generic shifts (PR40391)
AVX2/AVX512 per-element shifts can be replaced with generic shifts if the shift amounts are guaranteed to be in-range (upper bits are known zero).
2020-03-18 11:26:54 +00:00
Sander de Smalen c5b81466c2 Reland D75470 [SVE] Auto-generate builtins and header for svld1.
Reworked the patch to avoid sharing a header (SVETypeFlags.h) between
include/clang/Basic and utils/TableGen/SveEmitter.cpp. Now the patch
generates the enum/flags which is included in TargetBuiltins.h.

Also renamed one of the SveEmitter options to be in line with MVE.

Summary:

This is a first patch in a series for the SveEmitter to generate the arm_sve.h
header file and builtins.

I've tried my best to strip down this patch as best as I could, but there
are still a few changes that are not necessarily exercised by the load intrinsics
in this patch, mostly around the SVEType class which has some common logic to
represent types from a type and prototype string. I thought it didn't make
much sense to remove that from this patch and split it up.
2020-03-18 11:16:28 +00:00
Simon Tatham 928776de92 [ARM,MVE] Add intrinsics for the VQDMLAH family.
Summary:
These are complicated integer multiply+add instructions with extra
saturation, taking the high half of a double-width product, and
optional rounding. There's no sensible way to represent that in
standard IR, so I've converted the clang builtins directly to
target-specific intrinsics.

Reviewers: dmgreen, MarkMurrayARM, miyuki, ostannard

Reviewed By: miyuki

Subscribers: kristof.beyls, hiraditya, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76123
2020-03-18 10:55:04 +00:00
Simon Tatham 28c5d97bee [ARM,MVE] Add intrinsics and isel for MVE integer VMLA.
Summary:
These instructions compute multiply+add in integers, with one of the
operands being a splat of a scalar. (VMLA and VMLAS differ in whether
the splat operand is a multiplier or the addend.)

I've represented these in IR using existing standard IR operations for
the unpredicated forms. The predicated forms are done with target-
specific intrinsics, as usual.

When operating on n-bit vector lanes, only the bottom n bits of the
i32 scalar operand are used. So we have to tell that to isel lowering,
to allow it to remove a pointless sign- or zero-extension instruction
on that input register. That's done in `PerformIntrinsicCombine`, but
first I had to enable `PerformIntrinsicCombine` for MVE targets
(previously all the intrinsics it handled were for NEON), and make it
a method of `ARMTargetLowering` so that it can get at
`SimplifyDemandedBits`.

Reviewers: dmgreen, MarkMurrayARM, miyuki, ostannard

Reviewed By: dmgreen

Subscribers: kristof.beyls, hiraditya, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76122
2020-03-18 10:55:04 +00:00
serge-sans-paille 8d019cda85 Fix ac1d23ed7d interaction with gold plugin
Correctly set RelocationModel, thanks @modocache for spotting this.

Related to differential revision: https://reviews.llvm.org/D75579
2020-03-18 11:44:17 +01:00
Simon Pilgrim cda2b0769f [InstCombine][X86] Tests for variable but in-range per-element shift amounts (PR40391)
These shifts are masked to be inrange so we should be able to replace them with generic shifts.
2020-03-18 10:29:47 +00:00
Florian Hahn 5672ae8d86 [SCCP] Use constant ranges for select, if cond is overdefined.
For selects with an unknown condition, we can approximate the result by
merging the state of both options. This automatically takes care of
the case where on operand is undef.

Reviewers: davide, efriedma, mssimpso

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D71935
2020-03-18 09:26:02 +00:00
Sam Parker ef56b55e12 [NFC][ARM] Add thumb triple to test
Test the costs of selects for thumbv8m.base too.
2020-03-18 09:15:19 +00:00
Haojian Wu bd763e2cf7 [clang] Fix crash on visiting null nestedNameSpecifier.
Summary: Fix https://github.com/clangd/clangd/issues/293

Reviewers: sammccall

Subscribers: ilya-biryukov, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76320
2020-03-18 09:15:02 +01:00
Guillaume Chatelet c3df69faa0 [Alignment][NFC] Deprecate getTransientStackAlignment
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: jholewinski, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76301
2020-03-18 09:02:48 +01:00
Pengfei Wang 974d649f8e CET for Exception Handle
Summary:
Bug fix for https://bugs.llvm.org/show_bug.cgi?id=45182
Exception handle may indirectly jump to catch pad, So we should add ENDBR instruction before catch pad instructions.

Reviewers: craig.topper, hjl.tools, LuoYuanke, annita.zhang, pengfei

Reviewed By: LuoYuanke

Subscribers: hiraditya, llvm-commits

Patch By: Xiang Zhang (xiangzhangllvm)

Differential Revision: https://reviews.llvm.org/D76190
2020-03-17 22:35:05 -07:00
Alex Brachet 4d35055635 [libc] Add sigaction
Summary: This patch adds `sigaction` and the `sa_restorer` signal trampoline function `__restore_rt`

Reviewers: sivachandra, MaskRay, PaulkaToast

Reviewed By: sivachandra

Subscribers: gchatelet, mgorny, tschuett, libc-commits

Differential Revision: https://reviews.llvm.org/D75802
2020-03-18 01:08:59 -04:00
Vitaly Buka 9bca8fc4cf Revert "AMDGPU/GlobalISel: Fully handle 0 dmask case during legalize"
The patch introduced use-after-poison.

This reverts commit d0fe13ecf9.
2020-03-17 22:04:14 -07:00
River Riddle 34d0d6ba74 [mlir][DialectConversion] Print the operation being legalized if it has no regions
This helps when looking at the debug log and understanding what properties the invalid operation has when legalization fails.
2020-03-17 21:05:58 -07:00
Richard Smith e7a811b319 PR45133: Don't crash if the active member of a union changes while it's
in the process of being initialized.
2020-03-17 20:37:14 -07:00
QingShan Zhang d577193c0f [DAGCombine] Respect the uses when combine FMA for a*b+/-c*d
If it is a*b-c*d, it could be also folded into fma(a, b, -c*d) or fma(-c, d, a*b).
This patch is trying to respect the uses of a*b and c*d to make the best choice.

Differential Revision: https://reviews.llvm.org/D75982
2020-03-18 03:34:27 +00:00
River Riddle bd0ca2627c [mlir] Update DRR patterns to notify the rewriter why a pattern fails to match.
Summary:
This adds support in RewriterGen for calling into the new `PatternRewriter::notifyMatchFailure` hook. This lets derived pattern rewriters display this information to users, an example from DialectConversion is shown below:

```

Legalizing operation : 'std.and'(0x60e0000066a0) {
  * Fold {
  } -> FAILURE : unable to fold

  * Pattern : 'std.and -> (spv.BitwiseAnd)' {
    ** Failure : operand 0 of op 'std.and' failed to satisfy constraint: '8/16/32/64-bit integer or vector of 8/16/32/64-bit integer values of length 2/3/4'
  } -> FAILURE : pattern failed to match

  * Pattern : 'std.and -> (spv.LogicalAnd)' {
    ** Failure : operand 0 of op 'std.and' failed to satisfy constraint: 'bool or vector of bool values of length 2/3/4'
  } -> FAILURE : pattern failed to match
} -> FAILURE : no matched legalization pattern

```

Differential Revision: https://reviews.llvm.org/D76335
2020-03-17 20:22:00 -07:00
River Riddle 3145427dd7 [mlir][NFC] Replace all usages of PatternMatchResult with LogicalResult
This also replaces usages of matchSuccess/matchFailure with success/failure respectively.

Differential Revision: https://reviews.llvm.org/D76313
2020-03-17 20:21:32 -07:00
Nicolas Vasilache 2fae7878d5 [mlir][Vector] Mostly-NFC - Restructure options for lowering to LLVM Matrix Intrinsics
Summary:
This revision restructures the calling of vector transforms to make it more flexible to ask for lowering through LLVM matrix intrinsics.
This also makes sure we bail out in degenerate cases (i.e. 1) in which LLVM complains about not being able to scalarize.

Differential Revision: https://reviews.llvm.org/D76266
2020-03-17 22:58:02 -04:00
Stephen Neuendorffer 7ca473a27b [MLIR] Add support for out of tree external projects using MLIR
LLVM has a documented mechanism for passing configuration information
to an out of tree project using cmake.  See
https://llvm.org/docs/CMake.html#embedding-llvm-in-your-project.  This
patch adds similar support for MLIR.

Using this requires something like:

cmake_minimum_required(VERSION 3.4.3)
project(SimpleProject)

find_package(MLIR REQUIRED CONFIG)

include_directories(${LLVM_INCLUDE_DIRS})
include_directories(${MLIR_INCLUDE_DIRS})
link_directories(${LLVM_BUILD_LIBRARY_DIR})
add_definitions(${LLVM_DEFINITIONS})

set(CMAKE_MODULE_PATH
  ${LLVM_CMAKE_DIR}
  ${MLIR_CMAKE_DIR}
  )
include(AddLLVM)
include(TableGen)
include(AddMLIR)

add_executable(test-opt test-opt.cpp)
llvm_update_compile_flags(test-opt)

get_property(dialect_libs GLOBAL PROPERTY MLIR_DIALECT_LIBS)
get_property(conversion_libs GLOBAL PROPERTY MLIR_CONVERSION_LIBS)
message(dialects=${dialect_libs})
set(LIBS
  ${dialect_libs}
  ${conversion_libs}
  MLIRLoopOpsTransforms
  MLIRLoopAnalysis
  MLIRAnalysis
  MLIRDialect
  MLIREDSC
  MLIROptLib
  MLIRParser
  MLIRPass
  MLIRQuantizerFxpMathConfig
  MLIRQuantizerSupport
  MLIRQuantizerTransforms
  MLIRSPIRV
  MLIRSPIRVTestPasses
  MLIRSPIRVTransforms
  MLIRTransforms
  MLIRTransformUtils
  MLIRTestDialect
  MLIRTestIR
  MLIRTestPass
  MLIRTestTransforms
  MLIRSupport
  MLIRIR
  MLIROptLib
  LLVMSupport
  LLVMCore
  LLVMAsmParser
  )
target_link_libraries(test-opt ${LIBS})

Differential Revision: https://reviews.llvm.org/D76047
2020-03-17 19:43:39 -07:00
Jin Lin 7b166d5182 Revert "Support repeated machine outlining"
This reverts commit ab2dcff309.
2020-03-17 18:33:55 -07:00
Jin Lin ab2dcff309 Support repeated machine outlining
Summary: The following change is to allow the machine outlining can be applied for Nth times, where N is specified by the compiler option. By default the value of N is 1. The motivation is that the repeated machine outlining can further reduce code size.  Please refer to the presentation "Improving Swift Binary Size via Link Time Optimization" in LLVM Developers' Meeting in 2019.

Reviewers: aschwaighofer, tellenbach, paquette

Reviewed By: paquette

Subscribers: tellenbach, hiraditya, llvm-commits, jinlin

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71027
2020-03-17 18:11:08 -07:00
Nico Weber 4e0fe038f4 Revert "Avoid emitting unreachable SP adjustments after `throw`"
This reverts commit 65b21282c7.
Breaks sanitizer bots (https://reviews.llvm.org/D75712#1927668)
and causes https://crbug.com/1062021 (which may or may not
be a compiler bug, not clear yet).
2020-03-17 20:49:22 -04:00
Paula Toth a9e05d5711 [libc] Add AOR testing dependencies for buildbot workers.
Summary: These dependencies are needed for testing on the buildbots until we migrate AORs into libc.

Reviewers: sivachandra

Reviewed By: sivachandra

Subscribers: MaskRay, tschuett, libc-commits

Tags: #libc-project

Differential Revision: https://reviews.llvm.org/D76330
2020-03-17 17:43:55 -07:00
Michael Liao f2f8bdc2b1 Fix `-Wunused-variable` warning. NFC. 2020-03-17 20:15:50 -04:00
Matt Arsenault c9b454a1b7 AMDGPU/GlobalISel: Fix verifier errors on image atomics 2020-03-17 20:06:25 -04:00
Jonas Devlieghere a11b330418 [lldb/Bindings] Check that process isn't None before calling is_alive.
Make sure that `process` is not None before calling is_alive. Otherwise
this might result in an AttributeError: 'NoneType' object has no
attribute 'is_alive'.

Although lldb.process and friends could already be None in the past, for
example after leaving an interactive scripting session, the issue became
more prevalent after `fc1fd6bf9fcfac412b10b4193805ec5de0e8df57`.

I audited the other interface files for usages of target, process,
thread and frame, but this seems the only place where a global is used
from an SB class.
2020-03-17 17:06:04 -07:00
Scott Linder 68f163df0e [AMDGPU] Print DWARF register numbers in AMDGPUInstPrinter
Summary:
Explanation is in a comment in the diff, but essentially printing a
physical register name here is ambiguous. Until we can implement
printing a DWARF register name here just use the encoding directly.

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D76253
2020-03-17 19:42:10 -04:00
Jon Chesterfield cc691f3384 Disable loader-uninitialized tests on Windows 2020-03-17 23:33:12 +00:00
Jonas Devlieghere 3829d85cc6 [lldb/PlatformDarwin] Return POSIX path from FindXcodeContentsDirectoryInPath
Always return a POSIX-style path from FindXcodeContentsDirectoryInPath
so that the output is identical on all host platforms.
2020-03-17 15:57:34 -07:00
Rob Suderman 4d60f47b08 [mlir][NFC] Renamed VectorOps to Vector
Summary: Renamed VectorOps to Vector to avoid the redundant Ops suffix.

Differential Revision: https://reviews.llvm.org/D76317
2020-03-17 15:28:08 -07:00
Rob Suderman 363dd3f394 [mlir][NFC] Rename QuantOps to Quant
Summary:
Renamed QuantOps to Quant to avoid the Ops suffix. All dialects will contain
ops, so the Ops suffix is redundant.

Differential Revision: https://reviews.llvm.org/D76318
2020-03-17 15:16:47 -07:00
Jon Chesterfield 1d19b15395 Fix arm build broken by D74361 by dropping align from filecheck pattern 2020-03-17 22:15:19 +00:00