Commit Graph

22 Commits

Author SHA1 Message Date
Ashutosh Nema 51c9dd0081 Add new intrinsic support for MONITORX and MWAITX instructions
Summary:
MONITORX/MWAITX instructions provide similar capability to the MONITOR/MWAIT
pair while adding a timer function, such that another termination of the MWAITX
instruction occurs when the timer expires. The presence of the MONITORX and 
MWAITX instructions is indicated by CPUID 8000_0001, ECX, bit 29.

The MONITORX and MWAITX instructions are intercepted by the same bits that
intercept MONITOR and MWAIT. MONITORX instruction establishes a range to be
monitored. MWAITX instruction causes the processor to stop instruction
execution and enter an implementation-dependent optimized state until
occurrence of a class of events.

Opcode of MONITORX instruction is "0F 01 FA". Opcode of MWAITX instruction is
"0F 01 FB". These opcode information is used in adding tests for the
disassembler.

These instructions are enabled for AMD's bdver4 architecture.

Patch by Ganesh Gopalasubramanian!

Reviewers: echristo, craig.topper

Subscribers: RKSimon, joker.eph, llvm-commits, cfe-commits

Differential Revision: http://reviews.llvm.org/D19796

llvm-svn: 269907
2016-05-18 11:56:23 +00:00
Nico Weber 379a1952b3 [ms] Reintroduce feature guards in intrinsic headers in Microsoft mode
Visual Studio's C++ standard library headers include intrin.h, so the intrinsic
headers get included a lot more often in Microsoft mode than elsewhere. The
AVX512 intrinsics are a lot of code (0.7 MB, causing 30% compile time overhead
for small programs including e.g. <string> and 6% compile time overhead for
larger projects like e.g. v8). Since multiversioning can't be relied on in
Microsoft mode (cl.exe doesn't support it), having faster compiles seems like
the much better tradeoff until we have a better intrinsic story going forward
(which we'll need for e.g. PR19898).

Actually using intrinsics on Windows already requires the right /arch:
settings, so this patch should have no big behavior change.

See also thread "The intrinsics headers (especially avx512) are too big. What
to do about it?" on cfe-dev.

http://reviews.llvm.org/D20291

llvm-svn: 269675
2016-05-16 18:14:07 +00:00
Eric Christopher 9fc7fb274e Update the intel intrinsic headers to use the target attribute support.
This involved removing the conditional inclusion and replacing them
with target attributes matching the original conditional inclusion
and checks. The testcase update removes the macro checks for each
file and replaces them with usage of the __target__ attribute, e.g.:

int __attribute__((__target__(("sse3")))) foo(int a) {
  _mm_mwait(0, 0);
  return 4;
}

This usage does require the enclosing function have the requisite
__target__ attribute for inlining and code generation - also for
any macro intrinsic uses in the enclosing function. There's no change
for existing uses of the intrinsic headers.

llvm-svn: 239883
2015-06-17 07:09:32 +00:00
Nico Weber 1287091373 Replace a few // comments with /**/ comments in headers, for consistency.
llvm-svn: 212556
2014-07-08 18:29:27 +00:00
Alexey Bataev 7cab007902 Implement __readeflags and __writeeflags intrinsics
llvm-svn: 202778
2014-03-04 03:03:03 +00:00
Yunzhong Gao f4e0b1047a Adding intrinsics to the clang front end for the x86 TBM instruction set.
Differential Revision: http://llvm-reviews.chandlerc.com/D1751

llvm-svn: 191681
2013-09-30 17:25:14 +00:00
Ben Langmuir 6efe3a886e Move sha intrinsics to immintrin.h
This is consistent with ICC and Intel's SHA-enabled GCC version.

llvm-svn: 191002
2013-09-19 14:00:22 +00:00
Ben Langmuir 58078d0103 Add C intrinsics for Intel SHA Extensions
Intrinsics added shaintrin.h, which is included from x86intrin.h if __SHA__ is
enabled. SHA implies SSE2, which is needed for the __m128i type.

Also add the -msha/-mno-sha option.

llvm-svn: 190999
2013-09-19 13:22:04 +00:00
Michael Liao ffaae3511a Add RDSEED intrinsic support defined in AVX2 extension
llvm-svn: 178331
2013-03-29 05:17:55 +00:00
Michael Liao 74f4eaf4dc Add PRFCHW intrinsic support
- Add head 'prfchwintrin.h' to define '_m_prefetchw' which is mapped to
  LLVM/clang prefetch builtin
- Add option '-mprfchw' to enable PRFCHW feature and pre-define '__PRFCHW__'
  macro

llvm-svn: 178041
2013-03-26 17:52:08 +00:00
Manman Ren a45358c284 X86: add F16C support in Clang
Support the following intrinsics:
  _mm_cvtph_ps, _mm256_cvtph_ps, _mm_cvtps_ph, _mm256_cvtps_ph

rdar://12407875

llvm-svn: 165685
2012-10-11 00:59:55 +00:00
Craig Topper 33b6d5e20b Begin adding XOP intrinsics
llvm-svn: 158286
2012-06-10 00:39:38 +00:00
Craig Topper 9fd12db1c0 Update FIXME. ABM is already covered by LZCNT and POPCNT.
llvm-svn: 157676
2012-05-30 04:49:49 +00:00
Benjamin Kramer ba6e2528fa Add an ammintrin.h header for SSE4a intrinsics.
This is a clean-room implementation based on public documentation and
I tried to validate it as much as possible against gcc.

llvm-svn: 157638
2012-05-29 19:10:17 +00:00
Chandler Carruth a2a5410e6d Add 3dNOW intrinsic header to x86intrin.h, conditioned on __3dNOW__ to
match the behavior of GCC. Also add a test for these intrinsics, which
apparently have *zero* tests. =[ Not surprisingly, Clang crashed when
compiling these.

Fix the bug in CodeGen where we failed to bitcast the argument type to
x86mmx prior to calling the LLVM intrinsic. This fixes an assert on the
new 3dnow-builtins.c test.

This is one issue impacting the efforts to get Clang to emulate the
Microsoft intrinsics headers -- 3dnow intrinsics are implictitly made
available there.

llvm-svn: 150948
2012-02-20 07:35:45 +00:00
Craig Topper b4ceb6fd52 Add FMA4 intrinsics.
llvm-svn: 147372
2011-12-30 09:15:03 +00:00
Craig Topper ba418d8e91 Remove an accidental change from r147370. Would only break if the new fma4 flag was used.
llvm-svn: 147371
2011-12-30 07:35:49 +00:00
Craig Topper ffdb46ceef Add FMA4 feature flag. Intrinsics coming soon. Also make sse4a feature flag imply sse3. Matches gcc behavior.
llvm-svn: 147370
2011-12-30 07:33:42 +00:00
Craig Topper 1de8348db7 Add popcnt feature flag to match gcc. This flag is implied when sse42 is enabled, but can be disabled separately. Move popcnt intrinsics to popcntintrin.h to match gcc.
llvm-svn: 147340
2011-12-29 16:10:46 +00:00
Craig Topper c334dd68a7 Add BMI2 intrinsics.
llvm-svn: 147275
2011-12-26 02:31:10 +00:00
Craig Topper f2855ade2b Add intrinsics for lzcnt and tzcnt instructions.
llvm-svn: 147263
2011-12-25 06:25:37 +00:00
Nick Lewycky 0b84914da0 Add x86intrin.h which is generic x86 intrinsics for more than just Intel. Thus
far, this just #include's immintrin.h for compatibility.

llvm-svn: 111785
2010-08-22 20:38:05 +00:00