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4 Commits

Author SHA1 Message Date
Michael Liao 2de86af22d Add RORX code generation support 
llvm-svn: 164674
 2012-09-26 08:24:51 +00:00
Evan Cheng fe420adde0 Update tests. 
llvm-svn: 102487
 2010-04-28 01:53:13 +00:00
Dan Gohman 40503396da Eliminate more uses of llvm-as and llvm-dis. 
llvm-svn: 81290
 2009-09-08 23:54:48 +00:00
Dan Gohman a39b0a1f05 Define patterns for shld and shrd that match immediate 
shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.

Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.

Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.

These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.

llvm-svn: 57662
 2008-10-17 01:23:35 +00:00