0c598cdaf1
Add the "vbroadcasti128" instruction back.
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This is a follow-up to r231182. This adds the "vbroadcasti128" instruction
back, but without the intrinsic mapping. Also add a test to check the
instriction encoding.
This is related to rdar://problem/18742778.
llvm-svn: 231945
2015-03-11 17:29:03 +00:00
43860838dc
[X86] Improve parsing support AVX/SSE floating point compare instruction mnemonic aliases. They'll now print with the alias the parser received instead of converting to the explicit immediate form.
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llvm-svn: 229266
2015-02-14 21:54:03 +00:00
327f13b43b
Move address override handling in X86MCCodeEmitter to a place where it works for VEX encoded instructions too. This allows 32-bit addressing to work in 64-bit mode.
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llvm-svn: 200516
2014-01-31 05:33:45 +00:00
a422b09ae3
Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.
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llvm-svn: 192567
2013-10-14 04:55:01 +00:00
72c8cd7bc3
Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse.
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llvm-svn: 192171
2013-10-08 05:53:50 +00:00
a0e0735e6a
Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not.
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This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this.
llvm-svn: 192088
2013-10-07 05:42:48 +00:00
4f1c7256f9
Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior.
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cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix.
cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix.
Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein.
llvm-svn: 171668
2013-01-06 20:39:29 +00:00
c7690ac7ac
Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms.
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llvm-svn: 160775
2012-07-26 07:48:28 +00:00
01deb5f2df
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas.
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llvm-svn: 160420
2012-07-18 04:11:12 +00:00
be41e2daa6
Reverse assembler/disassembler operand order for gather instructions.
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llvm-svn: 159983
2012-07-10 06:38:33 +00:00
98a5bf24a9
X86: add more GATHER intrinsics in LLVM
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Corrected type for index of llvm.x86.avx2.gather.d.pd.256
from 256-bit to 128-bit.
Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256
from 256-bit to 128-bit.
Support the following intrinsics:
llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q
llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256
llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d
llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256
llvm-svn: 159402
2012-06-29 00:54:20 +00:00
a09820414a
X86: add GATHER intrinsics (AVX2) in LLVM
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Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256
Modified Disassembler to handle VSIB addressing mode.
llvm-svn: 159221
2012-06-26 19:47:59 +00:00
94bf0f3855
Remove some duplicate instructions that exist only to given different mnemonics for the assembler. Use InstAlias instead.
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llvm-svn: 159184
2012-06-26 04:12:49 +00:00
7629d63bc4
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.
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llvm-svn: 153935
2012-04-03 05:20:24 +00:00
64944090ff
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
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llvm-svn: 146709
2011-12-15 23:46:18 +00:00
33e91a6cf7
The wrong relocation was being emitted for several SSSE3 instructions.
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This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.
llvm-svn: 140184
2011-09-20 21:39:21 +00:00
c4398d2c7b
Fix PR10949. Fix the encoding of VMOVPQIto64rr.
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llvm-svn: 140098
2011-09-19 23:36:59 +00:00
d126347f32
Re-write part of VEX encoding logic, to be more easy to read! Also fix
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a bug and add a testcase!
llvm-svn: 138123
2011-08-19 22:27:29 +00:00
22241acc29
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
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implementation!
llvm-svn: 138029
2011-08-19 02:23:56 +00:00
646dd0f4d1
Revert r133452: "Emit movq for 64-bit register to XMM register moves..."
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This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.
llvm-svn: 133524
2011-06-21 17:35:13 +00:00
c7df192279
Emit movq for 64-bit register to XMM register moves, but continue to accept
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movd when assembling.
llvm-svn: 133452
2011-06-20 18:33:26 +00:00
4ca7bb52d0
move X86 subdir up a level
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llvm-svn: 115292
2010-10-01 04:32:20 +00:00
Juergen Ributzka