llvm-project

Commit Graph

Author	SHA1	Message	Date
Puyan Lotfi	43e94b15ea	Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922	2018-01-31 22:04:26 +00:00
Tim Northover	fb26d9a286	MIR: remove explicit "noVRegs" property. We can infer this from the incoming MIR, so there's no reason to represent it with a special flag. llvm-svn: 304246	2017-05-30 21:28:57 +00:00
Stanislav Mekhanoshin	bd5394be3d	[AMDGPU] Merge M0 initializations Merges equivalent initializations of M0 and hoists them into a common dominator block. Technically the same code can be used with any register, physical or virtual. Differential Revision: https://reviews.llvm.org/D32279 llvm-svn: 301228	2017-04-24 19:37:54 +00:00

Author

SHA1

Message

Date

Puyan Lotfi

43e94b15ea

Followup on Proposal to move MIR physical register namespace to '$' sigil.

Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922

2018-01-31 22:04:26 +00:00

Tim Northover

fb26d9a286

MIR: remove explicit "noVRegs" property.

We can infer this from the incoming MIR, so there's no reason to
represent it with a special flag.

llvm-svn: 304246

2017-05-30 21:28:57 +00:00

Stanislav Mekhanoshin

bd5394be3d

[AMDGPU] Merge M0 initializations

Merges equivalent initializations of M0 and hoists them into a common
dominator block. Technically the same code can be used with any
register, physical or virtual.

Differential Revision: https://reviews.llvm.org/D32279

llvm-svn: 301228

2017-04-24 19:37:54 +00:00

3 Commits