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122 Commits

Author SHA1 Message Date
Matt Arsenault 61cc9083d0 R600/SI: Change how DS offsets are printed 
Match SC by using offset/offset0/offset1 and printing
in decimal.

llvm-svn: 219537
 2014-10-10 22:16:07 +00:00
Tom Stellard 845bb3c2fd R600/SI: Refactor VOP3 instruction defs 
llvm-svn: 219256
 2014-10-07 23:51:41 +00:00
Tom Stellard 0aec5877b6 R600/SI: Refactor VOPC instruction defs 
llvm-svn: 219255
 2014-10-07 23:51:39 +00:00
Tom Stellard bec5a249b3 R600/SI: Refactor VOP2 instruction defs 
llvm-svn: 219254
 2014-10-07 23:51:38 +00:00
Tom Stellard 94d2e99ceb R600/SI: Refactor VOP1 instruction defs 
llvm-svn: 219253
 2014-10-07 23:51:34 +00:00
Tom Stellard 3a35d8f4c2 R600/SI: Add a generic pseudo EXP instruction 
llvm-svn: 218767
 2014-10-01 14:44:45 +00:00
Tom Stellard 0c238c2fbe R600/SI: Add generic pseudo MTBUF instructions 
llvm-svn: 218766
 2014-10-01 14:44:43 +00:00
Tom Stellard c470c96e6b R600/SI: Add generic pseudo SMRD instructions 
llvm-svn: 218765
 2014-10-01 14:44:42 +00:00
Matt Arsenault 9706978077 R600/SI: Fix printing of clamp and omod 
No tests for omod since nothing uses it yet, but
this should get rid of the remaining annoying trailing
zeros after some instructions.

llvm-svn: 218692
 2014-09-30 19:49:48 +00:00
Matt Arsenault 272c50a1fe R600/SI: Update VOP3b to not include obsolete operands 
abs / neg are now part of the srcN_modifiers operands

llvm-svn: 218691
 2014-09-30 19:49:43 +00:00
Tom Stellard 7980fc8562 R600/SI: Add support for global atomic add 
llvm-svn: 218457
 2014-09-25 18:30:26 +00:00
Tom Stellard 73ae1cb59a R600/SI: Clean up checks for legality of immediate operands 
There are new register classes VCSrc_* which represent operands that
can take an SGPR, VGPR or inline constant.  The VSrc_* class is now used
to represent operands that can take an SGPR, VGPR, or a 32-bit
immediate.

This allows us to have more accurate checks for legality of
immediates, since before we had no way to distinguish between operands
that supported any 32-bit immediate and operands which could only
support inline constants.

llvm-svn: 218334
 2014-09-23 21:26:25 +00:00
Tom Stellard 9f73851e39 Revert "R600/SI: Add support for global atomic add" 
This reverts commit r218254.

The global_atomics.ll test fails with asserts disabled.  For some reason,
the compiler fails to produce the atomic no return variants.

llvm-svn: 218257
 2014-09-22 16:44:04 +00:00
Tom Stellard 2355a77e74 R600/SI: Add support for global atomic add 
llvm-svn: 218254
 2014-09-22 15:35:35 +00:00
Matt Arsenault 3f98140c87 R600/SI: Add preliminary support for flat address space 
llvm-svn: 217777
 2014-09-15 15:41:53 +00:00
Matt Arsenault 7ac9c4a074 R600/SI: Replace LDS atomics with no return versions 
llvm-svn: 217379
 2014-09-08 15:07:31 +00:00
Matt Arsenault 9903ccf7ee R600/SI: Add InstrMapping for noret atomics. 
Only handles LDS atomics for now, and will be used
to replace atomics with no uses with the no return
versions.

llvm-svn: 217378
 2014-09-08 15:07:27 +00:00
Matt Arsenault 8675db15da R600/SI: Use mad for fsub + fmul 
We can use a negate source modifier to match
this for fsub.

llvm-svn: 216735
 2014-08-29 16:01:14 +00:00
Tom Stellard f3fc555e3b R600/SI: Use READ2/WRITE2 instructions for 64-bit mem ops with 32-bit alignment 
llvm-svn: 216279
 2014-08-22 18:49:35 +00:00
Tom Stellard 85e8b6d5f9 R600/SI: Use a ComplexPattern for DS loads and stores 
llvm-svn: 216278
 2014-08-22 18:49:33 +00:00
Tom Stellard 0510514e36 R600/SI: Use correct helper class for DS_WRITE2 instructions 
DS_1A uses a single offset encoding, so offset1 wasn't being
encoded.

llvm-svn: 216276
 2014-08-22 18:49:28 +00:00
Tom Stellard 155bbb7713 R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variant 
This saves us from having to copy a 64-bit 0 value into VGPRs for
BUFFER_* instruction which only have a 12-bit immediate offset.

llvm-svn: 215399
 2014-08-11 22:18:17 +00:00
Tom Stellard ddea48673f R600/SI: Add an _OFFEN variant MUBUF_STORE_* and use it for scratch writes 
llvm-svn: 215398
 2014-08-11 22:18:14 +00:00
Tom Stellard 93ba12f163 R600/SI: Clear lds bit on MUBUF instructions used for private stores 
This bit was left uninitialized, which was causing some random failures
of piglit tests.

NOTE: This is a candidate for the 3.5 branch.
llvm-svn: 215396
 2014-08-11 22:18:09 +00:00
Tom Stellard 229d5e669b R600/SI: Update MUBUF assembly string to match AMD proprietary compiler 
llvm-svn: 214866
 2014-08-05 14:48:12 +00:00
Eric Christopher d913448b38 Remove the TargetMachine forwards for TargetSubtargetInfo based 
information and update all callers. No functional change.

llvm-svn: 214781
 2014-08-04 21:25:23 +00:00
Matt Arsenault fa097f8f3d R600/SI: Fix definitions for ds_read2 / ds_write2 instructions. 
These were just wrong, using the wrong register classes
and store2 was missing an operand.

llvm-svn: 214756
 2014-08-04 18:49:22 +00:00
Matt Arsenault 9215b17eb7 R600/SI: Fix extra whitespace in asm str 
This slipped in in r214467, so something like

V_MOV_B32_e32  v0, ... is now printed with 2 spaces
between the instruction name and first operand.

llvm-svn: 214660
 2014-08-03 05:27:14 +00:00
Matt Arsenault cdcdb87a62 R600/SI: Don't display GDS bit for read2 
This isn't displayed for any other instructions anymore,
and isn't ever used.

llvm-svn: 214523
 2014-08-01 17:00:26 +00:00
Tom Stellard b4a313a76f R600/SI: Do abs/neg folding with ComplexPatterns 
Abs/neg folding has moved out of foldOperands and into the instruction
selection phase using complex patterns.  As a consequence of this
change, we now prefer to select the 64-bit encoding for most
instructions and the modifier operands have been dropped from
integer VOP3 instructions.

llvm-svn: 214467
 2014-08-01 00:32:39 +00:00
Tom Stellard bda32c9e47 R600/SI: Refactor VOP3 instruction definitions 
llvm-svn: 213571
 2014-07-21 17:44:29 +00:00
Tom Stellard f757b5ddc2 R600/SI: Initailize encoding fields of unused VOP3 modifiers to 0 
llvm-svn: 213564
 2014-07-21 17:12:40 +00:00
Tom Stellard ca000c6c7b R600/SI: Initialize unused VOP3 sources to 0 instead of SIOperand.ZERO 
llvm-svn: 213563
 2014-07-21 17:12:37 +00:00
Tom Stellard 1aaad6970c R600/SI: Add instruction shrinking pass 
This pass converts 64-bit instructions to 32-bit when possible.

llvm-svn: 213561
 2014-07-21 16:55:33 +00:00
Tom Stellard 63797d4a23 R600/SI: VOPC instructions explicitly define VCC 
Therefore we don't need to add it to the implict defs list.

llvm-svn: 213558
 2014-07-21 16:27:24 +00:00
Tom Stellard b02094e115 R600/SI: Use scratch memory for large private arrays 
llvm-svn: 213551
 2014-07-21 15:45:01 +00:00
Tom Stellard 8e44d948b6 R600/SI: Remove vaddr operand from BUFFER_LOAD_*_OFFSET instructions 
This operand is never used.

llvm-svn: 213549
 2014-07-21 15:44:55 +00:00
Tom Stellard 067c81567b R600/SI: Store constant initializer data in constant memory 
This implements a solution for constant initializers suggested
by Vadim Girlin, where we store the data after the shader code
and then use the S_GETPC instruction to compute its address.

This saves use the trouble of creating a new buffer for constant data
and then having to pass the pointer to the kernel via user SGPRs or the
input buffer.

llvm-svn: 213530
 2014-07-21 14:01:14 +00:00
Tom Stellard 01825afad7 R600/SI: Use a custom encoding method for simm16 in SOPP branch instructions 
This allows us to explicitly define the type of fixup that is needed,
so we can distinguish this from future fixup types.

llvm-svn: 213527
 2014-07-21 14:01:08 +00:00
Tom Stellard 7c1838d797 R600/SI: Use a ComplexPattern for ADDR64 addressing of MUBUF loads 
llvm-svn: 212217
 2014-07-02 20:53:56 +00:00
Tom Stellard b02c268cbd R600/SI: Use a ComplexPattern for MUBUF stores 
Now that non-leaf ComplexPatterns are allowed we can fold all the MUBUF
store patterns into the instruction definition.  We will also be able to
reuse this new ComplexPattern for MUBUF loads and atomic operations.

llvm-svn: 211644
 2014-06-24 23:33:07 +00:00
Matt Arsenault f2b0aebb8a R600/SI: Fix div_scale intrinsic. 
The operand that must match one of the others does matter,
and implement selecting for it.

llvm-svn: 211523
 2014-06-23 18:28:28 +00:00
Marek Olsak 51b8e7b2e7 R600/SI: add gather4 and getlod intrinsics (v3) 
This contains all the previous patches + getlod support on top of it.
It doesn't use SDNodes anymore, so it's quite small.
It also adds v16i8 to SReg_128, which is used for the sampler descriptor.

Reviewed-by: Tom Stellard
llvm-svn: 211228
 2014-06-18 22:00:29 +00:00
Matt Arsenault dbc9aae1fb R600/SI: Prettier operand printing for 64-bit ops. 
Copy what is done for 32-bit already so the order is about the same.

llvm-svn: 211186
 2014-06-18 17:13:51 +00:00
Matt Arsenault 520e7c44c1 R600/SI: Comparisons set vcc. 
llvm-svn: 211178
 2014-06-18 16:53:48 +00:00
Tom Stellard 092f332ef2 R600/SI: Make sure target flags are set on pseudo VOP3 instructions 
llvm-svn: 211120
 2014-06-17 19:34:46 +00:00
Matt Arsenault 2c81994f92 R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec* 
There is not such thing as a 0-data ds instruction, and the data
operand needs to be a vgpr set to something meaningful.

llvm-svn: 210756
 2014-06-12 08:21:54 +00:00
Matt Arsenault caa0ec2851 R600/SI: Add common 64-bit LDS atomics 
llvm-svn: 210680
 2014-06-11 18:08:54 +00:00
Matt Arsenault 8c6613d2bf R600/SI: Add instruction definitions for more LDS ops 
llvm-svn: 210675
 2014-06-11 18:08:39 +00:00
Matt Arsenault 8333e4378e R600/SI: Implement i64 ctpop 
llvm-svn: 210568
 2014-06-10 19:18:24 +00:00