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24 Commits

Author SHA1 Message Date
Krzysztof Parzyszek d91a9e27a9 [Hexagon] Simplify CFG after atomic expansion 
This will remove suboptimal branching from the generated ll/sc loops.
The extra simplification pass affects a lot of testcases, which have
been modified to accommodate this change: either by modifying the
test to become immune to the CFG simplification, or (less preferablt)
by adding option -hexagon-initial-cfg-clenaup=0.

llvm-svn: 338774
 2018-08-02 22:17:53 +00:00
Krzysztof Parzyszek 4e07509d18 [Hexagon] Properly scale bit index when extracting elements from vNi1 
For example v = <2 x i1> is represented as bbbbaaaa in a predicate register,
where b = v[1], a = v[0]. Extracting v[1] is equivalent to extracting bit 4
from the predicate register.

llvm-svn: 337934
 2018-07-25 16:20:59 +00:00
Krzysztof Parzyszek 23bcf06a15 [Hexagon] Add/fix patterns for 32/64-bit vector compares and logical ops 
llvm-svn: 330330
 2018-04-19 14:24:31 +00:00
Roorda, Jan-Willem 4b8bcf007b [Pipeliner] Fixed node order issue related to zero latency edges 
Summary:
A desired property of the node order in Swing Modulo Scheduling is
that for nodes outside circuits the following holds: none of them is
scheduled after both a successor and a predecessor. We call
node orders that meet this property valid.

Although invalid node orders do not lead to the generation of incorrect
code, they can cause the pipeliner not being able to find a pipelined schedule
for arbitrary II. The reason is that after scheduling the successor and the
predecessor of a node, no room may be left to schedule the node itself.

For data flow graphs with 0-latency edges, the node ordering algorithm
of Swing Modulo Scheduling can generate such undesired invalid node orders.
This patch fixes that.

In the remainder of this commit message, I will give an example
demonstrating the issue, explain the fix, and explain how the the fix is tested.

Consider, as an example, the following data flow graph with all
edge latencies 0 and all edges pointing downward.

```
   n0
  /  \
n1    n3
  \  /
   n2
    |
   n4
```

Consider the implemented node order algorithm in top-down mode. In that mode,
the algorithm orders the nodes based on greatest Height and in case of equal
Height on lowest Movability. Finally, in case of equal Height and
Movability, given two nodes with an edge between them, the algorithm prefers
the source-node.

In the graph, for every node, the Height and Movability are equal to 0.
As will be explained below, the algorithm can generate the order n0, n1, n2, n3, n4.
So, node n3 is scheduled after its predecessor n0 and after its successor n2.

The reason that the algorithm can put node n2 in the order before node n3,
even though they have an edge between them in which node n3 is the source,
is the following: Suppose the algorithm has constructed the partial node
order n0, n1. Then, the nodes left to be ordered are nodes n2, n3, and n4. Suppose
that the while-loop in the implemented algorithm considers the nodes in
the order n4, n3, n2. The algorithm will start with node n4, and look for
more preferable nodes. First, node n4 will be compared with node n3. As the nodes
have equal Height and Movability and have no edge between them, the algorithm
will stick with node n4. Then node n4 is compared with node n2. Again the
Height and Movability are equal. But, this time, there is an edge between
the two nodes, and the algorithm will prefer the source node n2.
As there are no nodes left to compare, the algorithm will add node n2 to
the node order, yielding the partial node order n0, n1, n2. In this way node n2
arrives in the node-order before node n3.

To solve this, this patch introduces the ZeroLatencyHeight (ZLH) property
for nodes. It is defined as the maximum unweighted length of a path from the
given node to an arbitrary node in which each edge has latency 0.
So, ZLH(n0)=3, ZLH(n1)=ZLH(n3)=2, ZLH(n2)=1, and ZLH(n4)=0

In this patch, the preference for a greater ZeroLatencyHeight
is added in the top-down mode of the node ordering algorithm, after the
preference for a greater Height, and before the preference for a
lower Movability.

Therefore, the two allowed node-orders are n0, n1, n3, n2, n4 and n0, n3, n1, n2, n4.
Both of them are valid node orders.

In the same way, the bottom-up mode of the node ordering algorithm is adapted
by introducing the ZeroLatencyDepth property for nodes.

The patch is tested by adding extra checks to the following existing
lit-tests:
test/CodeGen/Hexagon/SUnit-boundary-prob.ll
test/CodeGen/Hexagon/frame-offset-overflow.ll
test/CodeGen/Hexagon/vect/vect-shuffle.ll

Before this patch, the pipeliner failed to pipeline the loops in these tests
due to invalid node-orders. After the patch, the pipeliner successfully
pipelines all these loops.

Reviewers: bcahoon

Reviewed By: bcahoon

Subscribers: Ayal, mgrang, llvm-commits

Differential Revision: https://reviews.llvm.org/D43620

llvm-svn: 326925
 2018-03-07 18:53:36 +00:00
Krzysztof Parzyszek 2c3edf0567 [Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned ones 
This is a follow-up to r325169, this time for all types, not just HVX
vector types.

Disable this by default, since it's not always safe. 

llvm-svn: 326915
 2018-03-07 17:27:18 +00:00
Krzysztof Parzyszek c9f797fdd0 [Hexagon] Remove {{ *}} from testcases 
The spaces in the instructions are now consistent.

llvm-svn: 326829
 2018-03-06 19:07:21 +00:00
Krzysztof Parzyszek b2c458e648 [Hexagon] SETEQ and SETNE are valid integer condition codes 
llvm-svn: 323452
 2018-01-25 18:07:27 +00:00
Krzysztof Parzyszek cf3ad5841b [Hexagon] Run late copy propagation and dead code elimination passes 
llvm-svn: 323346
 2018-01-24 17:48:11 +00:00
Krzysztof Parzyszek 3780a0e1fa [Hexagon] Implement basic vector operations on vectors vNi1 
In addition to that, make sure that there are no boolean vector types that
are associated with multiple register classes. Specifically, remove v32i1
and v64i1 from integer register classes. These types will correspond to
results of vector comparisons, and as such should belong to the vector
predicate class. Having them in scalar registers as well makes legalization
ambiguous.

llvm-svn: 323229
 2018-01-23 17:53:59 +00:00
Krzysztof Parzyszek b8f2a1e7b7 [Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectors 
The old implementation was not always correct. The new one recognizes
more shuffles that match specific instructions.

llvm-svn: 322498
 2018-01-15 18:33:33 +00:00
Krzysztof Parzyszek 240df6faa4 [Hexagon] Fix building 64-bit vector from constant values 
The constants were aggregated in a reverse order.

llvm-svn: 322303
 2018-01-11 18:30:41 +00:00
Krzysztof Parzyszek 66ee123d61 [Hexagon] Add pattern for vsplat to v8i8 
llvm-svn: 321892
 2018-01-05 20:43:56 +00:00
Krzysztof Parzyszek e4ce92cabf [Hexagon] Allow construction of HVX vector predicates 
Handle BUILD_VECTOR of boolean values.

llvm-svn: 321220
 2017-12-20 20:49:43 +00:00
Krzysztof Parzyszek 8f6b0c850a [Hexagon] Adjust the value type for BCvt in LowerFormalArguments 
llvm-svn: 321177
 2017-12-20 14:44:05 +00:00
Krzysztof Parzyszek f4dcc42e7b [Hexagon] Remove HexagonISD::PACKHL 
llvm-svn: 319352
 2017-11-29 19:59:29 +00:00
Krzysztof Parzyszek 942fa1631f [Hexagon] Implement buildVector32 and buildVector64 as utility functions 
Change LowerBUILD_VECTOR to use those functions. This commit will tempora-
rily affect constant vector generation (it will generate constant-extended
values instead of non-extended combines), but the code for the general case
should be better. The constant selection part will be fixed later.

llvm-svn: 318877
 2017-11-22 20:56:23 +00:00
Krzysztof Parzyszek 64e5d7d3ae [Hexagon] Reorganize and update instruction patterns 
llvm-svn: 316228
 2017-10-20 19:33:12 +00:00
Ron Lieberman f90493d220 [Hexagon] Patch to Extract i1 element from vector of i1 
This patch extracts 1 element from vector consisting
of elements of size 1 bit at given index.

llvm-svn: 314641
 2017-10-02 00:16:15 +00:00
Krzysztof Parzyszek 5eef92eb7f [Hexagon] Remove custom lowering of loads of v4i16 
The target-independent lowering works fine, except concatenating 32-bit
words. Add a pattern to generate A2_combinew instead of 64-bit asl/or.

llvm-svn: 308186
 2017-07-17 15:45:45 +00:00
Krzysztof Parzyszek 33fd0bbbe8 [Hexagon] Generate extract instructions more aggressively 
llvm-svn: 296537
 2017-02-28 23:27:33 +00:00
Krzysztof Parzyszek a72fad980c [Hexagon] Replace instruction definitions with auto-generated ones 
llvm-svn: 294753
 2017-02-10 15:33:13 +00:00
Krzysztof Parzyszek 167d918225 [Hexagon] Implement MI-level constant propagation 
llvm-svn: 277028
 2016-07-28 20:01:59 +00:00
Krzysztof Parzyszek a7c5f0409c [Hexagon] Split double registers 
llvm-svn: 250549
 2015-10-16 20:38:54 +00:00
Krzysztof Parzyszek 421133470f [Hexagon] Add support for vector instructions 
llvm-svn: 232728
 2015-03-19 16:33:08 +00:00