Commit Graph

7 Commits

Author SHA1 Message Date
Artyom Skrobov b43981076a [ARM] Allow SP in rGPR, starting from ARMv8
Summary:
This patch handles assembly and disassembly, but not codegen, as of yet.

Additionally, it fixes a bug whereby SP and PC as shifted-reg operands
were treated as predictable in ARMv7 Thumb; and it enables the tests
for invalid and unpredictable instructions to run on both ARMv7 and ARMv8.

Reviewers: jmolloy, rengolin

Subscribers: aemerson, rengolin, llvm-commits

Differential Revision: http://reviews.llvm.org/D14141

llvm-svn: 251516
2015-10-28 13:58:36 +00:00
Saleem Abdulrasool 27351f2022 ARM: implement support for the UDF mnemonic
The UDF instruction is a reserved undefined instruction space.  The assembler
mnemonic was introduced with ARM ARM rev C.a.  The instruction is not predicated
and the immediate constant is ignored by the CPU.  Add support for the three
encodings for this instruction.

The changes to the invalid instruction test is due to the fact that the invalid
instructions actually overlap with the undefined instruction.  Introduction of
the new instruction results in a partial decode as an undefined sequence.  Drop
the tests as they are invalid instruction patterns anyways.

llvm-svn: 208751
2014-05-14 03:47:39 +00:00
Tim Northover 08a8660260 ARM: provide diagnostics on more writeback LDM/STM instructions
The set of circumstances where the writeback register is allowed to be in the
list of registers is rather baroque, but I think this implements them all on
the assembly parsing side.

For disassembly, we still warn about an ARM-mode LDM even if the architecture
revision is < v7 (the required architecture information isn't available). It's
a silly instruction anyway, so hopefully no-one will mind.

rdar://problem/15223374

llvm-svn: 193185
2013-10-22 19:00:39 +00:00
Richard Barton 87dacc38b8 Add hint disassembly syntax for 16-bit Thumb hint instructions.
Patch by Artyom Skrobov

llvm-svn: 192972
2013-10-18 14:09:49 +00:00
Joey Gouly ad98f1671d [ARM] Introduce the 'sevl' instruction in ARMv8.
This also removes the restriction on the immediate field of the 'hint'
instruction.

llvm-svn: 191744
2013-10-01 12:39:11 +00:00
Rafael Espindola 91997c0f94 Add not so that these tests pass with pipefail enabled.
llvm-svn: 186939
2013-07-23 13:18:20 +00:00
Tim Northover 48cf6cc416 Improve llvm-mc disassembler mode and refactor ARM tests to use it
This allows "llvm-mc -disassemble" to accept two new features:
  + Using comma as a byte separator
  + Grouping bytes with '[' and ']' pairs.

The behaviour outside a [...] group is unchanged. But within the group once
llvm-mc encounters a true error, it stops rather than trying to resynchronise
the stream at the next byte. This is more useful for disassembly tests, where
we have an almost-instruction in mind and don't care what the misaligned
interpretation would be. Particularly if it means llvm-mc won't actually see
the next intended almost-instruction.

As a side effect, this means llvm-mc can disassemble its own -show-encoding
output if copy-pasted.

llvm-svn: 186661
2013-07-19 10:05:04 +00:00