f24f9d9cb6
Whitespace cleanup. Remove trailing whitespace.
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llvm-svn: 78666
2009-08-11 15:33:49 +00:00
780748d565
- More refactoring. This gets rid of all of the getOpcode calls.
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- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
llvm-svn: 77300
2009-07-28 05:48:47 +00:00
0e5b149930
Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target.
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llvm-svn: 77174
2009-07-27 00:24:36 +00:00
26b51b15ed
Just use a single isMoveInstr to catch all the cases.
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llvm-svn: 77173
2009-07-27 00:05:15 +00:00
95fc6ee51a
Remove unused member functions.
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llvm-svn: 76960
2009-07-24 07:43:59 +00:00
cdd405d804
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
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llvm-svn: 76919
2009-07-24 00:16:18 +00:00
6deba28c6f
Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.
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llvm-svn: 76883
2009-07-23 17:06:46 +00:00
af7451b674
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
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llvm-svn: 75010
2009-07-08 16:09:28 +00:00
ade05a37f1
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2.
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llvm-svn: 74731
2009-07-02 22:18:33 +00:00
Jim Grosbach