Commit Graph

127 Commits

Author SHA1 Message Date
Evan Cheng dcff2eb0e8 PredicateInstruction returns true if the operation was successful.
llvm-svn: 37124
2007-05-16 21:53:07 +00:00
Evan Cheng e2762c3d68 Removed isPredicable().
llvm-svn: 37119
2007-05-16 20:50:23 +00:00
Evan Cheng ad3aac71ce Hooks for predication support.
llvm-svn: 37093
2007-05-16 02:01:49 +00:00
Evan Cheng 0f7cbe8370 Add PredicateOperand to all ARM instructions that have the condition field.
llvm-svn: 37066
2007-05-15 01:29:07 +00:00
Dale Johannesen 4a00cf3fc4 Rewrite of Thumb constant islands handling (exact allowance for padding
around islands and jump tables).

llvm-svn: 36573
2007-04-29 19:19:30 +00:00
Evan Cheng 910c80851e Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.
llvm-svn: 36483
2007-04-26 19:00:32 +00:00
Evan Cheng 8cd224e81c Relex assertions to account for additional implicit def / use operands.
llvm-svn: 36430
2007-04-25 07:12:14 +00:00
Anton Korobeynikov fb80151c42 Removed tabs everywhere except autogenerated & external files. Add make
target for tabs checking.

llvm-svn: 36146
2007-04-16 18:10:23 +00:00
Evan Cheng e8315fe3f5 Inverted logic.
llvm-svn: 35619
2007-04-03 06:44:25 +00:00
Evan Cheng 7dbbd00b06 findRegisterUseOperand() changed.
llvm-svn: 35366
2007-03-26 22:41:48 +00:00
Evan Cheng 9bb01c9f4f Fix naming inconsistencies.
llvm-svn: 35163
2007-03-19 07:48:02 +00:00
Evan Cheng ec13f826a2 Spill / restore should avoid modifying the condition register.
llvm-svn: 33971
2007-02-07 00:06:56 +00:00
Evan Cheng 95b85e34ff Copy and paste bug.
llvm-svn: 33658
2007-01-30 08:22:33 +00:00
Evan Cheng ce8fa3ed83 Misseed thumb jumptable branch.
llvm-svn: 33656
2007-01-30 08:03:06 +00:00
Evan Cheng 760c68b8af Factor GetInstSize() out of constpool island pass.
llvm-svn: 33644
2007-01-29 23:45:17 +00:00
Jim Laskey f9e5445ed4 Make LABEL a builtin opcode.
llvm-svn: 33537
2007-01-26 14:34:52 +00:00
Evan Cheng 10043e215b ARM backend contribution from Apple.
llvm-svn: 33353
2007-01-19 07:51:42 +00:00
Evan Cheng 20350c4025 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.

llvm-svn: 31947
2006-11-27 23:37:22 +00:00
Rafael Espindola ed32883b27 fix warning about missing newline at end of file
llvm-svn: 31162
2006-10-24 17:07:11 +00:00
Chris Lattner aaeede0aa2 implement uncond branch insertion, mark branches with isBranch.
llvm-svn: 31160
2006-10-24 16:47:57 +00:00
Rafael Espindola 3130a756ef add shifts to addressing mode 1
llvm-svn: 30291
2006-09-13 12:09:43 +00:00
Rafael Espindola e45a79a9e2 partial implementation of the ARM Addressing Mode 1
llvm-svn: 30252
2006-09-11 17:25:40 +00:00
Rafael Espindola 8c41f99e6f change the addressing mode of the str instruction to reg+imm
llvm-svn: 29571
2006-08-08 20:35:03 +00:00
Rafael Espindola e40a7e2aa2 create the raddr addressing mode that matches any register and the frame index
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot

llvm-svn: 29079
2006-07-10 01:41:35 +00:00
Rafael Espindola f6f5aff038 handle the "mov reg1, reg2" case in isMoveInstr
llvm-svn: 28945
2006-06-27 21:52:45 +00:00
Rafael Espindola 27f8bdc7e5 implement minimal versions of
ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr

llvm-svn: 28431
2006-05-23 02:48:20 +00:00
Rafael Espindola ffdc24b847 added a skeleton of the ARM backend
llvm-svn: 28301
2006-05-14 22:18:28 +00:00