f66840020c
Reverting commit 306414 on behalf of @gadi.haber
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llvm-svn: 306532
2017-06-28 11:23:31 +00:00
13759a7ed6
Updated and extended the information about each instruction in HSW and SNB to include the following data:
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•static latency
•number of uOps from which the instructions consists
•all ports used by the instruction
Reviewers:
RKSimon
zvi
aymanmus
m_zuckerman
Differential Revision: https://reviews.llvm.org/D33897
llvm-svn: 306414
2017-06-27 15:05:13 +00:00
8cb1d0931f
Add scheduler classes to integer/float horizontal operations.
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This patch will close PR32801.
Differential Revision: https://reviews.llvm.org/D33203
llvm-svn: 304986
2017-06-08 16:44:13 +00:00
e2c055b8c5
[X86][AVX] Added zeroall/zeroupper scheduler tests
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Missing on SandyBridge and Btver2 models
llvm-svn: 302804
2017-05-11 15:02:49 +00:00
9111cd950d
[X86][AVX] Add scheduling latency/throughput tests for missing AVX1 instructions
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Had to split btver2/znver1 checks as only btver2 suppresses zeroupper
llvm-svn: 301181
2017-04-24 14:26:30 +00:00
12df01c3c7
[X86][AVX] Add scheduling latency/throughput tests for some AVX1 instructions
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More instructions will be added in future commits
llvm-svn: 301145
2017-04-23 22:08:17 +00:00
Michael Zuckerman