Commit Graph

9 Commits

Author SHA1 Message Date
Daniel Sanders fa961d76f0 [mips] Prevent %lo relocation being used on MSA loads and stores.
Summary:
Parts of the compiler still believed MSA load/stores have a 16-bit offset when
it is actually 10-bit. Corrected this, and fixed a closely related issue this
uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS
respectively) could not load/store using offsets from the stack/frame pointer.
They accepted frameindex+offset, but not frameindex by itself.

Reviewers: jacksprat, matheusalmeida

Reviewed By: jacksprat

Differential Revision: http://llvm-reviews.chandlerc.com/D2888

llvm-svn: 202717
2014-03-03 14:31:21 +00:00
Daniel Sanders 3f6eb546d3 [mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics)
llvm-svn: 194471
2013-11-12 10:45:18 +00:00
Daniel Sanders d74b130cc9 [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)
This required correcting the definition of the bins[lr]i intrinsics because
the result is also the first operand.

It also required removing the (arbitrary) check for 32-bit immediates in
MipsSEDAGToDAGISel::selectVSplat().

Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d
because the constant is legalized into a ConstantPool. Similar things can
happen with binsri.d with more than 10 bits set in the mask. The resulting
code when this happens is correct but not optimal.

llvm-svn: 193687
2013-10-30 14:45:14 +00:00
Daniel Sanders 7e51fe19d5 [mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics)
Updated some of the vshf since they (correctly) emit splati's now

llvm-svn: 191511
2013-09-27 11:48:57 +00:00
Daniel Sanders f49dd82e06 [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR.
Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover
bitcasted as well as normal vectors. However, it doesn't seem to be possible to
match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of
immediates, it should be possible to use ldi.b to load v2i64) using TableGen so
ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp

This made the majority of the constant splat BUILD_VECTOR lowering redundant.
The only transformation remaining for constant splats is when an (up-to) 32-bit
constant splat is possible but the value does not fit into a 10-bit signed
integer. In this case, the BUILD_VECTOR is transformed into a bitcasted
BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32
register (which is initialized using the usual lui/addui sequence).

There are no additional tests since this is a re-implementation of previous
functionality. The change is intended to make it easier to implement some of
the upcoming instruction selection patches since they can rely on existing
support for BUILD_VECTOR's in the DAGCombiner.

compare_float.ll changed slightly because a BITCAST is no longer
introduced during legalization.

llvm-svn: 191299
2013-09-24 13:33:07 +00:00
Daniel Sanders e6ed5b72f1 [mips][msa] Added load/store intrinsics.
llvm-svn: 189476
2013-08-28 12:04:29 +00:00
Jack Carter 9770097727 [Mips] Support for unaligned load/store microMips instructions
This includes instructions lwl, lwr, swl and swr.

Patch by Zoran Jovnovic

llvm-svn: 188312
2013-08-13 20:19:16 +00:00
Akira Hatanaka 040d225588 [mips] Rename functions and variables to start with proper case.
llvm-svn: 177092
2013-03-14 18:33:23 +00:00
Akira Hatanaka 29a0da3551 Add header file MipsISelDAGToDAG.h.
llvm-svn: 177090
2013-03-14 18:28:19 +00:00