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41 Commits

Author SHA1 Message Date
Zoran Jovanovic cabf0f41e0 Implementation of 16-bit microMIPS instructions MFHI and MFLO. 
Differential Revision: http://llvm-reviews.chandlerc.com/D3141

llvm-svn: 205532
 2014-04-03 12:47:34 +00:00
Zoran Jovanovic 9b05a31f76 Fixed issue with microMIPS JAL instruction. 
Differential Revision: http://llvm-reviews.chandlerc.com/D3200

llvm-svn: 205185
 2014-03-31 14:00:10 +00:00
Zoran Jovanovic a0f5328984 Provide an operand for microMIPS wait instruction. 
llvm-svn: 204329
 2014-03-20 10:41:37 +00:00
Zoran Jovanovic 87d13e5ec1 Implementation of microMIPS 16-bit instructions MOVE and JALR. 
Differential Revision: http://llvm-reviews.chandlerc.com/D3112

llvm-svn: 204325
 2014-03-20 10:18:24 +00:00
Zoran Jovanovic 285cc289e8 Fixed operand of SC microMIPS instruction. 
llvm-svn: 202526
 2014-02-28 18:22:56 +00:00
Daniel Sanders 0b385ac138 [mips][sched] Split IILoad into II_L[BHWD], II_L[BHW]U, II_L[WD][LR], and II_RESTORE 
No functional change since the InstrItinData's have been duplicated.

llvm-svn: 199749
 2014-01-21 15:21:14 +00:00
Daniel Sanders c7a9f8d298 [mips] Split IIIdiv int II_DIV, II_DIVU, II_DDIV, and II_DDIVU 
No functional change since the InstrItinData's were duplicated

llvm-svn: 199497
 2014-01-17 14:48:06 +00:00
Daniel Sanders e95a137b96 [mips][sched] Split IIImul and IIImult into subclasses. 
IIImul -> II_MUL
IIImult -> II_MULT, II_MULTU, II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_DMULT, II_DMULTU

No functional change since the InstrItinData's have been duplicated.

llvm-svn: 199495
 2014-01-17 14:32:41 +00:00
Daniel Sanders 4aefdc7bda [mips][sched] Put AND, OR, XOR, MOVT_I, and MOVF_I in the same itinerary class as their non-microMIPS counterparts. 
No functional change since both classes have the same InstrItinData definition.

llvm-svn: 199402
 2014-01-16 17:13:57 +00:00
Daniel Sanders 4d20f0c00f [mips][sched] Split IIseb into II_SEB and II_SEH 
No functional change since there are no InstrItinData's.

llvm-svn: 199396
 2014-01-16 16:19:38 +00:00
Daniel Sanders 980589a803 [mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. 
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
  II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
  II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
  II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
  II_SR[AL]V, II_SUBU, II_XOR

No functional change since the InstrItinData's have been duplicated.

This is necessary because the classes are shared between all schedulers.

Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.

llvm-svn: 199391
 2014-01-16 14:27:20 +00:00
Daniel Sanders bfe1830ab9 [mips] Correct itin class for MULT_MM and MULTu_MM to IIImult. 
This matches the itin class used by the non-microMIPS equivalents of these
instructions.

llvm-svn: 199389
 2014-01-16 14:02:48 +00:00
Zoran Jovanovic 7d63392da9 LL and SC decoder method fix. 
llvm-svn: 199316
 2014-01-15 13:17:33 +00:00
Zoran Jovanovic d4cb61cf0e Added support for LWU microMIPS instruction. 
llvm-svn: 199315
 2014-01-15 13:01:18 +00:00
Zoran Jovanovic bd28c373c4 Support for microMIPS load effective address. 
llvm-svn: 198010
 2013-12-25 10:14:07 +00:00
Zoran Jovanovic 8e918c3c4d Support for microMIPS control instructions. 
llvm-svn: 197696
 2013-12-19 16:25:00 +00:00
Zoran Jovanovic ff9d5f3284 Support for microMIPS LL and SC instructions. 
llvm-svn: 197692
 2013-12-19 16:12:56 +00:00
Akira Hatanaka f6109e4ad7 [mips] Redefine TAILCALL as a pseudo instruction. 
No functionality change.

llvm-svn: 195896
 2013-11-27 23:58:32 +00:00
Zoran Jovanovic ccb70caa13 Support for microMIPS trap instruction with immediate operands. 
llvm-svn: 194569
 2013-11-13 13:15:03 +00:00
Zoran Jovanovic c18b6d1083 Support for microMIPS trap instructions 1. 
llvm-svn: 194205
 2013-11-07 14:35:24 +00:00
Zoran Jovanovic 8a80aa76c8 Support for microMIPS branch instructions. 
llvm-svn: 193992
 2013-11-04 14:53:22 +00:00
Zoran Jovanovic 507e084a18 Support for microMIPS jump instructions 
llvm-svn: 193623
 2013-10-29 16:38:59 +00:00
Akira Hatanaka 16048332f1 [mips] Fix definition of mfhi and mflo instructions to read from the whole 
accumulator instead of its sub-registers, $hi and $lo. 

We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:

mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2     // read lower 32-bit result from $lo.
mtlo $4     // write to $lo. the content of $hi becomes unpredictable.
mfhi $3     // read higher 32-bit from $hi, which has an unpredictable value.

I don't have a test case for this change that reliably reproduces the problem.

llvm-svn: 192119
 2013-10-07 18:49:46 +00:00
Zoran Jovanovic 3671a5441a Support for microMIPS DIV instructions. 
llvm-svn: 190745
 2013-09-14 07:15:21 +00:00
Zoran Jovanovic ab85278137 Support for misc microMIPS instructions. 
llvm-svn: 190744
 2013-09-14 06:49:25 +00:00
Akira Hatanaka 3121353c99 [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit 
into a 5-bit or 6-bit field.

llvm-svn: 190226
 2013-09-07 00:02:02 +00:00
Vladimir Medic b936da159e This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch. 
llvm-svn: 190154
 2013-09-06 13:08:00 +00:00
Vladimir Medic 457ba56b05 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch. 
llvm-svn: 190152
 2013-09-06 12:53:21 +00:00
Vladimir Medic e0fbb44a48 This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch. 
llvm-svn: 190148
 2013-09-06 12:41:17 +00:00
Vladimir Medic dde3d582a2 This patch adds support for microMIPS disassembler and disassembler make check tests. 
llvm-svn: 190144
 2013-09-06 12:30:36 +00:00
Akira Hatanaka 6781fc1648 [mips] Resolve register classes dynamically using ptr_rc to reduce the number of 
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.

llvm-svn: 188830
 2013-08-20 21:08:22 +00:00
Akira Hatanaka a43b56d9af [mips] Guard micromips instructions with predicate InMicroMips. Also, fix 
assembler predicate HasStdEnd so that it is false when the target is micromips.

llvm-svn: 188824
 2013-08-20 20:46:51 +00:00
Akira Hatanaka 8002a3f6d8 [mips] Rename HIRegs and LORegs. 
llvm-svn: 188341
 2013-08-14 00:47:08 +00:00
Jack Carter 9770097727 [Mips] Support for unaligned load/store microMips instructions 
This includes instructions lwl, lwr, swl and swr.

Patch by Zoran Jovnovic

llvm-svn: 188312
 2013-08-13 20:19:16 +00:00
Akira Hatanaka 13e6ccf341 [mips] Rename register classes CPURegs and CPU64Regs. 
llvm-svn: 187832
 2013-08-06 23:08:38 +00:00
Akira Hatanaka 34a32c0b87 [mips] Replace usages of register classes with register operands. Also, remove 
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.

llvm-svn: 187821
 2013-08-06 22:20:40 +00:00
Akira Hatanaka f8fff213d5 [mips] Define instruction itineraries IIArith and IILogic. 
No functionality change.

llvm-svn: 187468
 2013-07-31 00:55:34 +00:00
Jack Carter 59817110ff Mips td file formatting: white space and long lines 
llvm-svn: 182047
 2013-05-16 20:08:49 +00:00
Akira Hatanaka f0aa6c9101 [mips] Add definitions of micromips load and store instructions. 
Patch by Zoran Jovanovic.

llvm-svn: 180241
 2013-04-25 01:21:25 +00:00
Akira Hatanaka cd9b74a599 [mips] Add definitions of micromips shift instructions. 
Patch by Zoran Jovanovic.

llvm-svn: 180238
 2013-04-25 01:11:15 +00:00
Akira Hatanaka be6a818fd4 [mips] First patch which adds support for micromips. 
This patch adds support for recoded (meaning assembly-language compatible to
standard mips32) arithmetic 32-bit instructions.

Patch by Zoran Jovanovic.

llvm-svn: 179873
 2013-04-19 19:03:11 +00:00