2a81dd4a3c
First chunk of MachineInstr bundle support.
...
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs
llvm-svn: 145975
2011-12-06 22:12:01 +00:00
1f5c5aa209
Tidy up. Fix naming convention stuff for some internal functions.
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llvm-svn: 145974
2011-12-06 22:07:02 +00:00
ac35a4d0f7
use space star instead of star space
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llvm-svn: 145944
2011-12-06 17:34:16 +00:00
9aa6137d97
add missing point at the end of sentences
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llvm-svn: 145943
2011-12-06 17:34:11 +00:00
9dff9f4c41
ARM NEON VEXT aliases for data type suffices.
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llvm-svn: 145726
2011-12-02 23:34:39 +00:00
4393d6bd05
TableGen: fix CMake build s'more
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Oops, missed another missing file from r145629.
llvm-svn: 145636
2011-12-01 21:53:39 +00:00
08ebdc1e71
Add a deterministic finite automaton based packetizer for VLIW architectures
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llvm-svn: 145629
2011-12-01 21:10:21 +00:00
8eeb353071
Replace an assert() with an actual diagnostic.
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llvm-svn: 145535
2011-11-30 23:16:25 +00:00
3ecf976ca9
ARM parsing for VLD1 two register all lanes, no writeback.
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llvm-svn: 145504
2011-11-30 18:21:25 +00:00
f09b1c46cf
llvm_unreachable() is not for user diagnostics....
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llvm-svn: 145465
2011-11-30 01:15:55 +00:00
cd6f5e757c
ARM parsing aliases for VLD1 single register all lanes.
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llvm-svn: 145464
2011-11-30 01:09:44 +00:00
539d0a8a09
build/CMake: Finish removal of add_llvm_library_dependencies.
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llvm-svn: 145420
2011-11-29 19:25:30 +00:00
0e5bae7191
lit/TestRunner.py: Try to catch ERROR_FILE_NOT_FOUND, too.
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Thanks to Francois, to let me know.
llvm-svn: 145381
2011-11-29 06:40:50 +00:00
b103fbf005
Install llvmCore to /usr/local. <rdar://problem/10390708>
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llvm-svn: 145378
2011-11-29 06:11:56 +00:00
4128db91c2
llvmbuild/CMake: Update CMake output fragment to include explicit library
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dependency information.
llvm-svn: 145328
2011-11-29 00:06:50 +00:00
957cc212bb
Support a 'final' release candidate tag.
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llvm-svn: 145243
2011-11-28 11:45:10 +00:00
a0d652e71b
lit/TestRunner.py: Use RemoveForce().
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llvm-svn: 145223
2011-11-28 01:55:08 +00:00
57fc5adca0
lit/TestRunner.py: [Win32] Introduce WinWaitReleased(f), to wait for file handles to be released by children.
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When wait() has finished, opened handles (especially writing stdout to file) might not be released immediately.
To wait for released, poll to attempt renaming.
llvm-svn: 145222
2011-11-28 01:55:01 +00:00
75ffc5fbb5
Remove some unnecessary filtering checks from X86 disassembler table build.
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llvm-svn: 144986
2011-11-19 05:48:20 +00:00
52f71220d5
llvm-build: Attempt to work around a CMake Makefile generator bug that doesn't
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properly quote strings when writing the CMakeFiles/Makefile.cmake output file
(which lists the dependencies). This shows up when using CMake + MSYS Makefile
generator.
llvm-svn: 144873
2011-11-17 01:19:53 +00:00
ca2f78a95b
Rename MVT::untyped to MVT::Untyped to match similar nomenclature.
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llvm-svn: 144747
2011-11-16 01:02:57 +00:00
7ca4b6eb5c
Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
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integer variants. rdar://10437054
llvm-svn: 144608
2011-11-15 02:12:34 +00:00
29cdcda80d
ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.
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rdar://10435076
llvm-svn: 144606
2011-11-15 01:46:57 +00:00
7b03fbd25c
Tidy up. Formatting.
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llvm-svn: 144598
2011-11-15 01:05:12 +00:00
415ecbc34a
LLVMBuild: Add info for gtest.
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llvm-svn: 144445
2011-11-12 02:11:04 +00:00
2f39f72703
LLVMBuild: Alphabetize required_libraries lists.
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llvm-svn: 144416
2011-11-11 22:59:23 +00:00
f258ad81c0
llvm-build: Add --configure-target-def-file option.
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- Can be used to generate the substitution values we currently use for the various target related .def files.
llvm-svn: 144345
2011-11-11 00:24:00 +00:00
6d617b48c7
LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler.
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llvm-svn: 144344
2011-11-11 00:23:56 +00:00
807c6e4e5f
build/Make & CMake: Pass the appropriate --native-target and --enable-targets
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options to llvm-build, so the all-targets etc. components are defined properly.
llvm-svn: 144255
2011-11-10 01:16:48 +00:00
233c9304a8
llvm-build: Add --native-target and --enable-targets options, and add logic to
...
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
- We still require these components to be in the project (currently in
lib/Target) so that we have a place to document them and hopefully make it
more obvious that they are "magic".
llvm-svn: 144253
2011-11-10 00:50:07 +00:00
79fa1e8891
llvm-build: Split out the validation logic.
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llvm-svn: 144252
2011-11-10 00:49:58 +00:00
82219ad4dc
llvm-build: Add an explicit component type to represent targets.
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- Gives us a place to hang target specific metadata (like whether the target has a JIT).
llvm-svn: 144250
2011-11-10 00:49:51 +00:00
c83a459937
llvm-build: Tidy up options.
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llvm-svn: 144249
2011-11-10 00:49:42 +00:00
133ccfcc22
Remove this from the CMake build since I erased the file.
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llvm-svn: 144245
2011-11-10 00:07:22 +00:00
efc349af6c
Remove the old-style ARM disassembler, which is no longer used.
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llvm-svn: 144243
2011-11-09 23:56:06 +00:00
f01f1b5cb9
More AVX2 instructions and their intrinsics.
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llvm-svn: 143895
2011-11-06 23:04:08 +00:00
0edba5c989
utils/llvm-build: Ensure output directory exists for tools which write various fragments.
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llvm-svn: 143782
2011-11-05 04:07:49 +00:00
9057a3de5a
utils/llvm-build: Add trivial quoting of slashes for CMake fragment.
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llvm-svn: 143781
2011-11-05 04:07:43 +00:00
b814ee46e8
llvm-build: Quote colons in target names, in an attempt to make msys happy.
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llvm-svn: 143745
2011-11-04 23:40:11 +00:00
e9733850be
llvm-build: Add initial --write-cmake-fragment option.
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llvm-svn: 143744
2011-11-04 23:10:37 +00:00
269532de25
Build llvmCore with RTTI enabled. <rdar://problem/10395761>
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llvm-svn: 143714
2011-11-04 17:57:13 +00:00
9ef81066ad
utils: Rename the "llvmbuild" script to llvm-compilers-check.
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llvm-svn: 143673
2011-11-04 01:09:02 +00:00
ab3b1804fe
llvm-build: Add initial code for --write-make-fragment.
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llvm-svn: 143661
2011-11-03 22:46:19 +00:00
9f01a0db7d
utils: Remove (way) old nightly test scripts, I don't think anyone uses them and LNT has way better tools than this.
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llvm-svn: 143655
2011-11-03 21:03:53 +00:00
3fa708098a
llvm-build: Avoid followlinks keyword argument to os.walk.
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- llvm-build should now be Python2.4 compatible as best I know.
llvm-svn: 143641
2011-11-03 19:45:52 +00:00
bf9bba47a1
build: Add initial cut at LLVMBuild.txt files.
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llvm-svn: 143634
2011-11-03 18:53:17 +00:00
453146e569
llvm-build: Update --write-llvmbuild to write out a standard LLVM style file
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header.
llvm-svn: 143629
2011-11-03 17:56:31 +00:00
445e8f9d35
llvm-build: Add "--write-library-table" option for generating the C++ library
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dependency table used by llvm-config.
llvm-svn: 143628
2011-11-03 17:56:28 +00:00
dbbb258666
llvm-build: Add --write-llvmbuild option, which writes out the component tree.
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- Useful for migrating or auto-upgrading the format schema.
llvm-svn: 143626
2011-11-03 17:56:21 +00:00
f45369d7e8
llvm-build: Add --print-tree command line option.
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llvm-svn: 143625
2011-11-03 17:56:18 +00:00
4897255255
llvm-build: Fill in some details w.r.t. component's parents.
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llvm-svn: 143624
2011-11-03 17:56:16 +00:00
8844e3c0b2
llvm-build: Validate information on the loaded components and form the topological ordering among them (as well as validating that there are no cycles).
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- Currently we require that all references between components (except the parent relation) fit into a DAG -- this could be relaxed later if it ever proves to be useful.
llvm-svn: 143623
2011-11-03 17:56:12 +00:00
84fc5ce7af
llvm-build: Fill in more of component parsing to be more strict and
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differentiate between strings and lists.
llvm-svn: 143622
2011-11-03 17:56:10 +00:00
dd3fb562c4
llvm-build: Sketch code to load LLVMBuild.txt files.
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llvm-svn: 143621
2011-11-03 17:56:06 +00:00
01b0588b42
build: Stub out llvm-build utility tool.
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llvm-svn: 143620
2011-11-03 17:56:03 +00:00
39bf89b382
The TableGen parts of the CMake build are seriously broken. This fixes
...
one aspect of them by having them use the (annoying, if not broken)
proper library dependency model for adding the LLVMTableGen library as
a dependency. This could manifest as a link order issue in the presence
of separate LLVM / Clang source builds with CMake and a linker that
really cares about such things.
Also, add the Support dependency to llvm-tblgen itself so that it
doesn't rely on TableGen's transitive Support dependency. A parallel
change for clang-tblgen will be forthcoming.
llvm-svn: 143531
2011-11-02 05:03:06 +00:00
800f223b12
Rename show-diagnostics to something less ambiguous.
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llvm-svn: 143525
2011-11-02 00:44:16 +00:00
f525e37c5d
Do a relative path ln command instead of an absolute path one. Some people strangely enough have different directory layouts...
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llvm-svn: 143302
2011-10-29 23:49:52 +00:00
d1f1b79b52
Allow InstAlias's to use immediate matcher patterns that xform the value.
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For example,
On ARM, "mov r3, #-3" is an alias for "mvn r3, #2", so we want to use a
matcher pattern that handles the bitwise negation when mapping to t2MVNi.
llvm-svn: 143233
2011-10-28 22:32:53 +00:00
6acb14818d
Allow register classes to match a containing class in InstAliases.
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If the register class in the source alias is a subclass of the register class
of the actual instruction, the alias can still match OK since the constraints
are strictly a subset of what the instruction can actually handle.
llvm-svn: 143200
2011-10-28 16:43:40 +00:00
4c9fca99c9
Remove the Alpha backend.
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llvm-svn: 143164
2011-10-27 22:56:32 +00:00
3628c64546
Delete dead code. Nothing ever instantiates this.
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llvm-svn: 143153
2011-10-27 21:59:17 +00:00
e800a9cb70
lit: Drop some unneeded code from example tests.
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- Also, cleanup site.exp files in example tests.
llvm-svn: 143141
2011-10-27 20:59:19 +00:00
b43c36f391
Remove the Blackfin backend.
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llvm-svn: 142880
2011-10-25 00:05:42 +00:00
dfc96aea90
Remove the SystemZ backend.
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llvm-svn: 142878
2011-10-24 23:48:32 +00:00
522b56d9d8
Add options to enable each individual level for the show-diagnostics tool.
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rdar://9683410
llvm-svn: 142856
2011-10-24 21:56:50 +00:00
addcfcac5c
Rename the script to indicate that this is for the TEST=simple tests.
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llvm-svn: 142764
2011-10-23 20:14:06 +00:00
e10675a39d
Resurrect the 'find regressions for the TEST=nightly tests' script.
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llvm-svn: 142763
2011-10-23 20:13:14 +00:00
980d59832a
Add X86 RORX instruction
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llvm-svn: 142741
2011-10-23 07:34:00 +00:00
0d6d098841
Move various generated tables into read-only memory, fixing up const correctness along the way.
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llvm-svn: 142726
2011-10-22 16:50:00 +00:00
118b38cbf1
Assembly parsing for 2-register sequential variant of VLD2.
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llvm-svn: 142691
2011-10-21 22:21:10 +00:00
846bcff7c7
Assembly parsing for 4-register variant of VLD1.
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llvm-svn: 142682
2011-10-21 20:35:01 +00:00
c4360fe575
Assembly parsing for 3-register variant of VLD1.
...
llvm-svn: 142675
2011-10-21 20:02:19 +00:00
2f2e3c4737
ARM VLD parsing and encoding.
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Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
2011-10-21 18:54:25 +00:00
12a16dbcb0
Ensure timestamps are not embedded into files when doing a release build.
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llvm-svn: 142647
2011-10-21 09:47:14 +00:00
7e9a7c4a7f
Modify the script to output the regressions and passes into categories. My Python-fu could use some improving...
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llvm-svn: 142643
2011-10-21 06:58:01 +00:00
d1bb644171
Check for divide by zero.
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llvm-svn: 142640
2011-10-21 06:26:01 +00:00
f105192ad5
Also compare the built dragonegg objects between phases 2 and 3.
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llvm-svn: 142608
2011-10-20 20:14:18 +00:00
9341b50c07
Reset the system compiler each time we start a new flavour. Otherwise
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the last compiler built for the previous flavour is used for the next,
for example the Debug clang compiler was being used for the initial build
of the Release LLVM. Flavors should be independent of each other. This
especially matters if the compiler built for the previous flavour doesn't
actually work!
llvm-svn: 142607
2011-10-20 20:10:58 +00:00
2efb4dd0cb
Add support for testing dragonegg. This is disabled by default.
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In fact this commit is not intended to change anything unless you
use one of the new command line flags.
llvm-svn: 142577
2011-10-20 11:13:04 +00:00
6966b4c2b2
Revamp the script to handle the 'TEST=simple' output.
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llvm-svn: 142559
2011-10-20 00:45:46 +00:00
a96c00bf47
Duncan pointed out that sometimes CC and CXX are used to specify the compiler. Also that the configure script takes care of finding an appropriate compiler if one's not specified.
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llvm-svn: 142489
2011-10-19 09:47:00 +00:00
f96a5bc15b
Use bash instead.
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llvm-svn: 142486
2011-10-19 09:25:49 +00:00
cfe8232d23
Make changes so that this runs on FreeBSD.
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llvm-svn: 142482
2011-10-19 08:42:07 +00:00
c39977d01b
Adding dependencies to allow -DBUILD_SHARED_LIBS=true to complete.
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llvm-svn: 142464
2011-10-19 00:13:13 +00:00
ad47cfcef9
ARM VTBL (one register) assembly parsing and encoding.
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llvm-svn: 142441
2011-10-18 23:02:30 +00:00
06ac75c8e3
Don't exit just because some early commands fail. Use the -k flag when running the checks.
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llvm-svn: 142369
2011-10-18 17:27:12 +00:00
e4454e0de2
ARM assembly parsing and encoding for VMOV.i64.
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llvm-svn: 142356
2011-10-18 16:18:11 +00:00
8211c051ca
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
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llvm-svn: 142321
2011-10-18 00:22:00 +00:00
cda32ae372
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
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llvm-svn: 142303
2011-10-17 23:09:09 +00:00
741cd73aab
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
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NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
llvm-svn: 142293
2011-10-17 22:26:03 +00:00
a5748e22e2
Forgot to add the project name to the 'svn ls' command.
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llvm-svn: 142282
2011-10-17 21:45:07 +00:00
6bf79084c3
Add message to svn mkdir command.
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llvm-svn: 142280
2011-10-17 21:42:29 +00:00
b7d9ee707d
Fix unused variable warning in the rare circumstance that we have no feature-dependent instructions.
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llvm-svn: 142193
2011-10-17 16:56:47 +00:00
77dfde0ba3
Pick low-hanging MatchEntry shrinkage fruit.
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Shaves 200k off Release-Asserts clang binaries on i386.
llvm-svn: 142191
2011-10-17 16:18:09 +00:00
f95c94e9a6
Don't download and compile compiler-rt, libcxx, and libcxxabi by default.
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llvm-svn: 142185
2011-10-17 08:41:20 +00:00
7b7d077c29
Update to disable asserts. Build a phase 3 compiler, and compare phase 2 files against phase 3.
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llvm-svn: 142173
2011-10-17 04:46:54 +00:00
9aa3943d9e
Overhaul the 'test-release' script.
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This removes support for building llvm-gcc. It will eventually add support for
building other projects.
llvm-svn: 142165
2011-10-16 22:44:08 +00:00
ef22c60abd
Update the tree before applying patch.
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llvm-svn: 142155
2011-10-16 20:59:25 +00:00
96fa597828
Add X86 PEXTR and PDEP instructions.
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llvm-svn: 142141
2011-10-16 16:50:08 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
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llvm-svn: 142122
2011-10-16 07:55:05 +00:00
0ae8d4d738
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
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llvm-svn: 142117
2011-10-16 07:05:40 +00:00
03b80a4027
Make SMDiagnostic a little more sane. Instead of passing around note/warning/error as a
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string, pass it around as an enum.
llvm-svn: 142107
2011-10-16 05:43:57 +00:00
a3a0681083
Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance
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the X86 asmparser to produce ranges in the one case that was annoying me, for example:
test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
^~~~~~~
It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use
ranges where appropriate if someone is interested.
llvm-svn: 142106
2011-10-16 04:47:35 +00:00
25ea4e5ad3
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
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llvm-svn: 142105
2011-10-16 03:51:13 +00:00
6b8fe982e0
Add a helper script to create branches and tag release candidates.
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llvm-svn: 142098
2011-10-16 02:03:18 +00:00
90f98e704d
Add a script that helps merge changes into a release branch.
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llvm-svn: 142097
2011-10-16 01:54:03 +00:00
27ad12539d
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
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llvm-svn: 142082
2011-10-15 20:46:47 +00:00
1dafb035c6
Fix threads/jobs Calculation
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Pass the correct jobs and threads information to the builder.
We were underutilizing the number of jobs and threads specified
by the user.
llvm-svn: 141977
2011-10-14 19:12:37 +00:00
327c643ec2
Add Helpful Messages
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Bit just a bit more verbose about what's going on. Print options
to make to aid debugging.
llvm-svn: 141976
2011-10-14 19:12:35 +00:00
0907a61acb
Add Option to Skip Install
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Add a --no-install option to skip installing components. This
speeds up the develop/test cycle.
llvm-svn: 141975
2011-10-14 19:12:34 +00:00
d42442d646
Add Option to Skip gcc Build
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And a --no-gcc option to skip dragonegg and gcc builds.
This greatly speeds up the develop/test cycle.
llvm-svn: 141974
2011-10-14 19:12:33 +00:00
965de2c197
Add X86 ANDN instruction. Including instruction selection.
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llvm-svn: 141947
2011-10-14 07:06:56 +00:00
d9444d455e
Ban rematerializable instructions with side effects.
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TableGen infers unmodeled side effects on instructions without a
pattern. Fix some instruction definitions where that was overlooked.
Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.
llvm-svn: 141929
2011-10-14 01:00:49 +00:00
483995875f
ARM parsing and encoding for the <option> form of LDC/STC instructions.
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llvm-svn: 141786
2011-10-12 17:34:41 +00:00
6878b1f233
Remove extra semicolon.
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llvm-svn: 141699
2011-10-11 19:53:40 +00:00
a697852386
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
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llvm-svn: 141642
2011-10-11 04:34:23 +00:00
a1ac0dab2d
Emit full ED initializers even for pseudo-instructions.
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This should unbreak the picky buildbots.
llvm-svn: 141575
2011-10-10 20:15:49 +00:00
b253f490c3
Insert dummy ED table entries for pseudo-instructions.
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The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.
Add a test case for xorps which has a very high opcode that exposes this
problem.
llvm-svn: 141562
2011-10-10 18:30:16 +00:00
d0637bfc68
ARM NEON assembly parsing and encoding for VDUP(scalar).
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llvm-svn: 141446
2011-10-07 23:56:00 +00:00
33f619971f
Remove Multidefs
...
Multidefs are a bit unwieldy and incomplete. Remove them in favor of
another mechanism, probably for loops.
Revert "Make Test More Thorough"
Revert "Fix a typo."
Revert "Vim Support for Multidefs"
Revert "Emacs Support for Multidefs"
Revert "Document Multidefs"
Revert "Add a Multidef Test"
Revert "Update Test for Multidefs"
Revert "Process Multidefs"
Revert "Parser Multidef Support"
Revert "Lexer Support for Multidefs"
Revert "Add Multidef Data Structures"
llvm-svn: 141378
2011-10-07 18:25:05 +00:00
5aebebe18d
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
...
llvm-svn: 141353
2011-10-07 05:35:38 +00:00
51eaba7a54
Remove the Clang tblgen backends from LLVM.
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llvm-svn: 141293
2011-10-06 13:21:42 +00:00
23eb468b1f
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
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llvm-svn: 141274
2011-10-06 06:44:41 +00:00
fb3d935649
Build system infrastructure for multiple tblgens.
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llvm-svn: 141266
2011-10-06 01:51:51 +00:00
6e429a16fd
Remove the TRI::getSubRegisterRegClass() hook.
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This restores my karma after I added TRI::getSubClassWithSubReg().
Register constraints are applied 'backwards'. Starting from the
register class required by an instruction operand, the correct question
is: 'How can I constrain the super-register register class so all its
sub-registers satisfy the instruction constraint?' The
getMatchingSuperRegClass() hook answers that.
We never need to go 'forwards': Starting from a super-register register
class, what register class are the sub-registers in? The
getSubRegisterRegClass() hook did that.
llvm-svn: 141258
2011-10-06 00:08:27 +00:00
4fff1e2f5e
Vim Support for Multidefs
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Add vim highlighting support for multidefs.
llvm-svn: 141238
2011-10-05 22:42:52 +00:00
5d835cc5a0
Emacs Support for Multidefs
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Add Emacs font-lock keyword support for multidefs.
llvm-svn: 141237
2011-10-05 22:42:51 +00:00
3a541b046a
Add TRI::getSubClassWithSubReg(RC, Idx) function.
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This function is used to constrain a register class to a sub-class that
supports the given sub-register index.
For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.
The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.
The version provided by TableGen is usually adequate, but targets can
override.
llvm-svn: 141142
2011-10-05 00:35:49 +00:00
b1147c4660
Properly use const_iterator.
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This should unbreak the Windows build.
llvm-svn: 141105
2011-10-04 20:18:39 +00:00
03efe84d0a
Teach TableGen to infer missing register classes.
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The set of register classes should be closed under sub-register
operations and intersections. That will allow the register allocator to
model combinations of constraints accurately.
This patch implements the easiest form of register class inference: For
every register class, and for every sub-register SubIdx, the subset of
registers in RC that have a SubIdx sub-register should also be a register
class.
This does create some new register classes for the targets in the tree:
ARM gets a new QQQQPR_with_ssub_0. This class was omitted from the .td
file on purpose because it only has two registers. InstrEmitter and
RegisterCoalescer have safeguards against selecting too small register
classes, so it is harmless.
PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32
sub-register of LR8. I think that might be an omission?
X86 puts RIP in the GR64 class, and since that register doesn't have
8-bit sub-registers, we get:
GR64_with_sub_8bit
GR64_TC_with_sub_8bit
GR64_NOREX_with_sub_8bit
GR64_TC_with_sub_8bit_hi
The various CodeGen classes have already been fixed so adding new
register classes should not affect compile time.
llvm-svn: 141084
2011-10-04 15:28:49 +00:00
331534e5bb
TableGen: Store all allocation orders together.
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There is no need to keep the primary order separate.
llvm-svn: 141082
2011-10-04 15:28:44 +00:00
bd92dc608d
TableGen: Privatize CodeGenRegisterClass::TheDef and Name.
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When TableGen starts creating its own register classes, the synthesized
classes won't have a Record reference. All register classes must have a
name, though.
llvm-svn: 141081
2011-10-04 15:28:08 +00:00
54dd16240c
TableGen: Don't add synthetic Records to the RecordKeeper.
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The RecordKeeper could be shared by multiple target instances, causing
duplicate record errors.
llvm-svn: 141080
2011-10-04 15:27:53 +00:00
f18c896337
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
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llvm-svn: 141065
2011-10-04 06:30:42 +00:00
74e5a2a712
Remove last references to hotpatch.
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llvm-svn: 141057
2011-10-04 03:08:43 +00:00
7f6f12405d
Find the strip tool that works with the specified SDKROOT. rdar://10165908
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llvm-svn: 141013
2011-10-03 18:48:16 +00:00
56ff34f7c5
Fix typo in r140954.
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llvm-svn: 140962
2011-10-02 04:54:26 +00:00
d07a59f288
Fix disassembling of INVEPT and INVVPID to take operands
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llvm-svn: 140955
2011-10-01 21:20:14 +00:00
88cb33e0d4
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
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llvm-svn: 140954
2011-10-01 19:54:56 +00:00
84c287e33c
Move TableGen's parser and entry point into a library
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This is the first step towards splitting LLVM and Clang's tblgen executables.
llvm-svn: 140951
2011-10-01 16:41:13 +00:00
ce29158bc4
Subtarget getFeatureBits() returns a uint64_t, not unsigned.
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llvm-svn: 140928
2011-10-01 02:47:54 +00:00
6417395d67
Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().
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All the sub-class bit vectors are computed when first creating the
register bank.
llvm-svn: 140905
2011-09-30 23:47:05 +00:00
237dceff90
Store sub-class lists as a bit vector.
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This uses less memory and it reduces the complexity of sub-class
operations:
- hasSubClassEq() and friends become O(1) instead of O(N).
- getCommonSubClass() becomes O(N) instead of O(N^2).
In the future, TableGen will infer register classes. This makes it
cheap to add them.
llvm-svn: 140898
2011-09-30 22:19:07 +00:00
8153f6c39f
Extract a slightly more general BitVector printer.
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This one can also print 32-bit groups.
llvm-svn: 140897
2011-09-30 22:18:54 +00:00
b15fad9df4
Compute lists of super-classes in CodeGenRegisterClass.
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Use these lists instead of computing them on the fly in
RegisterInfoEmitter.
llvm-svn: 140895
2011-09-30 22:18:45 +00:00
74ce80f34e
Implement VarListElementInit:: resolveListElementReference
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Implement VarListElementInit:: resolveListElementReference so that
lists of lists can be indexed.
llvm-svn: 140882
2011-09-30 20:59:49 +00:00
2c024b2d6a
Precompute a bit vector of register sub-classes.
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llvm-svn: 140827
2011-09-30 00:10:40 +00:00
c0fc173da0
Order register classes topologically.
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All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.
This will be used to simplify some sub-class operations.
llvm-svn: 140826
2011-09-30 00:10:36 +00:00
19be2ab320
Switch to ArrayRef<CodeGenRegisterClass*>.
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This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.
llvm-svn: 140816
2011-09-29 22:28:37 +00:00
9c248ac29e
tblgen/ClangDiagnostics: Add support for split default warning "no-werror" and
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"show-in-system-header" bits, which I will be adding in Clang shortly.
llvm-svn: 140741
2011-09-29 00:29:04 +00:00
02bb7573fb
Remove old hack for compiling with gcc-4.0.
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llvm-svn: 140573
2011-09-26 22:30:57 +00:00
f01e2de5e6
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
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llvm-svn: 140560
2011-09-26 21:06:22 +00:00
df977fedb6
Add target hook for pseudo instruction expansion.
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Many targets use pseudo instructions to help register allocation. Like
the COPY instruction, these pseudos can be expanded after register
allocation. The early expansion can make life easier for PEI and the
post-ra scheduler.
This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.
llvm-svn: 140472
2011-09-25 19:21:35 +00:00
526adabe87
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
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llvm-svn: 140370
2011-09-23 06:57:25 +00:00
52363bdbeb
Restore hasPostISelHook tblgen flag.
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No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.
llvm-svn: 140160
2011-09-20 18:22:31 +00:00
8586e62d91
ARM isel bug fix for adds/subs operands.
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Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
llvm-svn: 140134
2011-09-20 03:17:40 +00:00
69c02e9476
Remove more of llvmc and dependencies.
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llvm-svn: 140121
2011-09-20 00:34:27 +00:00
05541f45f3
Thumb2 assembly parsing and encoding for TBB/TBH.
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llvm-svn: 140078
2011-09-19 22:21:13 +00:00
39db48d0d4
Better Error Reporting
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Report missing template arguments more helpfully by supplying the name
of the missing argument in the error message.
llvm-svn: 140034
2011-09-19 18:26:07 +00:00
2266c007e3
Migrate this to use clang by default as well.
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llvm-svn: 139936
2011-09-16 20:36:22 +00:00
73ec21f301
We now look for clang, then llvm-gcc, then gcc as our compiler. We don't need
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this anymore.
llvm-svn: 139935
2011-09-16 20:36:20 +00:00
ee8157cb41
Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.
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llvm-svn: 139691
2011-09-14 06:41:26 +00:00
07863d80b7
[tablegen] In ClangAttrEmitter.cpp handle SourceLocation arguments to attributes.
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llvm-svn: 139617
2011-09-13 18:41:43 +00:00
3171285edf
In ClangAttrEmitter.cpp emit code that allows attributes to keep their source range.
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llvm-svn: 139598
2011-09-13 16:05:43 +00:00
e98d8a5c84
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
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llvm-svn: 139588
2011-09-13 06:54:58 +00:00
a88e356017
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
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llvm-svn: 139485
2011-09-11 21:41:45 +00:00
a948cb9058
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
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llvm-svn: 139484
2011-09-11 20:23:20 +00:00
8726d330f1
Update Clang AST attribute reader tblgen generation to match with ASTReader change
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llvm-svn: 139414
2011-09-09 21:37:29 +00:00
a05627ebaf
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
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llvm-svn: 139381
2011-09-09 18:37:27 +00:00
e776b580c1
Make sure to handle the case where emitPredicateMatch returns false. Noticed by inspection.
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llvm-svn: 139317
2011-09-08 21:00:31 +00:00
f774712782
Added LateParsed property to TableGen attributes.
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This patch was written by DeLesley Hutchins.
llvm-svn: 139300
2011-09-08 17:40:49 +00:00
21d293a37f
Fix warning on windows; use of comparison with bool argument.
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llvm-svn: 139286
2011-09-08 08:12:01 +00:00
43674ad44d
Fix a use of freed string contents.
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Speculatively try to fix our windows testers with a patch I found on the internet.
llvm-svn: 139279
2011-09-08 05:25:49 +00:00
61abca6daa
whitespace
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llvm-svn: 139278
2011-09-08 05:23:14 +00:00
2392c53e73
Thumb2 assembly parsing and encoding for LDRBT.
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llvm-svn: 139267
2011-09-07 23:39:14 +00:00
5bfa8bab06
Thumb2 parsing and encoding for LDR(immediate).
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The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.
llvm-svn: 139254
2011-09-07 20:58:57 +00:00
8067df9503
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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llvm-svn: 139250
2011-09-07 19:42:28 +00:00
3d76f312b2
Dependency should be on the output file name, not the dependency file
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name.
llvm-svn: 139220
2011-09-07 02:12:03 +00:00
09ade9bb8b
valgrind: Suppress glibc's optiized strcasecmp harder.
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llvm-svn: 139084
2011-09-03 17:59:31 +00:00
67ba2403e8
Attempt to silence known valgrind errors.
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llvm-svn: 139048
2011-09-02 22:59:34 +00:00
09d153eb12
Make RecordVal Name an Init
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Store a RecordVal's name as an Init to allow class-qualified Record
members to reference Records that have Init names. We'll use this to
provide more programmability in how we name defs and their associated
members.
llvm-svn: 139031
2011-09-02 20:12:07 +00:00
54e09b4799
Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
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llvm-svn: 139014
2011-09-02 18:03:03 +00:00
94ce535647
Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
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llvm-svn: 138997
2011-09-02 04:17:54 +00:00
db4ce60328
Fix up r137380 based on post-commit review by Jim Grosbach.
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llvm-svn: 138948
2011-09-01 18:02:14 +00:00
93f3082118
lit: Normalize pathsep slashes also on %T.
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On Python-w32 with mingw msys bash, %T was replaced to "x:\foo\bar...". msys bash cannot handle DOSish paths.
llvm-svn: 138852
2011-08-31 03:56:17 +00:00
e6fba77971
Follow up to r138791.
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Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.
llvm-svn: 138810
2011-08-30 19:09:48 +00:00
d74c19449e
Lit option for ignoring stderr output.
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This is useful for testing a build a temporarily hand instrumented
build.
Patch by arrowdodger!
llvm-svn: 138804
2011-08-30 17:42:33 +00:00
4f2fba1108
Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
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llvm-svn: 138795
2011-08-30 07:09:35 +00:00
7e2489a7c9
Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217
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llvm-svn: 138771
2011-08-29 22:06:28 +00:00
d22f9b395b
Reverted r138652, valgrind doesn't understand obj:*/tblgen.
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llvm-svn: 138703
2011-08-27 06:17:30 +00:00
b205c029a4
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
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llvm-svn: 138675
2011-08-26 23:32:08 +00:00
28dc5abd05
valgrind: Always suppress tblgen leaks.
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I'll clean up the rest of the XFAIL: vg_leak lines if this works.
llvm-svn: 138652
2011-08-26 20:41:20 +00:00
37e94d06ba
lit: Add %T as a replacement for the output directory
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llvm-svn: 138640
2011-08-26 19:05:18 +00:00
76e3e0b554
Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
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llvm-svn: 138552
2011-08-25 07:42:00 +00:00
0a0b3071df
Thumb parsing and encoding support for ADD SP instructions.
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Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
llvm-svn: 138488
2011-08-24 21:22:15 +00:00
1b8457a84c
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
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Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
llvm-svn: 138445
2011-08-24 17:46:13 +00:00
ffa5a909b4
Thread safety: Adding in an option for variadic expr* array of arguments
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llvm-svn: 138351
2011-08-23 18:49:23 +00:00
c50ea3beaf
Fix fpimmm->fpimm typo.
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Patch by Micah Villmow!
llvm-svn: 138330
2011-08-23 15:42:35 +00:00
9f1761c3e0
utils/lit/lit/TestingConfig.py: Pass TEMP and TMP to tests on Win32 hosts.
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Win32 GetTempPath() tends to pick up %WINDIR% when neither TEMP nor TMP was found. %WINDIR% should not be treated writable on recent Windows OS.
llvm-svn: 138192
2011-08-20 05:44:58 +00:00
Evan Cheng