Commit Graph

6 Commits

Author SHA1 Message Date
Hsiangkai Wang c274384cff [NFC][RISCV] Update test cases through update_cc_test_checks.py. 2021-10-03 15:44:06 +08:00
Craig Topper cfe3b0005f [RISCV] Reorder masked builtin operands. Use clang_builtin_alias for all overloaded vector builtins.
This patch makes the builtin operand order match the C operand order
for all intrinsics. With this we can use clang_builtin_alias for
all overloaded intrinsics.

This should further reduce the test time for vector intrinsics.

Differential Revision: https://reviews.llvm.org/D101700
2021-05-02 10:57:25 -07:00
Hsiangkai Wang b358a2be52 [RISCV] Remove riscv32 test cases for vector intrinsics. 2021-04-28 15:54:25 +08:00
Hsiangkai Wang d8fa5ef6a2 [RISCV] Apply clang_builtin_alias to overloaded builtins.
We only apply `clang_builtin_alias` to non-masked builtins.
Masked builtins could not use `clang_builtin_alias` because the
operand order is different between overloaded intrinsics and builtins.

A bunch of test cases need to be updated.

Differential Revision: https://reviews.llvm.org/D100658
2021-04-25 18:12:19 +08:00
Zakk Chen ca9e52f67c [RISCV][Clang] Drop the assembly tests for RVV intrinsics.
We had verified the correctness of all intrinsics in downstream, so
dropping the assembly tests to decrease the check-clang time.
It would remove 1/3 of the RUN lines.

https://reviews.llvm.org/D99151#2654154 mentions why we need to have
the ASM tests before.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D100617
2021-04-16 09:30:12 -07:00
Zakk Chen 66c05609e0 [RISCV][Clang] Add some RVV Integer intrinsic functions.
1. Rename RVVBinBuiltin to RVVOutputOp1Builtin because it is not related
to the number of operand.
2. Add RVV Integer instuctions which use RVVOutputOp1Builtin.

Reviewed By: craig.topper

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Differential Revision: https://reviews.llvm.org/D99524
2021-04-06 03:07:36 -07:00