Commit Graph

11 Commits

Author SHA1 Message Date
Hsiangkai Wang 5158cfef8b [RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR.
Previous patch only reverts C builtins for tail policy. In order to keep
LLVM IR intact, add the `ta` argument in vector builtins.
2021-10-13 19:41:49 +08:00
Hsiangkai Wang 7ccd31c900 Revert "[RISCV] (2/2) Add the tail policy argument to builtins/intrinsics."
This reverts commit 7afa61e718.
2021-10-13 19:41:48 +08:00
Hsiangkai Wang ff3ed78304 Revert "[RISCV] Define _m intrinsics as builtins, instead of macros."
This reverts commit 97f0c63783.

As discussed in https://reviews.llvm.org/D110684, it increased the
compile time and the binary size of clang more than 1%. I reverted
this patch first to think about a better way to do it.
2021-10-13 12:21:51 +08:00
Hsiangkai Wang 97f0c63783 [RISCV] Define _m intrinsics as builtins, instead of macros.
In the original design, we levarage _mt intrinsics to define macros for
_m intrinsics. Such as,

```
__builtin_rvv_vadd_vv_i8m1_mt((vbool8_t)(op0), (vint8m1_t)(op1), (vint8m1_t)(op2), (vint8m1_t)(op3), (size_t)(op4), (size_t)VE_TAIL_AGNOSTIC)
```

However, we could not define generic interface for mask intrinsics any
more due to clang_builtin_alias only accepts clang builtins as its
argument.

In the example,

```
 __rvv_overloaded
 __attribute__((clang_builtin_alias(__builtin_rvv_vadd_vv_i8m1_mt)))
  vint8m1_t vadd(vbool8_t op0, vint8m1_t op1, vint8m1_t op2, vint8m1_t
  op3, size_t op4, size_t op5);
```

op5 is the tail policy argument. When users want to use vadd generic
interface for masked vector add, they need to specify tail policy in the
previous design. In this patch, we define _m intrinsics as clang
builtins to solve the problem.

Differential Revision: https://reviews.llvm.org/D110684
2021-10-12 10:47:55 +08:00
Hsiangkai Wang c274384cff [NFC][RISCV] Update test cases through update_cc_test_checks.py. 2021-10-03 15:44:06 +08:00
Hsiangkai Wang 7afa61e718 [RISCV] (2/2) Add the tail policy argument to builtins/intrinsics.
Add the tail policy argument to Clang builtins. There
are two policies for tail elements. Tail agnostic means users do not
care about the values in the tail elements and tail undisturbed means
the values in the tail elements need to be kept after the operation. In
order to let users control the tail policy, we add an additional
argument at the end of the argument list.

For unmasked operations, we have no maskedoff and the tail policy is
always tail agnostic. If users want to keep tail elements under unmasked
operations, they could use all one mask in the masked operations to do
it. So, we only add the additional argument for masked operations for
most cases. There are exceptions listed below.

In this patch, we do not handle the following cases to reduce the
complexity of the patch. There could be two separate patches for them.

Use dest argument to control tail policy
vmerge.vvm/vmerge.vxm/vmerge.vim (add _t builtins with additional dest
argument)
vfmerge.vfm (add _t builtins with additional dest argument)
vmv.v.v (add _t builtins with additional dest argument)
vmv.v.x (add _t builtins with additional dest argument)
vmv.v.i (add _t builtins with additional dest argument)
vfmv.v.f (add _t builtins with additional dest argument)
vadc.vvm/vadc.vxm/vadc.vim (add _t builtins with additional dest
argument)
vsbc.vvm/vsbc.vxm (add _t builtins with additional dest argument)

Always has tail argument for masked/unmasked intrinsics
Vector Single-Width Integer Multiply-Add Instructions (add _t and _mt
builtins)
Vector Widening Integer Multiply-Add Instructions (add _t and _mt
builtins)
Vector Single-Width Floating-Point Fused Multiply-Add Instructions (add
_t and _mt builtins)
Vector Widening Floating-Point Fused Multiply-Add Instructions (add _t
and _mt builtins)
Vector Reduction Operations (add _t and _mt builtins)
Vector Slideup Instructions (add _t and _mt builtins)
Vector Slidedown Instructions (add _t and _mt builtins)

Discussion: https://github.com/riscv/rvv-intrinsic-doc/pull/101

Differential Revision: https://reviews.llvm.org/D109322
2021-09-24 17:09:50 +08:00
Craig Topper cfe3b0005f [RISCV] Reorder masked builtin operands. Use clang_builtin_alias for all overloaded vector builtins.
This patch makes the builtin operand order match the C operand order
for all intrinsics. With this we can use clang_builtin_alias for
all overloaded intrinsics.

This should further reduce the test time for vector intrinsics.

Differential Revision: https://reviews.llvm.org/D101700
2021-05-02 10:57:25 -07:00
Hsiangkai Wang b358a2be52 [RISCV] Remove riscv32 test cases for vector intrinsics. 2021-04-28 15:54:25 +08:00
Hsiangkai Wang d8fa5ef6a2 [RISCV] Apply clang_builtin_alias to overloaded builtins.
We only apply `clang_builtin_alias` to non-masked builtins.
Masked builtins could not use `clang_builtin_alias` because the
operand order is different between overloaded intrinsics and builtins.

A bunch of test cases need to be updated.

Differential Revision: https://reviews.llvm.org/D100658
2021-04-25 18:12:19 +08:00
Zakk Chen ca9e52f67c [RISCV][Clang] Drop the assembly tests for RVV intrinsics.
We had verified the correctness of all intrinsics in downstream, so
dropping the assembly tests to decrease the check-clang time.
It would remove 1/3 of the RUN lines.

https://reviews.llvm.org/D99151#2654154 mentions why we need to have
the ASM tests before.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D100617
2021-04-16 09:30:12 -07:00
Zakk Chen 66c05609e0 [RISCV][Clang] Add some RVV Integer intrinsic functions.
1. Rename RVVBinBuiltin to RVVOutputOp1Builtin because it is not related
to the number of operand.
2. Add RVV Integer instuctions which use RVVOutputOp1Builtin.

Reviewed By: craig.topper

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Differential Revision: https://reviews.llvm.org/D99524
2021-04-06 03:07:36 -07:00