4 Commits

Author	SHA1	Message	Date
Dylan McKay	6fddb53685	[AVR] Reorder the CHECK lines in directmem.ll to match current trunk ... In r346432 ("[DAGCombine] Improve alias analysis for chain of independent stores"), the order of ldi/sts blocks changed. The new IR is equivalent to the old IR. This patch updates the test to fix the test suite. llvm-svn: 346565	2018-11-09 23:17:59 +00:00
Dylan McKay	f2c83670f7	[AVR] Fix the build after setting alignment to 1 in r314179 ... Changing all types to be byte-aligned broke a small number of tests. llvm-svn: 314183	2017-09-26 02:07:54 +00:00
Dylan McKay	7838104382	[AVR] Fix the test suite ... A bunch of tests failed because memory operations have been reordered. I am unsure which commit changed this behaviour as the AVR build was failing at that point with an unrelated error. This commit just reoders some of the CHECK lines in some tests to suit current llc output. llvm-svn: 300682	2017-04-19 12:02:52 +00:00
Dylan McKay	a789f40002	[AVR] Add the pseudo instruction expansion pass ... Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162	2016-11-16 21:58:04 +00:00