Commit Graph

70184 Commits

Author SHA1 Message Date
Daniel Sanders 6c97d979df [mips][mips64r6] prefx is not available on MIPS32r6/MIPS64r6
Summary: We haven't implemented this instruction so we only add a test case.

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D4004

llvm-svn: 210779
2014-06-12 13:51:27 +00:00
Daniel Sanders 557889affd [mips][mips64r6] 80 col corrections that should have been in r210777.
llvm-svn: 210778
2014-06-12 13:42:04 +00:00
Daniel Sanders 0fa6041625 [mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6
Summary:
c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to
dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's
(like the GPR comparisons).

mov[fntz] have been replaced by seleqz and selnez. These instructions
conditionally zero a register based on a bool in a GPR. The results can
then be or'd together to act as a select without, for example, requiring a third
register read port.

mov[fntz].[ds] have been replaced with sel.[ds]

MIPS64r6 currently generates unnecessary sign-extensions for most selects.
This is because the result of a SETCC is currently an i32. Bits 32-63 are
undefined in i32 and the behaviour of seleqz/selnez would otherwise depend
on undefined bits. Later, we will fix this by making the result of SETCC an
i64 on MIPS64 targets.

Depends on D3958

Reviewers: jkolek, vmedic, zoran.jovanovic

Reviewed By: vmedic, zoran.jovanovic

Differential Revision: http://reviews.llvm.org/D4003

llvm-svn: 210777
2014-06-12 13:39:06 +00:00
Daniel Sanders 559dd851b6 [mips][mips64r6] jalx is not available on MIPS32r6/MIPS64r6
Summary: Depends on D3957

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3958

llvm-svn: 210775
2014-06-12 12:58:20 +00:00
Zoran Jovanovic b9c07f3b86 [mips][mips64r6] Add R_MIPS_PC19_S2
Differential Revision: http://reviews.llvm.org/D3866

llvm-svn: 210773
2014-06-12 12:40:00 +00:00
Rafael Espindola ed6882b835 Don't import make_error_code into the llvm namespace.
llvm-svn: 210772
2014-06-12 11:58:49 +00:00
Daniel Sanders 1f6f0f4b54 [mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64
Summary:
To make this work for both AFGR64 and FGR64 register sets, I've had to make the
instruction definition consistent with the white lie (that it reads the lower
32-bits of the register) when they are generated by expandBuildPairF64().

Corrected the definition of hasMips32r2() and hasMips64r2() to include
MIPS32r6 and MIPS64r6.

Depends on D3956

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3957

llvm-svn: 210771
2014-06-12 11:55:58 +00:00
Zoran Jovanovic 28a0ca0759 [mips][mips64r6] Add bgec and bgeuc instructions
Differential Revision: http://reviews.llvm.org/D4017

llvm-svn: 210770
2014-06-12 11:47:44 +00:00
Andrea Di Biagio 2dd3b3b674 [X86] Teach how to dump the name of target node RDTSCP_DAG.
When I originally added node RDTSCP_DAG (r207127) I forgot to add
a string name for it in method 'getTargetNodeName'.

No functional change intended.

llvm-svn: 210769
2014-06-12 11:37:24 +00:00
Daniel Sanders ded02af45e [mips][mips64r6] madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not available on MIPS32r6/MIPS64r6
Summary:
This patch updates both the assembler and the code generator.

MIPS32r6/MIPS64r6 replaces them with maddf.[ds] and msubf.[ds] which are fused
multiply-add/sub operations. We don't emit these yet, this patch only prevents the removed instructions from being emitted.

Depends on D3955

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3956

llvm-svn: 210763
2014-06-12 11:04:18 +00:00
Daniel Sanders 826f8b3d0c [mips][mips64r6] madd/maddu/msub/msubu are not available on MIPS32r6/MIPS64r6
Summary:
This patch disables madd/maddu/msub/msubu in both the assembler and code
generator.

Depends on D3896

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3955

llvm-svn: 210762
2014-06-12 10:54:16 +00:00
Andrea Di Biagio 972ff97f8c [X86] Teach how to combine AVX and AVX2 horizontal binop on packed 256-bit vectors.
This patch adds target combine rules to match:
 - [AVX] Horizontal add/sub of packed single/double precision floating point
   values from 256-bit vectors;
 - [AVX2] Horizontal add/sub of packed integer values from 256-bit vectors.

llvm-svn: 210761
2014-06-12 10:53:48 +00:00
Daniel Sanders 308181eaa0 [mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
  div $1, $2
  mflo $3
is now:
  div $3, $1, $2

This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.

Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.

MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D3896

llvm-svn: 210760
2014-06-12 10:44:10 +00:00
Matt Arsenault 2c81994f92 R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*
There is not such thing as a 0-data ds instruction, and the data
operand needs to be a vgpr set to something meaningful.

llvm-svn: 210756
2014-06-12 08:21:54 +00:00
Juergen Ributzka 04558dc77a [FastISel] Add support for the stackmap intrinsic.
This implements target-independent FastISel lowering for the stackmap intrinsic.

llvm-svn: 210742
2014-06-12 03:29:26 +00:00
Rafael Espindola e5ec53ba96 Prefix generic_category with std::.
Sorry I missed these before.

llvm-svn: 210740
2014-06-12 02:52:22 +00:00
Rafael Espindola 7e577f73ee Don't put generic_category in the llvm namespace.
llvm-svn: 210737
2014-06-12 02:00:39 +00:00
Bob Wilson 2f7cc01895 Fix verifier for GlobalAliases to avoid recursing into global initializers.
The verifier follows GlobalAlias operands so that it can detect cycles of
alias definitions. It was doing this in a way that caused it to also recurse
through initializers for the GlobalValue aliasees, and it would fail when
an initializer refers to a global that is a declaration and not a definition.
This patch causes it to stop recursing when it hits a global definition.
<rdar://problem/17277451>

llvm-svn: 210734
2014-06-12 01:46:54 +00:00
Rafael Espindola 25188c95de Don't import error_category into the llvm namespace.
llvm-svn: 210733
2014-06-12 01:45:43 +00:00
Rafael Espindola acc5d7c911 Don't import error_condition into the llvm namespace.
llvm-svn: 210731
2014-06-12 01:29:42 +00:00
Rafael Espindola 116f21c4dd Used mapWindowsError. I missed these in the initial transition.
llvm-svn: 210729
2014-06-12 01:25:33 +00:00
Rafael Espindola adb73e6fb9 Try to fix the mingw build.
* MingW needs mapWindowsError.
* MingW is missing some entries in std::errc, but we don't use them.

llvm-svn: 210725
2014-06-12 00:24:39 +00:00
Zachary Turner 39c422da57 Do not register and de-register PassRegistrationListeners during
construction and destruction.

PassRegistrationListener is intended for use as a generic listener.
In some cases, PassRegistrationListener-derived classes were being
created, and automatically registered and de-registered in static
constructors and destructors.  Since ManagedStatics are destroyed
prior to program shutdown, this leads to errors where an attempt is
made to access a ManagedStatic that has already been destroyed.

Reviewed by: rnk, dblaikie

Differential Revision: http://reviews.llvm.org/D4106

llvm-svn: 210724
2014-06-12 00:16:36 +00:00
Eli Bendersky 899bef099f Teach LoopUnrollPass to respect loop unrolling hints in metadata.
See http://reviews.llvm.org/D4090 for more details.

The Clang change that produces this metadata was committed in r210667

Patch by Mark Heffernan.

llvm-svn: 210721
2014-06-11 23:15:35 +00:00
Juergen Ributzka 272b570a80 [FastISel][X86] Add support for the sqrt intrinsic.
llvm-svn: 210720
2014-06-11 23:11:02 +00:00
Juergen Ributzka fbaa3db909 [FastIsel][X86] Add support for lowering the first 8 floating-point arguments.
llvm-svn: 210719
2014-06-11 23:10:58 +00:00
Zachary Turner a997d928fc Don't acquire the mutex during the destructor of PassRegistry.
This destructor is run as part of static program termination, and
so all ManagedStatics (including this lock) will have been
destroyed by llvm_shutdown.  Furthermore, if there is actually
a race condition during static program termination, then we are
just hiding a bug somewhere else, because other threads should
not be running at this point.

llvm-svn: 210717
2014-06-11 23:03:31 +00:00
Rafael Espindola da70bfd826 Implement get_magic with generic tools and inline it.
llvm-svn: 210716
2014-06-11 22:53:00 +00:00
Rafael Espindola 70fbe6f80e Remove unused has_magic.
This will allow inlining get_magic, which should in turn fix one of the mingw
build problems after the switch to std::error_code.

llvm-svn: 210712
2014-06-11 21:53:22 +00:00
Juergen Ributzka 4dc958777c [FastISel][X86] Add support for the frameaddress intrinsic.
llvm-svn: 210709
2014-06-11 21:44:44 +00:00
Chad Rosier 2205d4ef05 [AArch64] Basic Sched Model for Cortex-A57.
Patch by Dave Estes<cestes@codeaurora.org>
Differential Revision: http://reviews.llvm.org/D4008

llvm-svn: 210705
2014-06-11 21:06:56 +00:00
Tom Stellard 4a9cea608c R600: Set correct InstrItinClass for instructions using *Helper classes
We weren't doing this before, so all instruction using the *Helper
classes were considered for any ALU slot.

This fixes a hang in the builtin-char-clz-1.0.generated.cl piglit test.

llvm-svn: 210703
2014-06-11 20:51:42 +00:00
Tom Stellard 3fe21f8afa R600: BCNT_INT is a vector only instruction
llvm-svn: 210702
2014-06-11 20:51:39 +00:00
Jim Grosbach 7a930bf9ef ARM: honor hex immediate formatting for ldr/str i12 offsets.
Previously we would always print the offset as decimal, regardless of
the formatting requested. Now we use the formatImm() helper so the value
is printed as the client (LLDB in the motivating example) requested.

Before:
ldr.w r8, [sp, #180] @ always

After:
ldr.w r8, [sp, #0xb4] @ when printing hex immediates
ldr.w r8, [sp, #0180] @ when printing decimal immediates

rdar://17237103

llvm-svn: 210701
2014-06-11 20:26:45 +00:00
Matt Arsenault 2acc7a4570 R600/SI: Fix bitcast between v2i32 and f64
This is the same problem fixed in r210664 for more types.

The test passes without this fix. For some reason
I'm only hitting this when creating selects lowered
to v2i32 selects.

llvm-svn: 210692
2014-06-11 19:31:13 +00:00
Rafael Espindola 5c4f829424 Use std::error_code instead of llvm::error_code.
The idea of this patch is to turn llvm/Support/system_error.h into a
transitional header that just brings in the erorr_code api to the llvm
namespace. I will remove it shortly afterwards.

The cases where the general idea needed some tweaking:

* std::errc is a namespace in msvc, so we cannot use "using std::errc". I could
add an #ifdef, but there were not that many uses, so I just added std:: to
them in this patch.

* Template specialization had to be moved to the std namespace in this
patch set already.

* The msvc implementation of default_error_condition doesn't seem to
provide the same transformations as we need. Not too surprising since
the standard doesn't actually say what "equivalent" means. I fixed the
problem by keeping our old mapping and using it at error_code
construction time.

Despite these shortcomings I think this is still a good thing. Some reasons:

* The different implementations of system_error might improve over time.
* It removes 925 lines of code from llvm already.
* It removes 6313 bytes from the text segment of the clang binary when
it is built with gcc and 2816 bytes when building with clang and
libstdc++.

llvm-svn: 210687
2014-06-11 19:05:50 +00:00
Chad Rosier 829cc2e7d9 Fix assert comments in Instruction.cpp.
llvm-svn: 210684
2014-06-11 18:26:29 +00:00
Matt Arsenault 845438204f R600/SI: Update place using old subtarget predicate
llvm-svn: 210683
2014-06-11 18:11:34 +00:00
Matt Arsenault caa0ec2851 R600/SI: Add common 64-bit LDS atomics
llvm-svn: 210680
2014-06-11 18:08:54 +00:00
Matt Arsenault 1f10c5e2c9 R600/SI: Add instruction definitions for 64-bit LDS atomics
llvm-svn: 210679
2014-06-11 18:08:50 +00:00
Matt Arsenault c793e1d9dc R600/SI: Add 32-bit LDS atomic cmpxchg
llvm-svn: 210678
2014-06-11 18:08:48 +00:00
Matt Arsenault 9e874541ac R600/SI: Use LDS atomic inc / dec
llvm-svn: 210677
2014-06-11 18:08:45 +00:00
Matt Arsenault 0e69e8128c R600/SI: Add other LDS atomic operations
llvm-svn: 210676
2014-06-11 18:08:42 +00:00
Matt Arsenault 8c6613d2bf R600/SI: Add instruction definitions for more LDS ops
llvm-svn: 210675
2014-06-11 18:08:39 +00:00
Matt Arsenault 7ddcd83d49 R600/SI: Fix backwards names for local atomic instructions.
The manual lists them as *_RTN_U32, not *_U32_RTN, which is more
consistent with how every other sized instruction is named.

llvm-svn: 210674
2014-06-11 18:08:37 +00:00
Matt Arsenault 725741004c R600/SI: Refactor local atomics.
Use patterns that will also match the immediate offset to
match the normal read / writes.

llvm-svn: 210673
2014-06-11 18:08:34 +00:00
Matt Arsenault 364a6747aa R600/SI: Use v_cvt_f32_ubyte* instructions
This eliminates extra extract instructions when loading an i8 vector to
a float vector.

llvm-svn: 210666
2014-06-11 17:50:44 +00:00
Matt Arsenault 064c206d23 R600/SI: Fix selection failure on scalar_to_vector
There seem to be only 2 places that produce these,
and it's kind of tricky to hit them.

Also fixes failure to bitcast between i64 and v2f32,
although this for some reason wasn't actually broken in the
simple bitcast testcase, but did in the scalar_to_vector one.

llvm-svn: 210664
2014-06-11 17:40:32 +00:00
Tim Northover 4dc9eaa6ba X86: add stringy name for X86ISD::LCMPXCHG16_DAG
I don't know what "target specific node #383" is, and I don't want to
have to.

llvm-svn: 210663
2014-06-11 17:04:08 +00:00
Eric Christopher 4fdc765b13 Revert r210613 to conform to coding standards.
Thanks Duncan for noticing.

llvm-svn: 210662
2014-06-11 16:59:33 +00:00