Even though we may not know the value of the shifter operand, it's possible we know the shifter operand is non-zero. This can allow us to infer more known bits - for example:
%1 = load %p !range {1, 5}
%2 = shl %q, %1
We don't know %1, but we do know that it is nonzero so %2[0] is known zero, and importantly %2 is known non-zero.
Calling isKnownNonZero is nontrivially expensive so use an Optional to run it lazily and cache its result.
llvm-svn: 251294
Summary:
Replace (const SCEVAddRecExpr *) with cast<SCEVAddRecExpr>.
Rename SCEVApplyRewriter to SCEVLoopAddRecRewriter (which is a more
appropriate name) since the description is "takes a scalar evolution
expression and applies the Map (Loop -> SCEV) to all AddRecExprs."
Subscribers: llvm-commits, sanjoy
Differential Revision: http://reviews.llvm.org/D14065
llvm-svn: 251292
Vectorization of memory instruction (Load/Store) is possible when the pointer is coming from GEP. The GEP analysis allows to estimate the profit.
In some cases we have a "bitcast" between GEP and memory instruction.
I added code that skips the "bitcast".
http://reviews.llvm.org/D13886
llvm-svn: 251291
Summary:
This patch adds support for using the "interrupt" attribute on Mips
for interrupt handling functions. At this time only mips32r2+ with the
o32 ABI with the static relocation model is supported. Unsupported
configurations will be rejected
Patch by Simon Dardis (+ clang-format & some trivial changes to follow the
LLVM coding standards by me).
Reviewers: mpf, dsanders
Subscribers: dsanders, vkalintiris, llvm-commits
Differential Revision: http://reviews.llvm.org/D10768
llvm-svn: 251286
Summary:
Add a SCEVRewriteVisitor class which contains the common
visiting patterns used when rewriting SCEVs.
SCEVParameterRewriter and SCEVApplyRewriter now inherit
from SCEVRewriteVisitor (and are therefore much simpler).
Reviewers: anemet, mzolotukhin, sanjoy
Subscribers: rengolin, llvm-commits, sanjoy
Differential Revision: http://reviews.llvm.org/D13242
llvm-svn: 251283
Summary:
InstCombine tries to transform GEP(PHI(GEP1, GEP2, ..)) into GEP(GEP(PHI(...))
when possible. However, this may leave the old PHI node around. Even if we
do end up folding the GEPs, having an extra PHI node might not be beneficial.
This change makes the transformation more conservative. We now only do this if
the PHI has only one use, and can therefore be removed after the transformation.
Reviewers: jmolloy, majnemer
Subscribers: mcrosier, mssimpso, llvm-commits
Differential Revision: http://reviews.llvm.org/D13887
llvm-svn: 251281
the module pointer type passed in by the user.
The previous ownership scheme, where the user pointer was always moved into a
std::shared_ptr, breaks if the user passes in a raw pointer.
Discovered while working on the Orc C API, which should be landing shortly.
I expect to include a test-case with that.
llvm-svn: 251273
GNU as and Darwin give the various binary operators different
precedence. LLVM's MC supported the Darwin semantics but not the GNU
semantics.
This fixes PR25311.
llvm-svn: 251271
We didn't validate that the .word directive was given a sane value,
leading to crashes when we attempt to write out the object file.
Instead, perform some validation and issue a diagnostic pointing at the
start of the diagnostic.
llvm-svn: 251270
Instead of playing around with dominance to verify if the possible expansion of
a scop region is indeed a single entry single exit region, we now distinguish
two cases. In case we only append a basic block, all edges entering this basic
block need to have come from within the region that is expanded. In case we join
two regions, the source basic blocks of the edges that end at the entry node of
the region that is appended most be part of either the original region or the
region that is appended.
This change will be tested through Polly.
This fixes llvm.org/PR25242
llvm-svn: 251267
Windows has two different mangling specifiers. `x` is used on x86 for the `_`
UserLabelPrefix. Others use `w` for the no UserLabelPrefix.
llvm-svn: 251260
When the target does not support these intrinsics they should be converted to a chain of scalar load or store operations.
If the mask is not constant, the scalarizer will build a chain of conditional basic blocks.
I added isLegalMaskedGather() isLegalMaskedScatter() APIs.
Differential Revision: http://reviews.llvm.org/D13722
llvm-svn: 251237
When using the MCU psABI, compiler-generated library calls should pass
some parameters in-register. However, since inreg marking for x86 is currently
done by the front end, it will not be applied to backend-generated calls.
This is a workaround for PR3997, which describes a similar issue for -mregparm.
Differential Revision: http://reviews.llvm.org/D13977
llvm-svn: 251223
This adds support for the i?86-*-elfiamcu triple, which indicates the IAMCU psABI is used.
Differential Revision: http://reviews.llvm.org/D13977
llvm-svn: 251222
I think it's fine to keep this fields around in terms of overhead,
I wasn't able to measure any substantial regression while running the
test suite, but, in case this causes some regression I'm ready to revert
and work on an alternative solution.
This was tested building with clang/gcc both in Debug and Release mode
and passes the test-suite.
llvm-svn: 251209
James Molloy