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4 Commits

Author SHA1 Message Date
Nirav Dave d1b3f09faa [X86][DAG] Switch X86 Target to post-legalized store merge 
Move store merge to happen after intrinsic lowering to allow lowered
stores to be merged.

Some regressions due in MergeConsecutiveStores to missing
insert_subvector that are addressed in follow up patch.

Reviewers: craig.topper, efriedma, RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D34559

llvm-svn: 310710
 2017-08-11 13:21:35 +00:00
Simon Pilgrim 19cee0d56c [X86][AVX] Regenerate i256 bitcasted store test 
Check on slow/fast unaligned memory targets

llvm-svn: 306138
 2017-06-23 18:34:56 +00:00
Mandeep Singh Grang da99e33ae3 [llvm] Remove redundant --check-prefix=CHECK from tests 
Reviewers: MatzeB, mcrosier, rengolin

Differential Revision: https://reviews.llvm.org/D25894

llvm-svn: 285003
 2016-10-24 18:57:55 +00:00
Michael Liao 460fc46e0f Enhance type legalization on bitcast from vector to integer 
- Find a legal vector type before casting and extracting element from it.
- As the new vector type may have more than 2 elements, build the final
  hi/lo pair by BFS pairing them from bottom to top.

llvm-svn: 163830
 2012-09-13 19:58:21 +00:00