Commit Graph

28 Commits

Author SHA1 Message Date
Gabor Ballabas cebcb3b52f Allow case-insensitive values for -march for ARM in line with GCC.
GCC allows case-insensitive values for -mcpu, -march and -mtune options.
This patch implements the same behaviour for the -march option for ARM.

llvm-svn: 239527
2015-06-11 12:29:56 +00:00
Gabor Ballabas 208826cc0f Allow case-insensitive values for -mcpu for ARM
GCC allows case-insensitive values for -mcpu, -march and -mtune options.
This patch implements the same behaviour for the -mcpu option.

llvm-svn: 239059
2015-06-04 17:56:32 +00:00
John Brawn a8f8234f91 [ARM] Adjust -march checking
getCanonicalArchName can return an empty string for an architecture
that is well-formed but meaningless. Use parseArch to determine if
it's actually valid or not.

Differential Revision: http://reviews.llvm.org/D10120

llvm-svn: 238553
2015-05-29 13:10:44 +00:00
Ranjeet Singh b90541519e [ARM] Be less specific about the error message expected.
Differential Revision: http://reviews.llvm.org/D10087

llvm-svn: 238436
2015-05-28 15:55:34 +00:00
Ranjeet Singh 5b30b0aaae Test commit.
llvm-svn: 238220
2015-05-26 17:30:35 +00:00
John Brawn 94fd963315 [ARM] Restructure cpu handling in the driver to mostly use the triple
Using the target cpu to determine some behaviour is sprinkled in
several places in the driver, but in almost all the information that
is needed can be found in the triple. Restructure things so that the
triple is used, and the cpu is only used if the exact cpu name is
needed.

Also add a check that the -mcpu argument is valid, and correct the
-march argument checking so that it handles -march=native correctly. I
would have liked to move these checks into the computation of the
triple, but the triple is calculated several times in several places
and that would lead to multiple error messages for the same thing.

Differential Revision: http://reviews.llvm.org/D9879

llvm-svn: 237894
2015-05-21 12:19:49 +00:00
Vladimir Sukharev c6dab75bd4 [ARM] Add v8.1a architecture
Add support for ARMv8.1a architecture. 

Briefly it is described on http://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-a-architecture-and-its-ongoing-development

Reviewers: 	jmolloy, rengolin

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D8799

llvm-svn: 237349
2015-05-14 08:25:18 +00:00
Renato Golin 4045f66175 Revert "Allow case-insensitive values for -mcpu for ARM and AArch64"
This reverts commit r236859, as it broke multiple builds. I'll investigate
and reapply when safe.

llvm-svn: 236869
2015-05-08 15:44:36 +00:00
Renato Golin 9e36fb4c18 Allow case-insensitive values for -mcpu for ARM and AArch64
GCC allows case-insensitive values for -mcpu, -march and -mtune options.
This patch implements the same behaviour for the -mcpu option.

Patch by Gabor Ballabas.

llvm-svn: 236859
2015-05-08 14:50:32 +00:00
John Brawn a95c1a8315 [ARM] Give an error on invalid -march values
llvm::Triple::getARMCPUForArch now returns nullptr for invalid -march
values, instead of silently translating it to arm7tdmi. Use this to
give an error message, which is consistent with how gcc behaves.

Differential Revision: http://reviews.llvm.org/D9602

llvm-svn: 236846
2015-05-08 12:52:18 +00:00
Javed Absar 879d18b843 [ARM] add support for Cortex-R4/R4F
Adds ARM Cortex-R4 and R4F support and tests in Clang. Though Cortex-R4
support was present, the support for hwdiv in thumb-mode was not defined
or tested properly. This has also been added.

llvm-svn: 234488
2015-04-09 14:12:10 +00:00
Renato Golin e11531f7ea [ARM] Add support for ARMV6K subtarget (Clang)
ARMv6K is another layer between ARMV6 and ARMV6T2. This is the Clang
side of the changes.

ARMV6 family LLVM implementation.

+-------------------------------------+
| ARMV6                               |
+----------------+--------------------+
| ARMV6M (thumb) | ARMV6K (arm,thumb) | <- From ARMV6K and ARMV6M processors
+----------------+--------------------+    have support for hint instructions
| ARMV6T2 (arm,thumb,thumb2)          |    (SEV/WFE/WFI/NOP/YIELD). They can
+-------------------------------------+    be either real or default to NOP.
| ARMV7 (arm,thumb,thumb2)            |    The two processors also use
+-------------------------------------+    different encoding for them.

Patch by Vinicius Tinti.

llvm-svn: 232469
2015-03-17 11:55:43 +00:00
Bradley Smith d86d670e85 [ARM] Add missing M/R class CPUs
Add some of the missing M and R class Cortex CPUs, namely:

Cortex-M0+ (called Cortex-M0plus for GCC compatibility)
Cortex-M1
SC000
SC300
Cortex-R5

llvm-svn: 229661
2015-02-18 10:34:48 +00:00
Bradley Smith 1a178c5663 [ARM] Add tests for armv6s[-]m being an alias to armv6[-]m
llvm-svn: 228697
2015-02-10 15:16:49 +00:00
Renato Golin 84545d7a5c Teaches the Clang driver to accept Cortex-A72
A previous commit added Cortex-A72 to LLVM, this teaches Clang to
accept it as well.

Patch by Ranjeet Singh.

llvm-svn: 228141
2015-02-04 13:31:56 +00:00
Artyom Skrobov 6701327758 D5823: Fix typo in Clang test arm-cortex-cpus.c; patch by Gabor Ballabas!
llvm-svn: 220201
2014-10-20 13:48:19 +00:00
Renato Golin 5886bc35b0 Adds support for the Cortex-A17 processor to Clang
Patch by Matthew Wahab.

llvm-svn: 219607
2014-10-13 10:22:48 +00:00
Oliver Stannard bfd3ea32b7 [ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP
The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and
FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be
modeled using the same target feature, and all double-precision
operations are already disabled by the fp-only-sp target features.

llvm-svn: 218748
2014-10-01 09:03:02 +00:00
Christian Pirker 918d1097a1 Simplify getARMCPUForMArch() and make it more consistent
llvm-svn: 207956
2014-05-05 08:48:18 +00:00
Christian Pirker ba289f0c64 ARM: Add command line option to select big or little endian
llvm-svn: 205967
2014-04-10 13:59:32 +00:00
Christian Pirker f01cd6f57b Add ARM big endian Target (armeb, thumbeb)
Reviewed at http://llvm-reviews.chandlerc.com/D3096

llvm-svn: 205008
2014-03-28 14:40:46 +00:00
Reid Kleckner 2c35b3b029 Revert "Cortex-M3 and Cortex-M4 should not enable hwdiv-arm"
This reverts commit r200233.

The test required a registered ARM target, it was testing LLVM's
generated assembly, and it should have been an IRGen test.

llvm-svn: 200242
2014-01-27 19:26:39 +00:00
Artyom Skrobov 1c66c3a7f2 Cortex-M3 and Cortex-M4 should not enable hwdiv-arm
llvm-svn: 200233
2014-01-27 18:44:25 +00:00
Bernard Ogden 8af41b5a21 Make thumb the default instruction set for v7m and v7em
llvm-svn: 197152
2013-12-12 13:27:04 +00:00
Bernard Ogden 178d0dc95b Fix -mthumb resetting of target cpu
Passing -mthumb with no explicit CPU on the command line
resulted in target CPU changing from the architecture
default to arm7tdmi. Now it does not.

llvm-svn: 197151
2013-12-12 13:26:59 +00:00
Bernard Ogden 021d7dacd0 Teach clang driver about Cortex-A53 and Cortex-A57.
Adds some Cortex-A53 strings where they were missing before.
Cortex-A57 is entirely new to clang.

Doesn't touch code only used by Darwin, in consequence of which
one of the A53 lines has been removed.

Change-Id: I5edb58f6eae93947334787e26a8772c736de6483
llvm-svn: 193364
2013-10-24 18:32:36 +00:00
Renato Golin 1a04f22356 Add more Cortex CPUs and tests
llvm-svn: 190703
2013-09-13 17:02:54 +00:00
Bob Wilson 743bf67caf Add ARM v6m, v7m, and v7em architectures for Cortex-M series processors.
<rdar://problem/11314476>

llvm-svn: 176458
2013-03-04 22:37:49 +00:00