3d345b11c8
[mips][sched] Split IIFmoveC1 into II_M[FT]C1, II_M[FT]HC1, II_DM[FT]C1
...
No functional change since the InstrItinData's have been duplicated.
llvm-svn: 199748
2014-01-21 15:03:52 +00:00
bf8aa22902
[mips][sched] Split IIFStore into II_S[WD]C1, and II_S[WDU]XC1
...
No functional change since the InstrItinData's have been duplicated.
llvm-svn: 199747
2014-01-21 14:50:20 +00:00
7741274534
[mips][sched] Split IIFLoad into II_L[WD]C1, and II_L[WDU]XC1
...
No functional change since the InstrItinData's have been duplicated.
llvm-svn: 199743
2014-01-21 13:59:56 +00:00
3424067527
[mips][sched] Renamed II_FsqrtSingle and II_FsqrtDouble to II_SQRT_S and II_SQRT_D respectively
...
No functional change
llvm-svn: 199741
2014-01-21 13:36:45 +00:00
072f60f0dc
[mips][sched] Renamed II_FdivSingle and II_FdivDouble to II_DIV_S and II_DIV_D respectively
...
No functional change
llvm-svn: 199738
2014-01-21 13:22:08 +00:00
2ce72b061c
[mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, II_NMADD_D, and II_NMSUB_S
...
No functional change since the InstrItinData's have been duplicated.
llvm-svn: 199737
2014-01-21 13:07:31 +00:00
47b4b6dd78
[mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, II_NMADD_S, and II_NMSUB_S
...
No functional change since the InstrItinData's have been duplicated.
llvm-svn: 199734
2014-01-21 12:51:44 +00:00
4bf6078841
[mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS]
...
No functional change since the InstrItinData's have been duplicated.
llvm-svn: 199732
2014-01-21 12:38:07 +00:00
b8013baf8f
[mips][sched] Split IIFcmp into II_C_CC_[SD]
...
No functional change since the InstrItinData's have been duplicated.
llvm-svn: 199728
2014-01-21 11:42:48 +00:00
f5fb34137e
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD]
...
No functional change since the InstrItinData's have been duplicated.
llvm-svn: 199727
2014-01-21 11:28:03 +00:00
555f4c5672
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG
...
No functional change since the InstrItinData's have been duplicated.
llvm-svn: 199722
2014-01-21 10:56:23 +00:00
8876be39c7
Support for microMIPS FPU instructions 2.
...
llvm-svn: 198009
2013-12-25 10:09:27 +00:00
ce02486d16
Support for microMIPS FPU instructions 1.
...
llvm-svn: 197815
2013-12-20 15:44:08 +00:00
05bcde6d9a
This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added.
...
llvm-svn: 190780
2013-09-16 10:29:42 +00:00
6379121694
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
...
precision loads and stores as well as reg+imm double precision loads and stores.
Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.
llvm-svn: 190235
2013-09-07 00:52:30 +00:00
9bfa2e2e7f
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
...
Also, fix predicates.
llvm-svn: 189432
2013-08-28 00:55:15 +00:00
9a1fb6b9fc
[mips] Add support for mfhc1 and mthc1.
...
llvm-svn: 188848
2013-08-20 23:47:25 +00:00
8dd951bc9f
[mips] Remove predicates that were incorrectly or unnecessarily added.
...
llvm-svn: 188845
2013-08-20 23:21:55 +00:00
14e31a2fe7
[mips] Define register class FGRH32 for the high half of the 64-bit floating
...
point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.
llvm-svn: 188842
2013-08-20 22:58:56 +00:00
6781fc1648
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of
...
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.
llvm-svn: 188830
2013-08-20 21:08:22 +00:00
00fcf2e169
[mips] Rename accumulator register classes and FP register operands.
...
llvm-svn: 188020
2013-08-08 21:54:26 +00:00
13e6ccf341
[mips] Rename register classes CPURegs and CPU64Regs.
...
llvm-svn: 187832
2013-08-06 23:08:38 +00:00
643b398786
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
...
llvm-svn: 187410
2013-07-30 10:12:14 +00:00
8bce21c154
[mips] Fix FP conditional move instructions to have explicit FP condition code
...
register operands.
llvm-svn: 187242
2013-07-26 20:51:20 +00:00
1fb1b8b811
[mips] Fix FP branch instructions to have explicit FP condition code register
...
operands.
llvm-svn: 187238
2013-07-26 20:13:47 +00:00
55f69b302c
[mips] Fix floating point branch, comparison, and conditional move instructions
...
to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.
No intended functionality change.
llvm-svn: 187233
2013-07-26 19:01:56 +00:00
5bcb2407a5
[mips] Delete MFC1_FT_CCR, MTC1_FT_CCR and MOVCCRToCCR.
...
No functionality change.
llvm-svn: 186642
2013-07-19 01:19:52 +00:00
64828a1f73
This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient.
...
llvm-svn: 186397
2013-07-16 10:07:14 +00:00
b34ad7860f
[mips] Add new InstrItinClasses for move from/to coprocessor instructions and
...
floating point loads and stores.
No changes in functionality.
llvm-svn: 185399
2013-07-02 00:00:02 +00:00
233dd51b13
This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser.
...
llvm-svn: 184716
2013-06-24 10:05:34 +00:00
252f54f769
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr).
...
Previously, three instructions were needed:
trunc.w.s $f0, $f2
mfc1 $4, $f0
sw $4, 0($2)
Now we need only two:
trunc.w.s $f0, $f2
swc1 $f0, 0($2)
llvm-svn: 182053
2013-05-16 21:17:15 +00:00
39d40f7baf
[mips] Fix instruction selection pattern for sint_to_fp node to avoid emitting an
...
invalid instruction sequence.
Rather than emitting an int-to-FP move instruction and an int-to-FP conversion
instruction during instruction selection, we emit a pseudo instruction which gets
expanded post-RA. Without this change, register allocation can possibly insert a
floating point register move instruction between the two instructions, which is not
valid according to the ISA manual.
mtc1 $f4, $4 # int-to-fp move instruction.
mov.s $f2, $f4 # move contents of $f4 to $f2.
cvt.s.w $f0, $f2 # int-to-fp conversion.
llvm-svn: 182042
2013-05-16 19:48:37 +00:00
21bab5badc
[mips] Fix indentation.
...
llvm-svn: 182036
2013-05-16 18:42:42 +00:00
9edae02db8
[mips] Add option -mno-ldc1-sdc1.
...
This option is used when the user wants to avoid emitting double precision FP
loads and stores. Double precision FP loads and stores are expanded to single
precision instructions after register allocation.
llvm-svn: 181718
2013-05-13 18:23:35 +00:00
b1457304cc
[mips] Define reg+imm load/store pattern templates.
...
llvm-svn: 178407
2013-03-30 02:01:48 +00:00
69fb3d11ec
[mips] Split SelectAddr, which was used to match address patterns, into two
...
functions. Set AddedComplexity to determine the order in which patterns are
matched.
This simplifies selection of floating point loads/stores.
No functionality change intended.
llvm-svn: 175300
2013-02-15 21:20:45 +00:00
28aed9ca85
[mips] Set flag neverHasSideEffects flag on some of the floating point instructions.
...
llvm-svn: 173401
2013-01-25 00:20:39 +00:00
873c724b4a
This patch tackles the problem of parsing Mips
...
register names in the standalone assembler llvm-mc.
Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.
The problem is resolved by the Mips specific AsmParser
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.
Contributer: Vladimir Medic
llvm-svn: 172284
2013-01-12 01:03:14 +00:00
b1527b7505
[mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
...
parameter.
llvm-svn: 170661
2012-12-20 04:20:09 +00:00
b2cc8a756f
[mips] Delete all floating point instruction classes that are no longer used.
...
No functionality change.
llvm-svn: 170084
2012-12-13 02:05:02 +00:00
79e1cdb00b
[mips] Modify definitions of floating point comparison instructions.
...
No functionality change.
llvm-svn: 170077
2012-12-13 01:34:09 +00:00
fd9163b74c
[mips] Modify definitions of floating point branch instructions.
...
No functionality change.
llvm-svn: 170076
2012-12-13 01:32:36 +00:00
cd3dfd238e
[mips] Modify definitions of floating point indexed load and store instructions.
...
No functionality change.
llvm-svn: 170075
2012-12-13 01:30:49 +00:00
b0d4acbc65
[mips] Modify definitions of floating point multiply-add/sub instructions.
...
No functionality change.
llvm-svn: 170073
2012-12-13 01:27:48 +00:00
92994f4846
[mips] Modify definitions of floating point load and store instructions.
...
No functionality change.
llvm-svn: 170072
2012-12-13 01:24:00 +00:00
2b75dde5fa
[mips] Modify definitions of move from/to coprocessor instructions.
...
No functionality change.
llvm-svn: 170071
2012-12-13 01:16:49 +00:00
dea8f61ae0
[mips] Modify definitions of two register operand floating point instructions.
...
No functionality change.
llvm-svn: 170069
2012-12-13 01:14:07 +00:00
29b513871a
[mips] Modify definitions of three register operand floating point instructions
...
and separate encoding information from the rest.
llvm-svn: 170066
2012-12-13 01:07:37 +00:00
84693d5606
[mips] Move classes that do not belong in MipsInstrFormats.td into
...
MipsInstrFPU.td.
llvm-svn: 170061
2012-12-13 00:49:23 +00:00
db49b39200
[mips] Set isCommutable flag in a more explicit way.
...
llvm-svn: 170060
2012-12-13 00:46:23 +00:00
Daniel Sanders