57af4ece60
update testcase.
...
llvm-svn: 77192
2009-07-27 15:52:58 +00:00
8e58bc9ed4
put normal data into .data instead of .data.rel on elf systems.
...
llvm-svn: 77116
2009-07-26 03:06:11 +00:00
397792d981
finish simplifying DarwinTargetAsmInfo::SelectSectionForGlobal
...
for now. Make the section switching directives more consistent
by not including \n and including \t for them all.
llvm-svn: 77107
2009-07-26 01:24:18 +00:00
5b42b45fb9
simplify DarwinTargetAsmInfo::SelectSectionForGlobal a bit
...
and make it more aggressive, we now put:
const int G2 __attribute__((weak)) = 42;
into the text (readonly) segment like gcc, previously we put
it into the data (readwrite) segment.
llvm-svn: 77104
2009-07-26 00:51:36 +00:00
8a37bbebfd
Add support for ARM Neon VREV instructions.
...
Patch by Anton Korzh, with some modifications from me.
llvm-svn: 77101
2009-07-26 00:39:34 +00:00
2de9510572
add the most expedient hack to fix PR4619, along with a testcase.
...
Thanks to Rafael for the great example.
llvm-svn: 77083
2009-07-25 17:57:37 +00:00
3b5791f982
I've lost my mind. PR4572 has not been fixed.
...
llvm-svn: 77031
2009-07-25 01:11:46 +00:00
f3a1fce8ae
Change Thumb2 jumptable codegen to one that uses two level jumps:
...
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2 ]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
llvm-svn: 77024
2009-07-25 00:33:29 +00:00
8c8e88bd39
Remove a duplicated test.
...
llvm-svn: 77020
2009-07-25 00:24:40 +00:00
01740ab57b
Forgot this test earlier.
...
llvm-svn: 77007
2009-07-24 22:42:45 +00:00
aee0e1f48c
Fix these tests.
...
llvm-svn: 77006
2009-07-24 22:42:22 +00:00
fae639c9ad
Move insertps tests to sse41 combo test file, convert to filecheck
...
format and add an extract/insert test.
llvm-svn: 76994
2009-07-24 19:24:26 +00:00
3990850a7d
Convert a test to FileCheck.
...
llvm-svn: 76954
2009-07-24 06:01:46 +00:00
26aff56462
Remove SectionKind::Small*. This was only used on mips, and is apparently
...
a sad mistake that is regretted. :)
llvm-svn: 76935
2009-07-24 03:11:51 +00:00
fc39e417a8
Add tests for handling of globals and tls on the XCore. These currently fail
...
but pass when run against r76652.
llvm-svn: 76923
2009-07-24 00:38:20 +00:00
17151155ed
Remove the IA-64 backend.
...
llvm-svn: 76920
2009-07-24 00:30:09 +00:00
dc99f07113
Thumb2 does not allow the use of "pc" register as part of the load / store address.
...
llvm-svn: 76909
2009-07-23 23:09:51 +00:00
d2919a1773
Fix up ARM constant island pass for Thumb2.
...
Also fixed up code to fully use the SoImm field for ADR on ARM mode.
llvm-svn: 76890
2009-07-23 18:27:47 +00:00
dc13b7c637
merge one more sse41 test into sse41.ll
...
llvm-svn: 76853
2009-07-23 04:49:39 +00:00
70d5783535
merge another sse41 test into sse41.ll
...
llvm-svn: 76852
2009-07-23 04:43:48 +00:00
08fc6e6e40
merge sse41-pmovx.ll into sse41.ll
...
llvm-svn: 76850
2009-07-23 04:39:09 +00:00
b9cdd3153c
change a test to run in filecheck style. Rename it to be a general
...
dumping ground of various SSE4.1 tests, since filecheck can reasonably
handle them all in one file. Generalize it to check x86-64 stuff as
well since it has a different ABI (a convenient way to test both the
reg and mem forms of these instructions).
llvm-svn: 76848
2009-07-23 04:33:02 +00:00
b1b77ca862
Support insertps via the intrinsic and add a couple of simple
...
testcases to make sure it's being generated.
llvm-svn: 76843
2009-07-23 02:22:41 +00:00
327cb795a1
Add test for pinsrd and pinsrb instructions.
...
llvm-svn: 76840
2009-07-23 01:58:04 +00:00
b215100c7c
Revert r75663 (and r76805), as it is causing regressions on powerpc.
...
llvm-svn: 76823
2009-07-23 00:09:46 +00:00
824ab40381
x86 isel tweak: use lea (%reg,%reg) instead of lea (,%reg,2).
...
llvm-svn: 76817
2009-07-22 23:26:55 +00:00
cdbef5f2c0
Add -march=ppc32 lines so that this test doesn't ever default to ppc64.
...
llvm-svn: 76805
2009-07-22 22:08:31 +00:00
e270d4a4dd
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
...
llvm-svn: 76803
2009-07-22 22:03:29 +00:00
c510293251
Make the grep line in this test more specific, to avoid
...
unintended matches.
llvm-svn: 76802
2009-07-22 22:02:42 +00:00
d2d52d1906
Ignore undef uses.
...
llvm-svn: 76799
2009-07-22 21:51:42 +00:00
0cf7f5d6d2
Revert commit 76707, it was breaking the llvm-gcc build
...
on linux platforms. The binutils assembler does not
recognize the "s" flag, see for example
http://sourceware.org/binutils/docs/as/Section.html
llvm-svn: 76733
2009-07-22 10:35:05 +00:00
8ebaec6b27
set the ELF "small" flag on objects that end up in .rodata.cst4 consistently,
...
updating a mips testcase to expect it.
llvm-svn: 76707
2009-07-22 00:41:56 +00:00
332a6590ae
Remove a big test case.
...
llvm-svn: 76669
2009-07-21 22:52:04 +00:00
38e88cb53f
Do not select tSXTB / tSXTH in thumb2 mode.
...
llvm-svn: 76600
2009-07-21 18:15:26 +00:00
8e55200089
convert this test to filecheck format, which is faster and avoids false matches of "st" -> "stdin"
...
llvm-svn: 76591
2009-07-21 17:36:24 +00:00
b61f9c8c8d
add a testcase for the pic16 section handling stuff.
...
llvm-svn: 76579
2009-07-21 16:48:20 +00:00
07a6ac6b29
Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past.
...
llvm-svn: 76558
2009-07-21 09:15:00 +00:00
83423aa276
remove a very large testcase for now.
...
llvm-svn: 76537
2009-07-21 06:28:36 +00:00
a7bb55ebb6
Fix a dagga combiner bug: avoid creating illegal constant.
...
Is this really a winning transformation?
fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
(srl (and x, (shl -1, c1)), (sub c1, c2))
llvm-svn: 76535
2009-07-21 05:40:15 +00:00
0d8b0cf3b8
Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1.
...
llvm-svn: 76520
2009-07-21 00:31:12 +00:00
9a47392f2e
Cross RC coalescing is now on by default.
...
llvm-svn: 76519
2009-07-21 00:22:59 +00:00
40c68ad3bb
Re-apply 75490, 75806 and 76177 with fixes and tests. Efficiency comes
...
next.
llvm-svn: 76486
2009-07-20 22:02:59 +00:00
a2b8c3f98f
Forgot this test earlier.
...
llvm-svn: 76485
2009-07-20 21:46:42 +00:00
57106d6dc0
Use TII->findCommutedOpIndices to find the commute operands (rather than guessing).
...
llvm-svn: 76472
2009-07-20 21:16:08 +00:00
027d9f93ea
Fix some sub-reg coalescing bugs where the coalescer wasn't updating the resulting interval's register class.
...
llvm-svn: 76458
2009-07-20 19:47:55 +00:00
33a3fd0b9c
Revert the addition of hasNoPointerOverflow to GEPOperator.
...
Getelementptrs that are defined to wrap are virtually useless to
optimization, and getelementptrs that are undefined on any kind
of overflow are too restrictive -- it's difficult to ensure that
all intermediate addresses are within bounds. I'm going to take
a different approach.
Remove a few optimizations that depended on this flag.
llvm-svn: 76437
2009-07-20 17:43:30 +00:00
58f9bb2ccd
implement a new magic global "llvm.compiler.used" which is like llvm.used, but
...
doesn't cause ".no_dead_strip" to be emitted on darwin.
llvm-svn: 76399
2009-07-20 06:14:25 +00:00
4e4eb0b00c
Restore AsmWriterEmitter.cpp back to 74742. The recent changes broke Thumb.
...
llvm-svn: 76398
2009-07-20 06:10:07 +00:00
aba695c7d0
Fix http://llvm.org/bugs/show_bug.cgi?id=4583
...
Inline asm instructions may have additional <imp-def,kill> register operands.
These operands are not marked with a flag like the normal asm operands, so we
must not assert that there is a flag.
llvm-svn: 76373
2009-07-19 19:09:59 +00:00
090db9b7a9
Catch more coalescing opportunities.
...
llvm-svn: 76282
2009-07-18 04:52:23 +00:00
e20cbf3068
Enable cross register class coalescing.
...
llvm-svn: 76281
2009-07-18 02:10:10 +00:00
a776067d3f
Fix pr4552. Stack slot coloring with register must take care not to generate illegal ams.
...
llvm-svn: 76258
2009-07-17 22:42:51 +00:00
18fe458103
Fix x86 inline ams 'q' constraint support. In 32-bit mode, it's just like 'Q', i.e. EAX, EDX, ECX, EBX. In 64-bit mode, it just means all the i64r registers. Yeah, that makes sense.
...
llvm-svn: 76248
2009-07-17 22:13:25 +00:00
52d436e98b
rename test.
...
llvm-svn: 76197
2009-07-17 18:05:55 +00:00
97f3f965eb
Make promotion in operation legalization for SETCC work correctly.
...
llvm-svn: 76153
2009-07-17 05:16:04 +00:00
c5df7e2dc1
Emit cross regclass register moves for thumb2.
...
Minor code duplication cleanup.
llvm-svn: 76124
2009-07-16 23:26:06 +00:00
c4148c4ec7
Assume an inline asm might be a call, so we get
...
stack alignment right when it is. This is not
ideal but conservatively correct. Adjust a test
to compensate for changed stack offset value.
gcc.apple/asm-block-57.c
llvm-svn: 76120
2009-07-16 22:34:45 +00:00
070fab8a1f
Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm operands.
...
The inline asm operands must be parsed from the first flag, you cannot assume
that an immediate operand preceeding a register use operand is the flag.
PowerPC "m" operands are represented as (flag, imm, reg) triples.
isRegTiedToDefOperand() would incorrectly interpret the imm as the flag.
llvm-svn: 76101
2009-07-16 20:58:34 +00:00
357645efad
Changed my mind. We now allow remat of instructions whose defs have subreg indices.
...
llvm-svn: 76100
2009-07-16 20:15:00 +00:00
fdd0eb4011
With recent MC changes, RIP base register is explicitly modeled. Make sure we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction.
...
llvm-svn: 76094
2009-07-16 18:44:05 +00:00
77a50bd3a8
Make xfail proper
...
llvm-svn: 76065
2009-07-16 14:53:47 +00:00
73fcd3d962
Temporary disable 16 bit bswap
...
llvm-svn: 76063
2009-07-16 14:35:57 +00:00
902facfe96
Add bswap patterns
...
llvm-svn: 76061
2009-07-16 14:34:52 +00:00
3ae30e08ef
Fix logic inversion for RI-mode address selection
...
llvm-svn: 76052
2009-07-16 14:31:14 +00:00
6c2c47ecb2
Unbreak the test
...
llvm-svn: 76051
2009-07-16 14:30:49 +00:00
4121039bef
Expand 32-bit bitconverts via memory
...
llvm-svn: 76050
2009-07-16 14:30:29 +00:00
bc2ead6ea3
Fix incomin arg stack frame offset in case we need to generate stack frame
...
llvm-svn: 76049
2009-07-16 14:29:57 +00:00
bd41c83ab0
Revert the commit, it just hides the real bug
...
llvm-svn: 76045
2009-07-16 14:28:26 +00:00
2acdac0f8e
Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension side effects
...
llvm-svn: 76035
2009-07-16 14:24:41 +00:00
b25949b0f5
Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide problems
...
llvm-svn: 76011
2009-07-16 14:18:17 +00:00
091872cb37
Implement 'large' PIC model
...
llvm-svn: 76006
2009-07-16 14:16:05 +00:00
569a94c4d0
Implement shifts properly (hopefilly - finally!)
...
llvm-svn: 76005
2009-07-16 14:15:24 +00:00
fe8df8ff61
Properly handle divides. As a bonus - implement memory versions of them.
...
llvm-svn: 76003
2009-07-16 14:14:33 +00:00
34ad780d0d
32 bit shifts have only 12 bit displacements
...
llvm-svn: 76000
2009-07-16 14:13:24 +00:00
1eb6262b4b
Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.
...
llvm-svn: 75990
2009-07-16 14:10:17 +00:00
62f8515b1c
Add support for 12 bit displacements
...
llvm-svn: 75988
2009-07-16 14:09:35 +00:00
43d33bd6d2
Emit proper lowering of load from arg stack slot
...
llvm-svn: 75986
2009-07-16 14:08:42 +00:00
a8197bb651
Implement dynamic allocas
...
llvm-svn: 75985
2009-07-16 14:08:15 +00:00
7193e2670e
Add jump tables
...
llvm-svn: 75984
2009-07-16 14:07:50 +00:00
2ff298fad0
Add rotates
...
llvm-svn: 75981
2009-07-16 14:06:49 +00:00
9362d9aa76
Add patterns for integer negate
...
llvm-svn: 75980
2009-07-16 14:06:27 +00:00
f07c7941f0
Provide proper patterns for and with imm instructions. Tune the tests accordingly.
...
llvm-svn: 75979
2009-07-16 14:06:00 +00:00
59049d9176
Add 32 bit and reg-imm and disable invalid patterns for now
...
llvm-svn: 75978
2009-07-16 14:05:32 +00:00
2d218394c6
Add z9 and z10 target processors. Mark z10-only instructions as such.
...
llvm-svn: 75977
2009-07-16 14:05:00 +00:00
d568f6dce2
Proper lower 'small' results
...
llvm-svn: 75962
2009-07-16 13:58:24 +00:00
f1bf3176c6
Completel forgot about unconditional branches
...
llvm-svn: 75961
2009-07-16 13:57:52 +00:00
15d6e8785b
Lower addresses of globals
...
llvm-svn: 75960
2009-07-16 13:57:27 +00:00
a442cdfb04
Test (incomplete) for easy muls
...
llvm-svn: 75959
2009-07-16 13:57:03 +00:00
f0d7d6ce65
Provide "wide" muls and divs/rems
...
llvm-svn: 75958
2009-07-16 13:56:42 +00:00
b04a4fa5c1
Tests for cmp / br_cc / select_cc
...
llvm-svn: 75949
2009-07-16 13:53:15 +00:00
8695a30066
Emit callee-saved regs spills / restores
...
llvm-svn: 75943
2009-07-16 13:51:12 +00:00
d694b9ff8b
Some preliminary call lowering
...
llvm-svn: 75941
2009-07-16 13:50:21 +00:00
018599fc0b
Prologue / epilogue emission
...
llvm-svn: 75940
2009-07-16 13:49:49 +00:00
09890bd434
Add simple frame index elimination
...
llvm-svn: 75939
2009-07-16 13:49:25 +00:00
5dc5629100
Provide proper test :)
...
llvm-svn: 75938
2009-07-16 13:48:59 +00:00
405833dfb6
Add address computation stuff
...
llvm-svn: 75935
2009-07-16 13:47:59 +00:00
df99232d27
Add mem-imm stores
...
llvm-svn: 75933
2009-07-16 13:47:14 +00:00
44f8bbfb3f
Add stores and truncstores
...
llvm-svn: 75931
2009-07-16 13:45:00 +00:00
11b91b4e2e
Add patterns for various extloads
...
llvm-svn: 75930
2009-07-16 13:44:30 +00:00
04be818918
Add shifts and reg-imm address matching
...
llvm-svn: 75927
2009-07-16 13:43:18 +00:00
cf7ea6a94f
Add bunch of 32-bit patterns... Uffff :)
...
llvm-svn: 75926
2009-07-16 13:42:31 +00:00
ebe2de0e14
Add bunch of reg-imm movs
...
llvm-svn: 75921
2009-07-16 13:34:50 +00:00
28234bcde2
Provide masked reg-imm 'or' and 'and'
...
llvm-svn: 75919
2009-07-16 13:33:57 +00:00
1c4c7823ae
Fix test running lines
...
llvm-svn: 75918
2009-07-16 13:33:21 +00:00
0d76b17a78
Add reg-reg and pattern
...
llvm-svn: 75917
2009-07-16 13:32:49 +00:00
f9fe4036f2
Add sub reg-reg pattern
...
llvm-svn: 75916
2009-07-16 13:32:16 +00:00
a083d7af53
Add xor reg-reg pattern
...
llvm-svn: 75915
2009-07-16 13:31:28 +00:00
65096d6a60
Add or reg-reg pattern.
...
llvm-svn: 75914
2009-07-16 13:30:53 +00:00
18172d786f
Add add reg-reg and reg-imm patterns
...
llvm-svn: 75913
2009-07-16 13:30:15 +00:00
09082fa01a
Add simple reg-reg and reg-imm moves
...
llvm-svn: 75912
2009-07-16 13:29:38 +00:00
cf4ba97dba
Minimal lowering for formal_arguments / ret
...
llvm-svn: 75911
2009-07-16 13:28:59 +00:00
a3ceeaeda5
Add testsuite dir for systemz stuff
...
llvm-svn: 75910
2009-07-16 13:28:22 +00:00
0cceec520c
Combine an unaligned store of unaligned load into a memmove.
...
llvm-svn: 75908
2009-07-16 12:50:48 +00:00
bfdc557c8a
Expand unaligned 32 bit loads from an address which is a constant
...
offset from a 32 bit aligned base as follows:
ldw low, base[offset >> 2]
ldw high, base[(offset >> 2) + 1]
shr low_shifted, low, (offset & 0x3) * 8
shl high_shifted, high, 32 - (offset & 0x3) * 8
or result, low_shifted, high_shifted
Expand 32 bit loads / stores with 16 bit alignment into two 16 bit
loads / stores.
llvm-svn: 75902
2009-07-16 10:42:35 +00:00
25b33cb035
Custom lower unaligned 32 bit stores and loads into libcalls. This is
...
a big code size win since before they were expanding to upto 16
instructions.
llvm-svn: 75901
2009-07-16 10:21:18 +00:00
84517443ca
Let callers decide the sub-register index on the def operand of rematerialized instructions.
...
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.
llvm-svn: 75900
2009-07-16 09:20:10 +00:00
43229fb489
ShortenDeadCopySrcLiveRange needs to be more conservative in multi-kill situations.
...
llvm-svn: 75838
2009-07-15 21:39:50 +00:00
a8edd048c2
Fix pattern for LD16S_3r, add basic tests to check load / store instructions
...
are being properly selected.
llvm-svn: 75797
2009-07-15 17:06:59 +00:00
57489b0658
Fix XCoreTargetLowering::isLegalAddressingMode to handle non simple VTs.
...
llvm-svn: 75788
2009-07-15 15:46:56 +00:00
55452c2bea
fix an arm codegen bug (the same as PR4482 on ppc) where available_externally
...
symbols were not getting stubs. While I'm at it, add a big testcase for
stub generation to make sure I don't break anything.
llvm-svn: 75737
2009-07-15 04:12:33 +00:00
7d1f9542c2
get the PPC stub temporary label from the mangler instead of
...
using horrible string hacking. This gives us a different label,
but it's just an assembler temporary, so the name doesn't matter.
llvm-svn: 75733
2009-07-15 02:56:53 +00:00
dab248ac95
convert this to filecheck style and make it a test of darwin/PPC's
...
extremely elaborate pic/nopic stubs.
llvm-svn: 75726
2009-07-15 01:43:31 +00:00
815337abd6
simplify this test to test the esentials.
...
llvm-svn: 75725
2009-07-15 01:32:33 +00:00
d7fec20cba
convert to filecheck style, simplify RUN line, and add comment.
...
llvm-svn: 75667
2009-07-14 19:49:11 +00:00
109866bf21
convert this test to filecheck style
...
llvm-svn: 75663
2009-07-14 18:57:40 +00:00
8c9a96b966
Reapply my previous asmprinter changes now with more testing and two
...
additional bug fixes:
1. The bug that everyone hit was a problem in the asmprinter where it
would remove $stub but keep the L prefix on a name when emitting the
indirect symbol. This is easy to fix by keeping the name of the stub
and the name of the symbol in a StringMap instead of just keeping a
StringSet and trying to reconstruct it late.
2. There was a problem printing the personality function. The current
logic to print out the personality function from the DWARF information
is a bit of a cesspool right now that duplicates a bunch of other
logic in the asm printer. The short version of it is that it depends
on emitting both the L and _ prefix for symbols (at least on darwin)
and until I can untangle it, it is best to switch the mangler back to
emitting both prefixes.
llvm-svn: 75646
2009-07-14 18:17:16 +00:00
966932ccb7
Revert r75610 (and r75620, which was blocking the revert), in the hopes of
...
unbreaking llvm-gcc (on Darwin).
--- Reverse-merging r75620 into '.':
U include/llvm/Support/Mangler.h
--- Reverse-merging r75610 into '.':
U test/CodeGen/X86/loop-hoist.ll
G include/llvm/Support/Mangler.h
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U lib/VMCore/Mangler.cpp
llvm-svn: 75636
2009-07-14 15:57:55 +00:00
774f2a2d51
Change the X86 asmprinter to use the mangler to apply suffixes like "$non_lazy_ptr"
...
to symbols instead of doing it with "printSuffixedName". This gets us to the point
where there is a real separation between computing a symbol name and printing it,
something I need for MC printer stuff.
This patch also fixes a corner case bug where unnamed private globals wouldn't get
the private label prefix.
Next up, rename all uses of getValueName -> getMangledName for better greppability,
and then tackle the ppc/arm backends to eliminate "printSuffixedName".
llvm-svn: 75610
2009-07-14 06:04:35 +00:00
f34815b32f
Change the internal interface to makeNameProper to take a bool that
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indicates whether the label is private or not, instead of taking
prefix stuff. One effect of this is that symbols will be generated
with *just* the private prefix, instead of both the private prefix
*and* the user-label-prefix, but this doesn't matter as long as it
is consistent. For example we'll now get "Lfoo" instead of "L_foo".
These are just assembler temporary labels anyway, so they never even
make it into the .o file.
llvm-svn: 75607
2009-07-14 04:50:12 +00:00
72b80ac9b1
Fix detection of valid BFC immediates.
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llvm-svn: 75576
2009-07-14 00:57:56 +00:00
e604b776a7
Check for the correct unnamed name.
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llvm-svn: 75573
2009-07-14 00:53:58 +00:00
dbaddda21f
Check in a reduced version of this testcase.
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llvm-svn: 75544
2009-07-13 23:04:44 +00:00
ec8efcb44e
Two changes:
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1) unique globals with the existing "Count" local in Mangler, not with
atomic nonsense. Using atomics will give us nondeterminstic output
from the compiler when using multiple threads, which is bad.
2) Do not mangle an unknown global name with a type suffix. We don't
need this anymore now that llvm ir doesn't have type planes.
llvm-svn: 75541
2009-07-13 22:48:46 +00:00
054d2a7837
Add testcases for PR4538, PR4537, and PR4534.
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llvm-svn: 75533
2009-07-13 22:30:31 +00:00
92ce8381f5
remove tests for removed intrinsics.
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llvm-svn: 75433
2009-07-12 21:30:06 +00:00
f39f55d46c
add nounwind
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llvm-svn: 75407
2009-07-12 00:46:16 +00:00
d57fb023e0
Darwin prepends an _ to internal globals, Linux doesn't.
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llvm-svn: 75405
2009-07-11 23:48:59 +00:00
38df005e12
fix x86-64 static codegen to materialize the address of a global with movl instead
...
of lea. It is better for code size (and presumably efficiency) to use:
movl $foo, %eax
rather than:
leal foo, eax
Both give a nice zero extending "move immediate" instruction, the former is just
smaller. Note that global addresses should be handled different by the x86
backend, but I chose to follow the style already in place and add more fixme's.
llvm-svn: 75403
2009-07-11 23:17:29 +00:00
056dfc6f90
this test was incorrect for x86-64 static. It passed on darwin, because darwin
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doesn't have static x86-64 mode.
llvm-svn: 75392
2009-07-11 22:30:05 +00:00
e91900097e
Fix PR4533, which is about buggy codegen in x86-64 -static mode.
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Basically, using:
lea symbol(%rip), %rax
is not valid in -static mode, because the current RIP may not be
within 32-bits of "symbol" when an app is built partially pic and
partially static. The fix for this is to compile it to:
lea symbol, %rax
It would be better to codegen this as:
movq $symbol, %rax
but that will come next.
The hard part of fixing this bug was fixing abi-isel, which was actively
testing for the wrong behavior. Also, the RUN lines are completely impossible
to understand what they are testing. To help with this, convert the -static
x86-64 codegen tests to use filecheck. This is much more stable and makes it
more clear what the codegen is expected to be.
llvm-svn: 75382
2009-07-11 20:29:19 +00:00
20adc670b2
We get the P modifier wrong in a lot of cases, just add some more rigorous testing.
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In addition to fixing this, I still need to do some more testing on darwin.
llvm-svn: 75362
2009-07-11 08:30:22 +00:00
017288a4fc
Don't put IT instruction before conditional branches.
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llvm-svn: 75361
2009-07-11 07:26:20 +00:00
0794c6a083
Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.
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llvm-svn: 75360
2009-07-11 07:08:13 +00:00
cd4cdd1157
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
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A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
2009-07-11 06:43:01 +00:00
e3c4765bac
convert test to use FileCheck, which is much more precise and faster than
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the previous RUN lines. Hopefully this will be an inspiration for future
tests :)
llvm-svn: 75261
2009-07-10 18:34:47 +00:00
0f9cce7951
Add a thumb2 pass to insert IT blocks.
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llvm-svn: 75218
2009-07-10 01:54:42 +00:00
223ac25930
Remove a bogus assertion.
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llvm-svn: 75206
2009-07-10 00:23:48 +00:00
9ce44e2521
Handle 'a' modifier on inline assembly operands.
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This is part of the fix for pr4521.
llvm-svn: 75201
2009-07-09 23:54:51 +00:00
2b77eef160
Make EXTRACT_VECTOR_ELT a bit more flexible in terms of the returned
...
value. Adjust other code to deal with that correctly. Make
DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT take advantage of
this new flexibility to simplify the code and make it deal with unusual
vectors (like <4 x i1>) correctly. Fixes PR3037.
llvm-svn: 75176
2009-07-09 22:01:03 +00:00
7452c968e4
Targets sometimes assign fixed stack object to spill certain callee-saved
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registers based on dynamic conditions. For example, X86 EBP/RBP, when used as
frame register has to be spilled in the first fixed object. It should inform
PEI this so it doesn't get allocated another stack object. Also, it should not
be spilled as other callee-saved registers but rather its spilling and restoring
are being handled by emitPrologue and emitEpilogue. Avoid spilling it twice.
llvm-svn: 75116
2009-07-09 06:53:48 +00:00
dab7b06de9
Improved tracking of value number kills. VN kills are now represented
...
as an (index,bool) pair. The bool flag records whether the kill is a
PHI kill or not. This code will be used to enable splitting of live
intervals containing PHI-kills.
A slight change to live interval weights introduced an extra spill
into lsr-code-insertion (outside the critical sections). The test
condition has been updated to reflect this.
llvm-svn: 75097
2009-07-09 03:57:02 +00:00
44f6bcfa0b
remove eh, convert to FileCheck style
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llvm-svn: 75087
2009-07-09 01:07:22 +00:00
212f44d180
we have no tests for dllimport/export. Add one.
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llvm-svn: 75085
2009-07-09 00:53:44 +00:00
ade55bc8dd
* add some assertions for sanity checking.
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* remove some old code that was needed when we'd put ESP in the scale instead of
the base of some instructions.
* Fix a bug with the P modifier in inline asm that caused us to drop it.
llvm-svn: 75077
2009-07-09 00:27:29 +00:00
da0cf0b134
add a test for dale's recent change.
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llvm-svn: 75074
2009-07-09 00:00:16 +00:00
f65129cb6a
switch test to FileCheck-style and test the P and non-P cases.
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llvm-svn: 75071
2009-07-08 23:44:06 +00:00
334e561e35
rename a test to make it a feature test.
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llvm-svn: 75070
2009-07-08 23:40:57 +00:00
22c2fba978
Use common code for both ARM and Thumb-2 instruction and register info.
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llvm-svn: 75067
2009-07-08 23:10:31 +00:00
1d298fd75b
Implement NEON vst1 instruction.
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llvm-svn: 75037
2009-07-08 20:32:02 +00:00
d5ffa8ffb6
add some more check for vector compares.
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llvm-svn: 75024
2009-07-08 18:51:25 +00:00
072198a2a1
convert a test to "FileCheck" style.
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llvm-svn: 75023
2009-07-08 18:48:24 +00:00
f731a2df6b
Implement NEON vld1 instructions.
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llvm-svn: 75019
2009-07-08 18:11:30 +00:00
121563c615
Add rev16 test... xfail for now
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llvm-svn: 75012
2009-07-08 16:15:06 +00:00
af7451b674
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
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llvm-svn: 75010
2009-07-08 16:09:28 +00:00
04bf64d43c
eliminate the v[if]cmp versions of these tests, now that [if]cmp+sext works.
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llvm-svn: 74980
2009-07-08 00:49:35 +00:00
dc84b31d94
Change these tests to use [fi]cmp+sext instead of v[fi]cmp. No
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functionality change.
llvm-svn: 74979
2009-07-08 00:46:57 +00:00
4ac607332d
dag combine sext(setcc) -> vsetcc before legalize. To make this safe,
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VSETCC must define all bits, which is different than it was documented
to before. Since all targets that implement VSETCC already have this
behavior, and we don't optimize based on this, just change the
documentation. We now get nice code for vec_compare.ll
llvm-svn: 74978
2009-07-08 00:31:33 +00:00
fc74e8241a
add support for legalizing an icmp where the result is illegal (4xi1) but
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the input is legal (4 x i32)
llvm-svn: 74964
2009-07-07 23:03:54 +00:00
cbbf747b7b
add a trivial test that vector compares work.
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llvm-svn: 74963
2009-07-07 22:51:09 +00:00
30220d8f98
implement support for spliting and scalarizing vector setcc's. This
...
finishes off enough support for vector compares to get the icmp/fcmp
version of 2008-07-23-VSetCC.ll passing.
llvm-svn: 74961
2009-07-07 22:47:46 +00:00
87d4f309f5
verify that the fcmp version of this works just as well as the
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vfcmp version. We actually get better code for this silly testcase.
llvm-svn: 74954
2009-07-07 22:07:47 +00:00
d0611f9a37
Add Thumb2 movcc instructions.
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llvm-svn: 74946
2009-07-07 20:39:03 +00:00
39d8075edc
Add missing tests.
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llvm-svn: 74945
2009-07-07 20:38:08 +00:00
d0f6324cdc
Add Thumb2 pkhbt / pkhtb.
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llvm-svn: 74895
2009-07-07 05:35:52 +00:00
b24e51e2d9
Add some more Thumb2 multiplication instructions.
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llvm-svn: 74889
2009-07-07 01:17:28 +00:00
40398233b7
Add bfc to armv6t2.
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llvm-svn: 74868
2009-07-06 22:23:46 +00:00
e63b0e6f79
Added ARM::mls for armv6t2.
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llvm-svn: 74866
2009-07-06 22:05:45 +00:00
ba2410b7ca
Avoid adding a duplicate def. This fixes PR4478.
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llvm-svn: 74857
2009-07-06 21:34:05 +00:00
0e8bde5910
Add thumb2 sign / zero extend with rotate instructions.
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llvm-svn: 74755
2009-07-03 01:43:10 +00:00
53cdf022b6
Added indexed stores.
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llvm-svn: 74740
2009-07-03 00:06:39 +00:00
8ecd7eb3f7
Sign extending pre/post indexed loads.
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llvm-svn: 74736
2009-07-02 23:16:11 +00:00
84c6cda2ef
Thumb2 pre/post indexed loads.
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llvm-svn: 74696
2009-07-02 07:28:31 +00:00
87bb642676
@GOTPCREL is also rip-relative. Fix fast-isel to do the right thing.
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This fixes an llvm-gcc bootstrap problem I introduced.
llvm-svn: 74691
2009-07-02 04:22:01 +00:00
d1c5951615
Fix yet-another bug I introduced into fastisel, this time handling
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constant pool references that weren't getting properly rip-relative.
llvm-svn: 74689
2009-07-02 03:14:25 +00:00
1f50b61329
Fix codegen for references to available_externally symbols. This fixes
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PR4482.
llvm-svn: 74613
2009-07-01 16:53:44 +00:00
04f72fc955
CommuteChangesDestination() should check if to-be-commuted instruction defines any register. Also teaches the default commuteInstruction() to commute instruction without definitions (e.g. X86::test / ARM::tsp).
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llvm-svn: 74602
2009-07-01 08:29:08 +00:00
2a5efe14a7
Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def.
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Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def.
llvm-svn: 74601
2009-07-01 08:19:36 +00:00
f95fa1b721
Fix some fast-isel problems selecting global variable addressing in
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pic mode.
llvm-svn: 74582
2009-07-01 03:27:19 +00:00
d379e896ff
Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
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llvm-svn: 74580
2009-07-01 01:59:31 +00:00
86c7e20ca6
Add PIC load and store patterns for Thumb-2.
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llvm-svn: 74577
2009-07-01 00:01:13 +00:00
d0890a2bad
Add thumb-2 store word, halfword, and byte.
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llvm-svn: 74555
2009-06-30 22:11:34 +00:00
28d6d87244
Improve Thumb-2 jump table support.
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llvm-svn: 74549
2009-06-30 19:50:22 +00:00
317fd045e2
Fix PR4485.
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Avoid unnecessary duplication of operand 0 of X86::FpSET_ST0_80. This duplication would
cause one register to remain on the stack at the function return.
llvm-svn: 74534
2009-06-30 16:40:03 +00:00
bd971ffcc6
Fix PR4484.
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This was caused by me confounding FP0 and ST(0).
llvm-svn: 74523
2009-06-30 12:18:16 +00:00
dcf1f59305
Temporarily restore the scavenger implicit_def checking code. MachineOperand isUndef mark is not being put on implicit_def of physical registers (created for parameter passing, etc.).
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llvm-svn: 74519
2009-06-30 09:19:42 +00:00
0dc101b897
Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.
...
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.
This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.
llvm-svn: 74518
2009-06-30 08:49:04 +00:00
57726817aa
A few more load instructions.
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llvm-svn: 74500
2009-06-30 02:15:48 +00:00
17512663f5
Enhance tests to include shifted-register operand testing.
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llvm-svn: 74490
2009-06-30 01:02:20 +00:00
76b37950ca
Add Thumb-2 support for TEQ amd TST.
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llvm-svn: 74468
2009-06-29 22:49:42 +00:00
911edef65b
Thumb-2 tests
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llvm-svn: 74464
2009-06-29 22:25:22 +00:00
538064d6b1
FIX PR 4459.
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Not sure I understand how the temp register gets used,
but this fixes a bug and introduces no regressions.
llvm-svn: 74446
2009-06-29 20:29:59 +00:00
dbf11ba800
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
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llvm-svn: 74423
2009-06-29 15:33:01 +00:00
b23b50d54d
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
9876bd8257
factor some logic out into a helper function, allow remat of loads from constant
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globals. This implements remat-constant.ll even without aggressive-remat.
llvm-svn: 74373
2009-06-27 04:38:55 +00:00
fea81da433
Reimplement rip-relative addressing in the X86-64 backend. The new
...
implementation primarily differs from the former in that the asmprinter
doesn't make a zillion decisions about whether or not something will be
RIP relative or not. Instead, those decisions are made by isel lowering
and propagated through to the asm printer. To achieve this, we:
1. Represent RIP relative addresses by setting the base of the X86 addr
mode to X86::RIP.
2. When ISel Lowering decides that it is safe to use RIP, it lowers to
X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to
X86ISD::Wrapper as before.
3. This removes isRIPRel from X86ISelAddressMode, representing it with
a basereg of RIP instead.
4. The addressing mode matching logic in isel is greatly simplified.
5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate
passed through various printoperand routines is gone now.
6. The various symbol printing routines in asmprinter now no longer infer
when to emit (%rip), they just print the symbol.
I think this is a big improvement over the previous situation. It does have
two small caveats though: 1. I implemented a horrible "no-rip" modifier for
the inline asm "P" constraint modifier. This is a short term hack, there is
a much better, but more involved, solution. 2. I had to xfail an
-aggressive-remat testcase because it isn't handling the use of RIP in the
constant-pool reading instruction. This specific test is easy to fix without
-aggressive-remat, which I intend to do next.
llvm-svn: 74372
2009-06-27 04:16:01 +00:00
df92e147c9
remove some unneeded eh info.
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llvm-svn: 74371
2009-06-27 04:07:31 +00:00
de36afc1fe
testcase for PR4466
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llvm-svn: 74367
2009-06-27 01:33:35 +00:00
5285817490
When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.
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llvm-svn: 74355
2009-06-26 23:13:13 +00:00
d3b930d426
Add some testcases for some of the recent ScalarEvolution bug fixes.
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llvm-svn: 74353
2009-06-26 22:54:11 +00:00
3aaa751712
Thumb-2 tests
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llvm-svn: 74345
2009-06-26 22:37:07 +00:00
b5c2639f83
remove unwind info, add test for asmprinting of jump table labels with (%rip)
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llvm-svn: 74337
2009-06-26 22:16:49 +00:00
07b016856d
Add x86 support for 'n' inline asm modifier. This will be handled target independently as part of MC work.
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llvm-svn: 74336
2009-06-26 22:00:19 +00:00
aa294c5593
Thumb-2 has CLZ.
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llvm-svn: 74322
2009-06-26 20:47:43 +00:00
35ee722d42
Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc".
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llvm-svn: 74321
2009-06-26 20:45:56 +00:00
a720af1370
More spelling Count as count.
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llvm-svn: 74306
2009-06-26 18:35:07 +00:00
6b1678d5d8
Spell Count as count.
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llvm-svn: 74298
2009-06-26 18:21:54 +00:00
3bd42afebe
Add Thumb-2 tests.
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llvm-svn: 74295
2009-06-26 18:10:30 +00:00
5960e6d974
ADC used to implement adde should use "adcs" opcode instead of "adc".
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llvm-svn: 74293
2009-06-26 18:07:25 +00:00
34f7ede9e7
ORN and BIC tests.
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llvm-svn: 74289
2009-06-26 16:20:06 +00:00
0377f737ff
Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
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Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.
llvm-svn: 74288
2009-06-26 16:10:07 +00:00
7779156b39
Fix tests: Count -> count.
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llvm-svn: 74282
2009-06-26 07:05:57 +00:00
34c8c7414f
Fix a CodeGenDAGPatterns bug. Check if top level predicates match when it's looking for duplicates.
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llvm-svn: 74276
2009-06-26 05:59:16 +00:00
07025e2c02
Fix spelling of 'count'
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llvm-svn: 74249
2009-06-26 01:33:02 +00:00
97727a61f9
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
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llvm-svn: 74228
2009-06-25 23:34:10 +00:00
16f357cccf
Use MVN for ~t2_so_imm immediates.
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llvm-svn: 74223
2009-06-25 23:11:21 +00:00
722c6e1b70
Don't grep the -debug output. This isn't the way to test changes.
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llvm-svn: 74211
2009-06-25 21:59:32 +00:00
a4194b1082
down with unwind info :)
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llvm-svn: 74206
2009-06-25 21:48:17 +00:00
c7ea8df67e
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
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llvm-svn: 74200
2009-06-25 20:59:23 +00:00
83f979a48b
Add Thumb2 pc relative add.
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llvm-svn: 74141
2009-06-24 23:47:58 +00:00
ff1a4a7271
We should run these tests as well.
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llvm-svn: 74121
2009-06-24 21:36:26 +00:00
01d5049dc2
unwind info not needed.
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llvm-svn: 74112
2009-06-24 19:48:04 +00:00
d76d0aa68a
Move thumb and thumb2 tests into separate directories.
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llvm-svn: 74068
2009-06-24 06:36:07 +00:00
38f2453817
Fix support for inline asm input / output operand tying when operand spans across multiple registers (e.g. two i64 operands in 32-bit mode).
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llvm-svn: 74053
2009-06-24 02:05:51 +00:00
f19aeec3f5
Extend ScalarEvolution's multiple-exit support to compute exact
...
trip counts in more cases.
Generalize ScalarEvolution's isLoopGuardedByCond code to recognize
And and Or conditions, splitting the code out into an
isNecessaryCond helper function so that it can evaluate Ands and Ors
recursively, and make SCEVExpander be much more aggressive about
hoisting instructions out of loops.
test/CodeGen/X86/pr3495.ll has an additional instruction now, but
it appears to be due to an arbitrary register allocation difference.
llvm-svn: 74048
2009-06-24 01:18:18 +00:00
4983e4550e
Proper patterns for thumb2 shift and rotate instructions.
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llvm-svn: 73987
2009-06-23 19:39:13 +00:00
2e076c4e02
Add support for ARM's Advanced SIMD (NEON) instruction set.
...
This is still a work in progress but most of the NEON instruction set
is supported.
llvm-svn: 73919
2009-06-22 23:27:02 +00:00
16ee19738c
It's coalescer, not coaleser.
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llvm-svn: 73902
2009-06-22 21:09:17 +00:00
4582530a2c
For Darwin on ARMv6 and newer, make register r9 available for use as a
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caller-saved register.
llvm-svn: 73901
2009-06-22 21:01:46 +00:00
8cbbc7944d
Fix another register coalescer crash: forgot to check if the instruction being updated has already been coalesced.
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llvm-svn: 73898
2009-06-22 20:49:32 +00:00
3d75d6af57
hasFP should return true if frame address is taken.
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llvm-svn: 73893
2009-06-22 18:38:48 +00:00
6ead59f8ed
Fix PR4185.
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Handle FpSET_ST0_80 being used when ST0 is still alive.
llvm-svn: 73850
2009-06-21 12:02:51 +00:00
7d2b049404
change TLS_ADDR lowering to lower to a real mem operand, instead of matching as
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a global with that gets printed with the :mem modifier. All operands to lea's
should be handled with the lea32mem operand kind, and this allows the TLS stuff
to do this. There are several better ways to do this, but I went for the minimal
change since I can't really test this (beyond make check).
This also makes the use of EBX explicit in the operand list in the 32-bit,
instead of implicit in the instruction.
llvm-svn: 73834
2009-06-20 20:38:48 +00:00
1771a852f0
no need for unwind info
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llvm-svn: 73832
2009-06-20 19:48:26 +00:00
fbc9778a1b
no need for unwind info here.
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llvm-svn: 73831
2009-06-20 19:43:09 +00:00
c6a8d0dbe9
Fix PR4419: handle defs of partial uses.
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llvm-svn: 73816
2009-06-20 04:34:51 +00:00
cc31110b95
Re-apply r73718, now that the fix in r73787 is in, and add a
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hand-crafted testcase which demonstrates the bug that was exposed
in 254.gap.
llvm-svn: 73793
2009-06-19 23:23:27 +00:00
b4b20bbb7d
Enable arm pre-allocation load / store multiple optimization pass.
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llvm-svn: 73791
2009-06-19 23:17:27 +00:00
86076c9e30
Revert 73718. It's breaking 254.gap.
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llvm-svn: 73783
2009-06-19 21:15:06 +00:00
2fc939c809
Fix for PR2484: add an SSE1 pattern for a shuffle we normally prefer to
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handle with an SSE2 instruction.
llvm-svn: 73760
2009-06-19 07:00:55 +00:00
d984158320
Mark a few Thumb instructions commutable; just happened to spot this
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while experimenting. I'm reasonably sure this is correct, but please
tell me if these instructions have some strange property which makes this
change unsafe.
llvm-svn: 73746
2009-06-19 01:43:08 +00:00
Chris Lattner