Commit Graph

32592 Commits

Author SHA1 Message Date
David Majnemer 47e3842982 COFF: Let globals with private linkage reside in their own section
Summary:
COFF COMDATs (for selection kinds other than 'select any') require at
least one non-section symbol in the symbol table.
Satisfy this by morally enhancing the linkage from private to internal.

Reviewers: rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8374

llvm-svn: 232539
2015-03-17 20:39:25 +00:00
Rafael Espindola 9ab09237dc Centralize the handling of unique ids for temporary labels.
Before this patch code wanting to create temporary labels for a given entity
(function, cu, exception range, etc) had to keep its own counter to have stable
symbol names.

createTempSymbol would still add a suffix to make sure a new symbol was always
returned, but it kept a single counter. Because of that, if we were to use
just createTempSymbol("cu_begin"), the label could change from cu_begin42 to
cu_begin43 because some other code started using temporary labels.

Simplify this by just keeping one counter per prefix and removing the various
specialized counters.

llvm-svn: 232535
2015-03-17 20:07:06 +00:00
Samuel Antao 0d59f31d12 Add assertion to detect invalid registers in the PowerPC MC instruction lowering.
We have observed that noreg was being generated due to a bug in FastIsel and was not being detected during emission. It happens that in the Asm emission there is an assertion that detects this in getRegisterName() from the tbl-generated file PPCGenAsmWriter.inc. However, when emitting an Obj file, invalid registers can be emitted given that no check are made in getBinaryCodeFromInstr() from PPCGenMCCodeEmitter.inc. In order to cover all cases this adds an assertion for reg operands in LowerPPCMachineInstrToMCInst.

llvm-svn: 232525
2015-03-17 19:31:19 +00:00
Richard Barton 30934c0926 [ARM] Fix offset calculation in ARMBaseRegisterInfo::needsFrameBaseReg
The input offset to needsFrameBaseReg is a negative value below the top of the
stack frame, but when converting to a positive offset from the bottom of the
stack frame this value was negated, causing the final offset to be too large
by twice the input offset's magnitude. Fix that by not negating the offset.

Patch by John Brawn

Differential Revision: http://reviews.llvm.org/D8316

llvm-svn: 232513
2015-03-17 18:20:47 +00:00
Daniel Sanders 2eeace219d [systemz] Distinguish the 'Q', 'R', 'S', and 'T' inline assembly memory constraints.
Summary:
But still handle them the same way since I don't know how they differ on
this target.

No functional change intended.

Reviewers: uweigand

Reviewed By: uweigand

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8251

llvm-svn: 232495
2015-03-17 16:16:14 +00:00
Samuel Antao f68156015d Fix R0 use in PowerPC VSX store for FastIsel.
The VSX stores are sometimes generated with a undefined index register, causing %noreg to be used and R0 to be emitted later on. The semantics of the VSX store (e.g. stdsdx) requires R0 to be used as base if we want zero to be used in the computation of the effective address instead of the content of R0. This patch checks if no index register was generated and forces R0 to be used as base address.

llvm-svn: 232486
2015-03-17 15:00:57 +00:00
Rafael Espindola ccfbbd5596 Use createTempSymbol to avoid collisions instead of an ad hoc method.
llvm-svn: 232483
2015-03-17 14:50:32 +00:00
Rafael Espindola 8dc4e1007a Make EmitFunctionHeader a private helper.
llvm-svn: 232481
2015-03-17 14:38:30 +00:00
Daniel Sanders 49f643c472 Re-commit: [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints.
Summary:
But still handle them the same way since I don't know how they differ on
this target.

No functional change intended.

Reviewers: kparzysz, adasgupt

Reviewed By: kparzysz, adasgupt

Subscribers: colinl, llvm-commits

Differential Revision: http://reviews.llvm.org/D8204

Like for the PowerPC target, I've had to add 'i' to the constraint mappings in
order to pass 2007-12-17-InvokeAsm.ll. It's not clear why 'i' has historically
been treated as a memory constraint.

llvm-svn: 232480
2015-03-17 14:37:39 +00:00
Rafael Espindola ec8da3de01 Call EmitFunctionHeader just before EmitFunctionBody.
This avoids switching to .AMDGPU.config and back and hardcoding the
section it switches back to.

llvm-svn: 232479
2015-03-17 14:34:42 +00:00
Rafael Espindola 5345e420c4 Convert the easy cases of GetTempSymbol to createTempSymbol.
In these cases no code was depending on GetTempSymbol finding an existing
symbol.

llvm-svn: 232478
2015-03-17 14:22:31 +00:00
Rafael Espindola dc4263c760 Move the EH symbol to the asm printer and use it for the SJLJ case too.
llvm-svn: 232475
2015-03-17 13:57:48 +00:00
Toma Tabacu dcebf5b901 [mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction.
Summary:
This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58".
This should work for all MIPS ISAs.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8284

llvm-svn: 232473
2015-03-17 13:17:44 +00:00
Daniel Sanders 914b947e9b Fix r232466 by adding 'i' to the mappings for inline assembly memory constraints.
It's not completely clear why 'i' has historically been treated as a memory
constraint. According to the documentation, it represents a constant immediate.

llvm-svn: 232470
2015-03-17 12:00:04 +00:00
Renato Golin 1235060734 [ARM] Add support for ARMV6K subtarget (LLVM)
ARMv6K is another layer between ARMV6 and ARMV6T2. This is the LLVM
side of the changes.

ARMV6 family LLVM implementation.

+-------------------------------------+
| ARMV6                               |
+----------------+--------------------+
| ARMV6M (thumb) | ARMV6K (arm,thumb) | <- From ARMV6K and ARMV6M processors
+----------------+--------------------+    have support for hint instructions
| ARMV6T2 (arm,thumb,thumb2)          |    (SEV/WFE/WFI/NOP/YIELD). They can
+-------------------------------------+    be either real or default to NOP.
| ARMV7 (arm,thumb,thumb2)            |    The two processors also use
+-------------------------------------+    different encoding for them.

Patch by Vinicius Tinti.

llvm-svn: 232468
2015-03-17 11:55:28 +00:00
Daniel Sanders 0828860694 [ppc] Distinguish the 'es', 'o', 'm', 'Q', 'Z', and 'Zy' inline assembly memory constraints.
Summary:
But still handle them the same way since I don't know how they differ on
this target.

Of these, 'es', and 'Q' do not have backend tests but are accepted by
clang.

No functional change intended. Depends on D8173.

Reviewers: hfinkel

Reviewed By: hfinkel

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8213

llvm-svn: 232466
2015-03-17 11:09:13 +00:00
Ahmed Bougacha e0afb1fe6c [AArch64] Use intermediate step for concat_vectors of illegal truncs.
Optimize concat_vectors of truncated vectors, where the intermediate
type is illegal, to avoid said illegality,  e.g.,
  (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
                         (v2i16 (truncate (v2i64)))))
->
  (v4i16 (truncate (v4i32 (concat_vectors (v2i32 (truncate (v2i64))),
                                          (v2i32 (truncate (v2i64)))))))

This isn't really target-specific, and, as such, would best go in the
DAGCombiner.  However, ISD::TRUNCATE legality isn't keyed on both input
and result type, so we might generate worse code when we don't know
better.  On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
rdar://20022387

llvm-svn: 232459
2015-03-17 03:23:09 +00:00
Ahmed Bougacha e33e6c979c [AArch64] Factor out N->getOperand()s; format. NFCI.
llvm-svn: 232458
2015-03-17 03:19:18 +00:00
Rafael Espindola f696df1148 Pass in a "const Triple &T" instead of a raw StringRef.
llvm-svn: 232429
2015-03-16 22:29:29 +00:00
Rafael Espindola 9bcf2fcb89 Remove unused argument. NFC.
llvm-svn: 232428
2015-03-16 22:06:15 +00:00
Rafael Espindola 73870dd438 There is only one Asm streamer, there is no need for targets to register it.
Instead, have the targets register a TargetStreamer to be use with the
asm streamer (if any).

llvm-svn: 232423
2015-03-16 21:43:42 +00:00
David Blaikie 9f380a3ca0 Fix uses of reserved identifiers starting with an underscore followed by an uppercase letter
This covers essentially all of llvm's headers and libs. One or two weird
cases I wasn't sure were worth/appropriate to fix.

llvm-svn: 232394
2015-03-16 18:06:57 +00:00
Tom Stellard 7c840bcbf3 R600/SI: don't try min3/max3/med3 with f64
There are no opcodes for this. This also adds a test case.

v2: make test more robust

Patch by: Grigori Goronzy

llvm-svn: 232386
2015-03-16 15:53:55 +00:00
Sanjay Patel c2bdf37712 fix comments to match code; NFC
llvm-svn: 232385
2015-03-16 15:38:48 +00:00
Petar Jovanovic b592a75f5e [MIPS] Fix justify error for small structures
Fix justify error for small structures bigger than 32 bits in fixed
arguments for MIPS64 big endian. There was a problem when small structures
are passed as fixed arguments. The structures that are bigger than 32 bits
but smaller than 64 bits were not left justified properly on MIPS64 big
endian. This is fixed by shifting the value to make it left justified when
appropriate.

Patch by Aleksandar Beserminji.

Differential Revision: http://reviews.llvm.org/D8174

llvm-svn: 232382
2015-03-16 15:01:09 +00:00
Rafael Espindola 933f51af54 Use the i8 immediate cmp instructions when possible.
llvm-svn: 232378
2015-03-16 14:25:08 +00:00
Daniel Sanders e8a570562d Revert r232374: [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints.
2007-12-17-InvokeAsm.ll fails on the buildbot but not on my own system. Will investigate.

llvm-svn: 232376
2015-03-16 14:21:22 +00:00
Rafael Espindola 19141f2711 Don't repeat names in comments and clang-format this function.
llvm-svn: 232375
2015-03-16 14:05:49 +00:00
Daniel Sanders b2d0c02451 [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints.
Summary:
But still handle them the same way since I don't know how they differ on
this target.

No functional change intended.

Reviewers: kparzysz, adasgupt

Reviewed By: kparzysz, adasgupt

Subscribers: colinl, llvm-commits

Differential Revision: http://reviews.llvm.org/D8204

llvm-svn: 232374
2015-03-16 13:54:19 +00:00
Daniel Sanders bf5b80f5f9 Make each target map all inline assembly memory constraints to InlineAsm::Constraint_m. NFC.
Summary:
This is instead of doing this in target independent code and is the last
non-functional change before targets begin to distinguish between
different memory constraints when selecting code for the ISD::INLINEASM
node.

Next, each target will individually move away from the idea that all
memory constraints behave like 'm'.

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D8173

llvm-svn: 232373
2015-03-16 13:13:41 +00:00
Toma Tabacu 234482a54e [mips] [IAS] Outline NOP creation. NFC.
Summary: Make the code more readable by outlining NOP creation.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8320

llvm-svn: 232371
2015-03-16 12:03:39 +00:00
Gabor Horvath fee043439c [llvm] Replacing asserts with static_asserts where appropriate
Summary:
This patch consists of the suggestions of clang-tidy/misc-static-assert check.


Reviewers: alexfh

Reviewed By: alexfh

Subscribers: xazax.hun, llvm-commits

Differential Revision: http://reviews.llvm.org/D8343

llvm-svn: 232366
2015-03-16 09:53:42 +00:00
Simon Pilgrim e2c6a1b96d Use SDValue bool check to tidyup some possible combines. NFC.
llvm-svn: 232331
2015-03-15 19:47:42 +00:00
Simon Pilgrim cc4d4d4fef Use SDValue bool check to tidyup some possible combines. NFC.
llvm-svn: 232325
2015-03-15 17:21:35 +00:00
David Blaikie c95c3aee15 [opaque pointer type] gep API migration
llvm-svn: 232279
2015-03-14 21:20:51 +00:00
David Blaikie 096b1da29d [opaque pointer type] more gep API migration
llvm-svn: 232274
2015-03-14 19:53:33 +00:00
Vasileios Kalintiris 46fa9b7b1e [mips] Remove trivial header for the MipsModuleISelDAGToDAG pass. NFC.
llvm-svn: 232260
2015-03-14 09:20:52 +00:00
Vasileios Kalintiris 6611eb35f1 [mips] Remove trivial header for the Mips16HardFloat pass. NFC.
llvm-svn: 232259
2015-03-14 09:02:23 +00:00
Vasileios Kalintiris 6312f516ee [mips] Remove trivial header for the MipsOs16 pass. NFC.
llvm-svn: 232258
2015-03-14 08:34:25 +00:00
Rafael Espindola e7ce9ec398 Use add32ri8 and friends on fast isel.
This fixes pr22854.

The core issue on the bug is that there are multiple instructions that
print the same in assembly. In fact, there doesn't seem to be any
syntax for specifying that a constant that fits in 8 bits should use a 32 bit
immediate.

The attached patch changes fast isel to consider i16immSExt8,
i32immSExt8, and i64immSExt8. They were disabled because fastisel didn’t know
to call the predicate back in the day.

llvm-svn: 232223
2015-03-13 22:18:18 +00:00
Alexei Starovoitov 58a615f9d0 bpf: turn on HasJIT flag in BPF backend
basic tests that use BPF backend to produce code in memory are passing.

llvm-svn: 232222
2015-03-13 22:03:25 +00:00
Alexei Starovoitov a208faa0a3 bpf: fix build
fix missed bits which were left over after r231987

Signed-off-by: Alexei Starovoitov <ast@plumgrid.com>
llvm-svn: 232208
2015-03-13 20:49:38 +00:00
Jan Vesely 7a9cca9e7d r600: Clear visited structure before running.
Fixes random crashes in for-loop piglit.

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com>
llvm-svn: 232181
2015-03-13 17:32:46 +00:00
Jan Vesely 18b289f590 r600: Use deque and simplify loops in AMDGPUCFGStructurizer
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com>
llvm-svn: 232180
2015-03-13 17:32:43 +00:00
Andrea Di Biagio 510feca1b8 [X86][AVX] Fix wrong lowering of v4x64 shuffles into concat_vector plus extract_subvector nodes.
This patch fixes a bug in the shuffle lowering logic implemented by function
'lowerV2X128VectorShuffle'.

The are few cases where function 'lowerV2X128VectorShuffle' wrongly expands a
shuffle of two v4X64 vectors into a CONCAT_VECTORS of two EXTRACT_SUBVECTOR
nodes. The problematic expansion only occurs when the shuffle mask M has an
'undef' element at position 2, and M is equivalent to mask <0,1,4,5>.
In that case, the algorithm propagates the wrong vector to one of the two
new EXTRACT_SUBVECTOR nodes.

Example:
;;
define <4 x double> @test(<4 x double> %A, <4 x double> %B) {
entry:
  %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32><i32 undef, i32 1, i32 undef, i32 5>
  ret <4 x double> %0
}
;;

Before this patch, llc (-mattr=+avx) generated:
  vinsertf128 $1, %xmm0, %ymm0, %ymm0

With this patch, llc correctly generates:
  vinsertf128 $1, %xmm1, %ymm0, %ymm0

Added test lower-vec-shuffle-bug.ll

Differential Revision: http://reviews.llvm.org/D8259

llvm-svn: 232179
2015-03-13 17:29:49 +00:00
Benjamin Kramer 76e37aa334 unique_ptrs are unique already, no need to unique them any further.
llvm-svn: 232178
2015-03-13 16:59:29 +00:00
Daniel Sanders 60f1db0525 Recommit r232027 with PR22883 fixed: Add infrastructure for support of multiple memory constraints.
The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break
anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate
Constraint_* values.

PR22883 was caused the matching operands copying the whole of the operand flags
for the matched operand. This included the constraint id which needed to be
replaced with the operand number. This has been fixed with a conversion
function. Following on from this, matching operands also used the operand
number as the constraint id. This has been fixed by looking up the matched
operand and taking it from there. 

llvm-svn: 232165
2015-03-13 12:45:09 +00:00
Toma Tabacu e95a49118c [mips] [IAS] Refactor MipsTargetStreamer::emitMipsAbiFlags(). NFC.
Summary: Make emitMipsAbiFlags a direct member of MipsTargetELFStreamer, as that's the only place where it's used, and remove the empty implementations from MipsTargetStreamer and MipsTargetAsmStreamer.

Reviewers: dsanders, rafael

Reviewed By: rafael

Subscribers: rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D8199

llvm-svn: 232161
2015-03-13 11:40:01 +00:00
Sanjay Patel 4339abe66f [X86, AVX2] Replace inserti128 and extracti128 intrinsics with generic shuffles
This should complete the job started in r231794 and continued in r232045:
We want to replace as much custom x86 shuffling via intrinsics
as possible because pushing the code down the generic shuffle
optimization path allows for better codegen and less complexity
in LLVM.

AVX2 introduced proper integer variants of the hacked integer insert/extract
C intrinsics that were created for this same functionality with AVX1.

This should complete the removal of insert/extract128 intrinsics.

The Clang precursor patch for this change was checked in at r232109.

llvm-svn: 232120
2015-03-12 23:16:18 +00:00
Eric Christopher 7fde301d5b Move a variable into the assert where it's used - fixes a -Asserts
build warning/error.

llvm-svn: 232119
2015-03-12 23:13:03 +00:00
Eric Christopher ae32649ff2 In preparation for moving ARM's TargetRegisterInfo to the TargetMachine
merge Thumb1RegisterInfo and Thumb2RegisterInfo. This will enable
us to match the TargetMachine for our TargetRegisterInfo classes.

llvm-svn: 232117
2015-03-12 22:48:50 +00:00
Tom Stellard e2f5b41055 R600/SI: Don't print scc reg in sopc assembly string
This is how the proprietary driver prints sopc instructions.

llvm-svn: 232106
2015-03-12 21:34:28 +00:00
Tom Stellard c0503926f5 R600/SI: Remove _e32 and _e64 suffixes from mnemonics
Instead print them as part of the $dst operand.  The AsmMatcher
requires the 32-bit and 64-bit encodings have the same mnemonic in
order to parse them correctly.

llvm-svn: 232105
2015-03-12 21:34:22 +00:00
Eric Christopher 1b585aeb8a Migrate the AArch64 TargetRegisterInfo to its TargetMachine
implementation. This requires a bit of scaffolding and a few fixups
that'll go away once all of the ports have been migrated.

llvm-svn: 232103
2015-03-12 21:04:46 +00:00
Hal Finkel e78e52ba9b Revert "r232027 - Add infrastructure for support of multiple memory constraints"
This (r232027) has caused PR22883; so it seems those bits might be used by
something else after all. Reverting until we can figure out what else to do.

Original commit message:

The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate Constraint_*
values.

llvm-svn: 232093
2015-03-12 20:09:39 +00:00
Quentin Colombet f59b2d034c [X86] Fix a regression introduced by r223641.
The permps and permd instructions have their operands swapped compared to the
intrinsic definition. Therefore, they do not fall into the INTR_TYPE_2OP
category.

I did not create a new category for those two, as they are the only one AFAICT
in that case.

<rdar://problem/20108262>

llvm-svn: 232085
2015-03-12 19:34:12 +00:00
Eric Christopher 63ea0402c2 Fix comment formatting.
llvm-svn: 232076
2015-03-12 18:23:01 +00:00
Eric Christopher ed6a446403 Remove the need to cache the subtarget in the X86 TargetRegisterInfo
classes. Use a Triple instead and simplify a lot of the querying
logic to use lookups on the Triple.

llvm-svn: 232071
2015-03-12 17:54:19 +00:00
Krzysztof Parzyszek a29622a8c5 Remove unused complex patterns for addressing modes on Hexagon.
llvm-svn: 232057
2015-03-12 16:44:50 +00:00
Andrea Di Biagio de2fb00a16 [X86] Fix wrong target specific combine on SETCC nodes.
Part of the folding logic implemented by function 'PerformISDSETCCCombine'
only worked under the assumption that the condition code in input could have
been either SETNE or SETEQ.
Unfortunately that assumption was incorrect, and in some cases the algorithm
ended up incorrectly folding SETCC nodes.

The incorrect folding only affected SETCC dag nodes where:
 - one of the operands was a build_vector of all zeroes;
 - the other operand was a SIGN_EXTEND from a vector of MVT:i1 elements;
 - the condition code was neither SETNE nor SETEQ.

Example:
  (setcc (v4i32 (sign_extend v4i1:%A)), (v4i32 VectorOfAllZeroes), setge)

Before this patch, the entire dag node sequence from the example was
incorrectly folded to node %A.

With this patch, the dag node sequence is folded to a
  (xor %A, (v4i1 VectorOfAllOnes)).

Added test setcc-combine.ll.

Thanks to Greg Bedwell for spotting this issue.

llvm-svn: 232046
2015-03-12 15:16:58 +00:00
Aaron Ballman c579d66b9a Silencing an "enumeral and non-enumeral type in conditional expression" warning; NFC.
llvm-svn: 232035
2015-03-12 13:24:06 +00:00
Daniel Sanders 41c072e63b Add infrastructure for support of multiple memory constraints.
Summary:
The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate Constraint_*
values.

Reviewers: hfinkel

Reviewed By: hfinkel

Subscribers: hfinkel, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D8171

llvm-svn: 232027
2015-03-12 11:00:48 +00:00
Elena Demikhovsky 5d06b4c80c AVX-512: Added encoding tests for VPROR, VPROL instructions,
fixed opcode.

llvm-svn: 232018
2015-03-12 07:28:41 +00:00
Eric Christopher 234a1ec404 Remove some unnecessary forward declarations and put a couple more
where they're supposed to reside.

llvm-svn: 232014
2015-03-12 06:07:16 +00:00
Eric Christopher 8bb838ac07 Remove the need to cache the subtarget in the Sparc TargetRegisterInfo
classes.

llvm-svn: 232013
2015-03-12 05:55:26 +00:00
Eric Christopher a20c3cf85d Remove the need to cache the subtarget in the Mips TargetRegisterInfo
classes.

llvm-svn: 232012
2015-03-12 05:43:57 +00:00
Eric Christopher 34085832f8 Remove the need to cache the subtarget in the ARM TargetRegisterInfo
classes. Replace the frame pointer initialization with a static function
that'll look it up via the subtarget on the MachineFunction.

llvm-svn: 232010
2015-03-12 05:12:31 +00:00
Eric Christopher 09696d3fea Remove the need to cache the subtarget in the AArch64 TargetRegisterInfo
classes. Replace it with a cache to the Triple and use that
where applicable at the moment.

llvm-svn: 232005
2015-03-12 02:04:46 +00:00
Jingyue Wu e8290f21b5 [NVPTXAsmPrinter] do not print .align on function headers
Summary:
PTX does not allow .align directives on function headers.

Fixes PR21551.

Test Plan: test/Codegen/NVPTX/function-align.ll

Reviewers: eliben, jholewinski

Reviewed By: eliben, jholewinski

Subscribers: llvm-commits, eliben, jpienaar, jholewinski

Differential Revision: http://reviews.llvm.org/D8274

llvm-svn: 232004
2015-03-12 01:50:30 +00:00
Eric Christopher ea178cf48f Remove the need to cache the subtarget in the PowerPC TargetRegisterInfo
classes. Replace it with a cache to the TargetMachine and use that
where applicable at the moment.

llvm-svn: 232002
2015-03-12 01:42:51 +00:00
Krzysztof Parzyszek 325297c101 Fix build break introduced in r231992
llvm-svn: 231996
2015-03-12 00:49:13 +00:00
Krzysztof Parzyszek 6d5a4b5dcd Eliminate constant-extender profitability checks from Hexagon isel
llvm-svn: 231992
2015-03-12 00:19:59 +00:00
Mehdi Amini 93e1ea167e Move the DataLayout to the generic TargetMachine, making it mandatory.
Summary:
I don't know why every singled backend had to redeclare its own DataLayout.
There was a virtual getDataLayout() on the common base TargetMachine, the
default implementation returned nullptr. It was not clear from this that
we could assume at call site that a DataLayout will be available with
each Target.

Now getDataLayout() is no longer virtual and return a pointer to the
DataLayout member of the common base TargetMachine. I plan to turn it into
a reference in a future patch.

The only backend that didn't have a DataLayout previsouly was the CPPBackend.
It now initializes the default DataLayout. This commit is NFC for all the
other backends.

Test Plan: clang+llvm ninja check-all

Reviewers: echristo

Subscribers: jfb, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D8243

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 231987
2015-03-12 00:07:24 +00:00
Hal Finkel 6a778fb7c2 [PowerPC] Remove canFoldAsLoad from instruction definitions
The PowerPC backend had a number of loads that were marked as canFoldAsLoad
(and I'm partially at fault here for copying around the relevant line of
TableGen definitions without really looking at what it meant). This is not
right; PPC (non-memory) instructions don't support direct memory operands, and
so there is nothing a 'foldable' instruction could be folded into.

Noticed by inspection, no test case.

The one thing we might lose by doing this is ability to fold some loads into
stackmap/patchpoint pseudo-instructions. However, this was untested, and would
not obviously have worked for extending loads, and I'd rather re-add support
for that once it can be tested.

llvm-svn: 231982
2015-03-11 23:28:38 +00:00
Eric Christopher 5f141b03fa Remove useMachineScheduler and replace it with subtarget options
that control, individually, all of the disparate things it was
controlling.

At the same time move a FIXME in the Hexagon port to a new
subtarget function that will enable a user of the machine
scheduler to avoid using the source scheduler for pre-RA-scheduling.
The FIXME would have this removed, but involves either testcase
changes or adding -pre-RA-sched=source to a few testcases.

llvm-svn: 231980
2015-03-11 22:56:10 +00:00
Eric Christopher 9deb75d176 Have getCallPreservedMask and getThisCallPreservedMask take a
MachineFunction argument so that we can grab subtarget specific
features off of it.

llvm-svn: 231979
2015-03-11 22:42:13 +00:00
Eric Christopher ec8cda5668 One more getCalleeSavedRegs prototype with nullptr.
llvm-svn: 231977
2015-03-11 22:24:37 +00:00
Eric Christopher 7af9528747 Have getCalleeSavedRegs take a non-null MachineFunction all the
time. The target independent code was passing in one all the
time and targets weren't checking validity before using. Update
a few calls to pass in a MachineFunction where necessary.

llvm-svn: 231970
2015-03-11 21:41:28 +00:00
Pete Cooper d987cd2f31 Constify AArch64CollectLOH.cpp. NFC
llvm-svn: 231969
2015-03-11 21:40:25 +00:00
Jozef Kolek 4468947fce [mips][microMIPS] Make usage of NOT16 by code generator
Differential Revision: http://reviews.llvm.org/D7748

llvm-svn: 231963
2015-03-11 20:28:31 +00:00
Tim Northover 8cda34f5e7 ARM: simplify and extend byval handling
The main issue being fixed here is that APCS targets handling a "byval align N"
parameter with N > 4 were miscounting what objects were where on the stack,
leading to FrameLowering setting the frame pointer incorrectly and clobbering
the stack.

But byval handling had grown over many years, and had multiple layers of cruft
trying to compensate for each other and calculate padding correctly. This only
really needs to be done once, in the HandleByVal function. Elsewhere should
just do what it's told by that call.

I also stripped out unnecessary APCS/AAPCS distinctions (now that Clang emits
byvals with the correct C ABI alignment), which simplified HandleByVal.

rdar://20095672

llvm-svn: 231959
2015-03-11 18:54:22 +00:00
Eric Christopher 6c5b511b4d Remove the need to cache the subtarget in the R600 TargetRegisterInfo
classes.

llvm-svn: 231954
2015-03-11 18:43:21 +00:00
Eric Christopher 4320495319 Have getRegPressureSetLimit take a MachineFunction so that a
we can inspect the subtarget and function when computing values.

llvm-svn: 231951
2015-03-11 18:34:58 +00:00
Kit Barton 116e18be41 Updated with list of possible improvements we are tracking internally
llvm-svn: 231946
2015-03-11 17:43:43 +00:00
Juergen Ributzka 0c598cdaf1 Add the "vbroadcasti128" instruction back.
This is a follow-up to r231182. This adds the "vbroadcasti128" instruction
back, but without the intrinsic mapping. Also add a test to check the
instriction encoding.

This is related to rdar://problem/18742778.

llvm-svn: 231945
2015-03-11 17:29:03 +00:00
Derek Schuff 072f93fe72 Make NaCl's use of .init_array for static constructors match Linux
Summary:
The generic ELF TargetObjectFile defaults to .ctors, but Linux's
defaults to .init_array by calling InitializeELF with the value of
UseInitArray from TargetMachine. Make NaCl's behavior match.

Reviewers: jvoung
Differential Revision: http://reviews.llvm.org/D8240

llvm-svn: 231934
2015-03-11 16:16:09 +00:00
Elena Demikhovsky 0b9dbe33aa AVX-512: Added SKX forms of shift instructions.
Added rotation instructions, encoding only.
Added encoding tests for all these forms.

llvm-svn: 231916
2015-03-11 10:25:42 +00:00
Eric Christopher 433c432b7e Have TargetRegisterInfo::getLargestLegalSuperClass take a
MachineFunction argument so that it can look up the subtarget
rather than using a cached one in some Targets.

llvm-svn: 231888
2015-03-10 23:46:01 +00:00
Eric Christopher c4d3140524 Remove subtarget dependence from HexagonRegisterInfo.
llvm-svn: 231887
2015-03-10 23:45:55 +00:00
Eric Christopher 49338e9fa6 Remove dead code.
llvm-svn: 231883
2015-03-10 23:22:04 +00:00
Eric Christopher 0169e42c3b Remove the use of the subtarget in MCCodeEmitter creation and
update all ports accordingly. Required a couple of small rewrites
in handling subtarget features during creation in PPC.

llvm-svn: 231861
2015-03-10 22:03:14 +00:00
Rafael Espindola 6b9998b3eb Create symbols marking the start of a section earlier.
This lets us pass the symbol to the constructor and avoid the mutable field.

This also opens the way for outputting the symbol only when needed, instead
of outputting them at the start of the file.

llvm-svn: 231859
2015-03-10 22:00:25 +00:00
Eric Christopher 501d5e9f66 Remove createAMDGPUMCCodeEmitter and instead just register the correct
MCCodeEmitter creation routine based on TargetMachine since the only
64-bit R600 gpus are part of the GCN target.

llvm-svn: 231856
2015-03-10 21:57:34 +00:00
Colin LeMahieu bdc6c83d24 [Hexagon] Adding frame index + add load/store patterns.
llvm-svn: 231850
2015-03-10 21:24:13 +00:00
Colin LeMahieu 3901c066e0 [Hexagon] Simplifying deallocret definitions.
llvm-svn: 231847
2015-03-10 21:12:32 +00:00
Colin LeMahieu 4e90d2136f [Hexagon] Separating InstHexagon from OpcodeHexagon.
llvm-svn: 231844
2015-03-10 20:56:22 +00:00
Nemanja Ivanovic 0adf26b9b0 Add support for part-word atomics for PPC
http://reviews.llvm.org/D8090#inline-67337

llvm-svn: 231843
2015-03-10 20:51:07 +00:00
Ahmed Bougacha fab5892f8b [AArch64] Avoid going through GPRs for across-vector instructions.
This adds new node types for each intrinsic.
For instance, for addv, we have AArch64ISD::UADDV, such that:
  (v4i32 (uaddv ...))
is the same as
  (v4i32 (scalar_to_vector (i32 (int_aarch64_neon_uaddv ...))))
that is,
  (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
           (i32 (int_aarch64_neon_uaddv ...)), ssub)

In a combine, we transform all such across-vector-lanes intrinsics to:

  (i32 (extract_vector_elt (uaddv ...), 0))

This has one big advantage: by making the extract_element explicit, we
enable the existing patterns for lane-aware instructions to fire.
This lets us avoid needlessly going through the GPRs.  Consider:

    uint32x4_t test_mul(uint32x4_t a, uint32x4_t b) {
        return vmulq_n_u32(a, vaddvq_u32(b));
    }

We now generate:
    addv.4s  s1, v1
    mul.4s   v0, v0, v1[0]
instead of the previous:
    addv.4s  s1, v1
    fmov     w8, s1
    dup.4s   v1, w8
    mul.4s   v0, v1, v0

rdar://20044838

llvm-svn: 231840
2015-03-10 20:45:38 +00:00
Ahmed Bougacha 8f6a115de9 [AArch64] Remove integer INSvi*lane patterns. NFCI.
Most are redundant, and they never seem to fire.

The V128 integer patterns already exist in the INS multiclass.
The duplicates only fire when the vector index type isn't i64,
because they accept "imm" instead of an explicit "i64", as the
instruction definition patterns do.

TLI::getVectorIdxTy is i64 on AArch64, so this should never happen.
Also, one of them had a typo: for i64, INSvi32lane was used.
I noticed because I mistakenly used an explicit i32 as the idx type,
and got ins.s for an i64 vector_insert.

The V64 patterns also don't seem to ever fire, as V64 vector
extract/insert are legalized to V128.

The equivalent float patterns are unique and useful, so keep them.

No functional change intended;  none exhibited on the LIT and LNT tests.

llvm-svn: 231838
2015-03-10 20:37:19 +00:00
Benjamin Kramer d58792f38b Don't use LLVM_LIBRARY_VISIBILITY in cpp files.
llvm-svn: 231831
2015-03-10 20:07:44 +00:00
Colin LeMahieu 60a99e66a0 [Hexagon] Adding nodes for PIC support.
llvm-svn: 231829
2015-03-10 20:04:44 +00:00
Colin LeMahieu 092d9c18a8 [Hexagon] Adding DuplexInst instruction format and duplex class defs.
llvm-svn: 231828
2015-03-10 19:53:14 +00:00
Kit Barton 20d3981e15 Change the generation of the vmuluwm instruction to be based on the MUL opcode.
Phabricator review: http://reviews.llvm.org/D8185

llvm-svn: 231827
2015-03-10 19:49:38 +00:00
Colin LeMahieu 3b6747df13 [Hexagon] Adding nodes for vector insert/extract lowering.
llvm-svn: 231825
2015-03-10 19:40:03 +00:00
Colin LeMahieu ee776452f9 [Hexagon] Renaming HexagonJT to JT and adding CP for constantpool.
llvm-svn: 231824
2015-03-10 19:29:53 +00:00
Benjamin Kramer 414c0964c3 NVPTX: move NVPTXAllocaHoisting into the cpp file
Also initialize without using static initialization.

llvm-svn: 231822
2015-03-10 19:20:52 +00:00
Benjamin Kramer 42a31e1f5e NVPTX: Remove copy of LLVMInitializeNVPTXAsmPrinter.
If anyone is using this for some strange reason,
LLVMInitializeNVPTXAsmPrinter does exactly the same thing and is what
other LLVM tools are calling.

llvm-svn: 231810
2015-03-10 18:19:24 +00:00
Benjamin Kramer 9d1f2dfec7 Hexagon: Remove unused InstrMapping.
llvm-svn: 231809
2015-03-10 18:19:16 +00:00
Tom Stellard a14b0114a3 R600/SI: Add _IDXEN and _BOTHEN variants for buffer_store
llvm-svn: 231798
2015-03-10 16:16:51 +00:00
Tom Stellard c229baa94c R600/SI: Re-order MUBUF operands to match asm strings.
llvm-svn: 231797
2015-03-10 16:16:49 +00:00
Tom Stellard 4d6c99ddf2 R600/SI: Move kill flag to second instruction when splitting SMRD
This fixes a machine verifier error in the salu-to-valu.ll, which
would have been exposed by a future commit.

llvm-svn: 231796
2015-03-10 16:16:48 +00:00
Tom Stellard 5224df36c8 R600/SI: Add 32-bit encoding of v_cndmask_b32
This was done by refactoring the v_cndmask_b32 tablegen definition
to use inherit from VOP2Inst.

llvm-svn: 231795
2015-03-10 16:16:44 +00:00
Benjamin Kramer 4683395808 Hexagon: Remove pass that does nothing at all
llvm-svn: 231791
2015-03-10 15:06:38 +00:00
Aaron Ballman f00fd1f087 Removing dead code to silence warning C4060: switch statement contains no 'case' or 'default' labels; NFC.
llvm-svn: 231785
2015-03-10 13:56:28 +00:00
Rafael Espindola 760bf9520a Remove incredibly confusing isBaseAddressKnownZero.
When referring to a symbol in a dwarf section on ELF we should use

.long foo

instead of

.long foo - .debug_something

because ELF is unaware of the content of the sections and therefore needs
relocations. This has nothing to do with optimizing a -0.

llvm-svn: 231751
2015-03-10 04:11:52 +00:00
Rafael Espindola fcc2821882 Use a better name for compile unit labels.
They mark the start of a compile unit, so name them .Lcu_*. Using
Section->getLabelBeginName() makes it looks like they mark the start of the
section.

While at it, switch to createTempSymbol to avoid collisions with labels
created in inline assembly. Not sure if a "don't crash" test is worth it.

With this getLabelBeginName is dead, delete it.

llvm-svn: 231750
2015-03-10 03:58:36 +00:00
Mehdi Amini a28d91d81b DataLayout is mandatory, update the API to reflect it with references.
Summary:
Now that the DataLayout is a mandatory part of the module, let's start
cleaning the codebase. This patch is a first attempt at doing that.

This patch is not exactly NFC as for instance some places were passing
a nullptr instead of the DataLayout, possibly just because there was a
default value on the DataLayout argument to many functions in the API.
Even though it is not purely NFC, there is no change in the
validation.

I turned as many pointer to DataLayout to references, this helped
figuring out all the places where a nullptr could come up.

I had initially a local version of this patch broken into over 30
independant, commits but some later commit were cleaning the API and
touching part of the code modified in the previous commits, so it
seemed cleaner without the intermediate state.

Test Plan:

Reviewers: echristo

Subscribers: llvm-commits

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 231740
2015-03-10 02:37:25 +00:00
Eric Christopher 33866f141c Remove an unused variable.
llvm-svn: 231730
2015-03-10 00:33:22 +00:00
Colin LeMahieu fa79110cc7 [Hexagon] Removing unused patterns.
llvm-svn: 231723
2015-03-09 23:08:46 +00:00
Colin LeMahieu 7b1799c7f8 [Hexagon] Use single tailcall pseudoinst and fix checking for label jumping versus tail calling.
llvm-svn: 231713
2015-03-09 22:05:21 +00:00
Colin LeMahieu 2efa2d01d7 [Hexagon] Reapply r231699. Remove assumption that second operand is an immediate when checking if A2_tfrsi is combinable.
llvm-svn: 231710
2015-03-09 21:48:13 +00:00
Colin LeMahieu ed853397c6 [Hexagon] Reverting r231699
llvm-svn: 231703
2015-03-09 21:19:02 +00:00
Colin LeMahieu 8c4dfaa13b [Hexagon] Updating constant set to simpler versions.
llvm-svn: 231699
2015-03-09 20:33:12 +00:00
Reid Kleckner 294fa7aa9d TableGen: Use 'enum : uint64_t' for feature flags to fix -Wmicrosoft
clang-cl would warn that this value is not representable in 'int':
  enum { FeatureX = 1ULL << 31 };
All MS enums are 'ints' unless otherwise specified, so we have to use an
explicit type.  The AMDGPU target just hit 32 features, triggering this
warning.

Now that we have C++11 strong enum types, we can also eliminate the
'const uint64_t' codepath from tablegen and just use 'enum : uint64_t'.

llvm-svn: 231697
2015-03-09 20:23:14 +00:00
Benjamin Kramer 7bd1f7cb58 Remove the remaining uses of abs64 and nuke it.
std::abs works just fine and we're already using it in many places. NFC intended.

llvm-svn: 231696
2015-03-09 20:20:16 +00:00
Colin LeMahieu 542510925b [Hexagon] Removing old halfword codegen instructions and updating const32/64 splitting.
llvm-svn: 231695
2015-03-09 20:11:02 +00:00
Colin LeMahieu 96bfaa9766 [Hexagon] Eliminating immediate condition set.
llvm-svn: 231693
2015-03-09 19:57:18 +00:00
Colin LeMahieu d46aeffc54 [Hexagon] Removing TFR_condset_ir/TFR_condset_ri modeling.
llvm-svn: 231689
2015-03-09 19:31:25 +00:00
Colin LeMahieu 63adf969a5 [Hexagon] Changing AddrFI back to ADDRri to address test issue.
llvm-svn: 231687
2015-03-09 18:57:33 +00:00
Tom Stellard 065e3d4cdb R600/SI: Move gds operand to the end of operand list
Also print it in the assembly string.

llvm-svn: 231684
2015-03-09 18:49:54 +00:00
Tom Stellard cf051f4112 R600/SI: Refactor DS instruction defs
llvm-svn: 231683
2015-03-09 18:49:45 +00:00
Rafael Espindola 028f8b43e2 Delete dead code. NFC.
llvm-svn: 231682
2015-03-09 18:48:29 +00:00
Colin LeMahieu bd8d0f3108 [Hexagon] Adding PackHL nodes and some missing modeling instructions and patterns
llvm-svn: 231678
2015-03-09 18:34:05 +00:00
Reed Kotler 07d3a2f6b2 Add logical ops to Mips fast-isel
Summary:
Code is mostly copied from AArch64 port and modified where needed for Mips.

This handles the "non" legal cases of logical ops. Legal cases are handled by tablegen patterns.

Test Plan:
Make check test logopm.ll

All of test-suite passes at O0/O2 and mips32 r1/r2 with this new change.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: echristo, llvm-commits, aemerson, rfuhler

Differential Revision: http://reviews.llvm.org/D6599

llvm-svn: 231665
2015-03-09 16:28:10 +00:00
Tom Stellard db4995a197 R600/SI: Fix DS definitions and add missing instructions
llvm-svn: 231663
2015-03-09 16:03:45 +00:00
Tom Stellard 968388cf45 R600/SI: Fix opcode for ds_read2_b64 and ds_read2st64_b64
llvm-svn: 231662
2015-03-09 16:03:39 +00:00
Benjamin Kramer a52f696e6f Move unreferenced passes into the cpp file
NFC.

llvm-svn: 231661
2015-03-09 15:50:58 +00:00
Marek Olsak 4d00dd2b93 R600/SI: Limit SGPRs to 80 on Tonga and Iceland
This is a candidate for stable.

llvm-svn: 231659
2015-03-09 15:48:09 +00:00
Marek Olsak f119679e2d R600/SI: Fix getNumSGPRsAllowed for VI
llvm-svn: 231658
2015-03-09 15:48:00 +00:00
Kevin Qin aef68418de [AArch64] Enable partial & runtime unrolling on cortex-a57
For inner one of nested loops, it is more likely to be a hot loop,
and the runtime check can be promoted out from patch 0001, so the
overhead is less, we can try a doubled threshold to unroll more loops.

llvm-svn: 231632
2015-03-09 06:14:28 +00:00
David Blaikie dc3f01e9cf Simplify expressions involving boolean constants with clang-tidy
Patch by Richard (legalize at xmission dot com).

Differential Revision: http://reviews.llvm.org/D8154

llvm-svn: 231617
2015-03-09 01:57:13 +00:00
Andrea Di Biagio 6c7d70469c [X86][AVX] Fix wrong lowering of VPERM2X128 nodes
There were cases where the backend computed a wrong permute mask for a VPERM2X128 node.

Example:
\code
define <8 x float> @foo(<8 x float> %a, <8 x float> %b) {
  %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 undef, i32 6, i32 7>
  ret <8 x float> %shuffle
}
\code end

Before this patch, llc (with -mattr=+avx) emitted the following vperm2f128:
  vperm2f128 $0, %ymm0, %ymm0, %ymm0  # ymm0 = ymm0[0,1,0,1]

With this patch, llc emits a vperm2f128 with a correct permute mask:
  vperm2f128 $17, %ymm0, %ymm0, %ymm0  # ymm0 = ymm0[2,3,2,3]

Differential Revision: http://reviews.llvm.org/D8119

llvm-svn: 231601
2015-03-08 16:28:47 +00:00
Benjamin Kramer 57a3d084cd Make static variables const if possible. Makes them go into a read-only section.
Or fold them into a initializer list which has the same effect. NFC.

llvm-svn: 231598
2015-03-08 16:07:39 +00:00
Simon Pilgrim 8c58c066b7 [DAGCombiner] Add a shuffle mask commutation helper function. NFCI.
We have an increasing number of cases where we are creating commuted shuffle masks - all implementing nearly the same code.

This patch adds a static helper function - ShuffleVectorSDNode::commuteMask() and replaces a number of cases to use it.

Differential Revision: http://reviews.llvm.org/D8139

llvm-svn: 231581
2015-03-07 22:33:11 +00:00
Benjamin Kramer 867bfc53ee Make constant arrays that are passed to functions as const.
In theory this allows the compiler to skip materializing the array on
the stack. In practice clang often fails to do that, but that's a
different story. NFC.

llvm-svn: 231571
2015-03-07 17:41:00 +00:00
Benjamin Kramer 4e0c7928e2 X86: Roll repetitive code into a loop. NFC.
llvm-svn: 231565
2015-03-07 15:06:16 +00:00
Eric Christopher 25dbdeb4d1 Typo.
llvm-svn: 231547
2015-03-07 01:39:09 +00:00
Eric Christopher 7e70aba1a8 Recommit r231324 with a fix to the ARM execution domain code
to disable lane switching if we don't actually have the instruction
set we want to switch to. Models the earlier check above the
conditional for the pass.

The testcase is one that triggered with the assert that's added
as part of the fix, use it to avoid adding a new testcase as it
highlights the same problem.

llvm-svn: 231539
2015-03-07 00:12:22 +00:00
Olivier Sallenave 049d803ce0 Do not restrict interleaved unrolling to small loops, depending on the target.
llvm-svn: 231528
2015-03-06 23:12:04 +00:00
Quentin Colombet 66b616351c [AArch64][LoadStoreOptimizer] Generate LDP + SXTW instead of LD[U]R + LD[U]RSW.
Teach the load store optimizer how to sign extend a result of a load pair when
it helps creating more pairs.
The rational is that loads are more expensive than sign extensions, so if we
gather some in one instruction this is better!

<rdar://problem/20072968>

llvm-svn: 231527
2015-03-06 22:42:10 +00:00
Tom Stellard 6b42f2d8aa R600/SI: Remove unused register class
llvm-svn: 231491
2015-03-06 17:00:16 +00:00
Bruno Cardoso Lopes 618c67a018 [AsmPrinter][TLOF] 32-bit MachO support for replacing GOT equivalents
Add MachO 32-bit (i.e. arm and x86) support for replacing global GOT equivalent
symbol accesses. Unlike 64-bit targets, there's no GOTPCREL relocation, and
access through a non_lazy_symbol_pointers section is used instead.

-- before

    _extgotequiv:
       .long _extfoo

    _delta:
       .long _extgotequiv-_delta

-- after

    _delta:
       .long L_extfoo$non_lazy_ptr-_delta

       .section __IMPORT,__pointers,non_lazy_symbol_pointers
    L_extfoo$non_lazy_ptr:
       .indirect_symbol _extfoo
       .long 0

llvm-svn: 231475
2015-03-06 13:49:05 +00:00
Bruno Cardoso Lopes 52b1391df6 [AsmPrinter][TLOF] ARM64 MachO support for replacing GOT equivalents
Follow up r230264 and add ARM64 support for replacing global GOT
equivalent symbol accesses by references to the GOT entry for the final
symbol instead, example:

-- before

   .globl  _foo
  _foo:
   .long   42

   .globl  _gotequivalent
  _gotequivalent:
   .quad   _foo

   .globl  _delta
  _delta:
   .long   _gotequivalent-_delta

-- after

   .globl  _foo
  _foo:
   .long   42

   .globl  _delta
  Ltmp3:
   .long _foo@GOT-Ltmp3

llvm-svn: 231474
2015-03-06 13:48:45 +00:00
Toma Tabacu 4e0cf8e211 [mips] [IAS] Add missing constraints and improve testing for the .module directive.
Summary:
None of the .set directives can be used before the .module directives. The .set mips0/pop/push were not triggering this constraint.
Also added testing for all the other implemented directives which are supposed to trigger this constraint.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7140

llvm-svn: 231465
2015-03-06 12:15:12 +00:00
David Majnemer b61f4e403d X86: Form IMGREL relocations for LLVM Functions
We supported forming IMGREL relocations from ConstantExprs involving
__ImageBase if the minuend was a GlobalVariable.  Extend this
functionality to all GlobalObjects.

llvm-svn: 231456
2015-03-06 08:11:32 +00:00
Ahmed Bougacha c6dcf7a7cc [X86] Remove stale comment. NFC.
It turns out 256bit V[SZ]EXT nodes are still
generated by the new shuffle lowering, so this
is here to stay!

llvm-svn: 231422
2015-03-05 23:18:41 +00:00
Sanjay Patel 302404b277 [AVX] Lower / fast-isel scalar FP selects into VBLENDV instructions (PR22483)
This patch reduces code size for all AVX targets and increases speed for some chips.

SSE 4.1 introduced the useless (see code comments) 2-register form of BLENDV and
only in the packed float/double flavors.

AVX subsequently made the instruction useful by adding a 4-register operand form.

So we just need to paper over the lack of scalar forms of this instruction, complicate
the code to choose float or double forms, and use blendv on scalars since all FP is in
xmm registers anyway.

This gives us an approximately 50% speed up for a blendv microbenchmark sequence
on SandyBridge and Haswell:
blendv : 29.73 cycles/iter
logic : 43.15 cycles/iter

No new test cases with this patch because:

1. fast-isel-select-sse.ll tests the positive side for regular X86 lowering and fast-isel
2. sse-minmax.ll and fp-select-cmp-and.ll confirm that we're not firing for scalar selects without AVX
3. fp-select-cmp-and.ll and logical-load-fold.ll confirm that we're not firing for scalar selects with constants.

http://llvm.org/bugs/show_bug.cgi?id=22483

Differential Revision: http://reviews.llvm.org/D8063

llvm-svn: 231408
2015-03-05 21:46:54 +00:00
Ahmed Bougacha 1b67630cb3 [AArch64] Teach AsmPrinter about GlobalAddress operands.
Fixes PR22761, rdar://20024866.
Differential Revision: http://reviews.llvm.org/D8042

llvm-svn: 231400
2015-03-05 20:04:21 +00:00
Rafael Espindola 092b619e55 Use the correct func begin symbol in all places in ppc.
I missed an occurrence of the old symbol in my previous patch.

llvm-svn: 231398
2015-03-05 19:47:50 +00:00
Ahmed Bougacha 4200cc95b4 [ARM] Enable vector extload combine for legal types.
This commit enables forming vector extloads for ARM.
It only does so for legal types, and when we can't fold the extension
in a wide/long form of the user instruction.

Enabling it for larger types isn't as good an idea on ARM as it is on
X86, because: 
- we pretend that extloads are legal, but end up generating vld+vmov
- we have instructions like vld {dN, dM}, which can't be generated
  when we "manually expand" extloads to vld+vmov.

For legal types, the combine doesn't fire that often: in the
integration tests only in a big endian testcase, where it removes a
pointless AND.

Related to rdar://19723053
Differential Revision: http://reviews.llvm.org/D7423

llvm-svn: 231396
2015-03-05 19:37:53 +00:00
Rafael Espindola 86bd6a1202 Use the generic Lfunc_begin label on ppc.
This removes yet another custom label to mark the start of a function.

llvm-svn: 231390
2015-03-05 18:55:50 +00:00
David Majnemer 71b9b6be1b X86: Optimize address mode matching for FRAME_ALLOC_RECOVER nodes
We know that the absolute symbol will be less than 2GB and thus will
always fit.

llvm-svn: 231389
2015-03-05 18:50:12 +00:00
Reid Kleckner cfb9ce53c1 Replace llvm.frameallocate with llvm.frameescape
Turns out it's pretty straightforward and simplifies the implementation.

Reviewers: andrew.w.kaylor

Differential Revision: http://reviews.llvm.org/D8051

llvm-svn: 231386
2015-03-05 18:26:34 +00:00
Kit Barton e48b1e1c4f While reviewing the changes to Clang to add builtin support for the vsld, vsrd, and vsrad instructions, it was pointed out that the builtins are generating the LLVM opcodes (shl, lshr, and ashr) not calls to the intrinsics. This patch changes the implementation of the vsld, vsrd, and vsrad instructions from from intrinsics to VXForm_1 instructions and makes them legal with P8 Altivec. It also removes the definition of the int_ppc_altivec_vsld, int_ppc_altivec_vsrd, and int_ppc_altivec_vsrad intrinsics.
llvm-svn: 231378
2015-03-05 16:24:38 +00:00
Elena Demikhovsky de05f10de2 AVX-512, SKX: Enabled masked_load/store operations for this target.
Added lowering for ISD::CONCAT_VECTORS and ISD::INSERT_SUBVECTOR for i1 vectors,
it is needed to pass all masked_memop.ll tests for SKX.

llvm-svn: 231371
2015-03-05 15:11:35 +00:00
Craig Topper 0ee8470a43 [X86] Use vmovss to handle inserting an element into index 0 of a v8f32 vector of zeros.
llvm-svn: 231354
2015-03-05 06:38:42 +00:00
Hans Wennborg 6d8e6d5ee4 Revert r231324 "Remove the conditional addition of the execution dependency fixing"
See PR22799.

llvm-svn: 231348
2015-03-05 03:24:49 +00:00
Eric Christopher 385f4b36d8 Remove the conditional addition of the execution dependency fixing
pass from the ARM backend as the pass itself will detect any use
of the appropriate register class.

llvm-svn: 231324
2015-03-05 00:28:55 +00:00
Eric Christopher 63b44882ef Cleanup and remove a chunk of getARMSubtarget calls in the
ARM TargetMachine pass pipeline construction by pushing them down
into the appropriate pass.

llvm-svn: 231323
2015-03-05 00:23:40 +00:00
Nemanja Ivanovic e8effe1edb Add LLVM support for PPC cryptography builtins
Review: http://reviews.llvm.org/D7955

llvm-svn: 231285
2015-03-04 20:44:33 +00:00
Mehdi Amini 46a43556db Make DataLayout Non-Optional in the Module
Summary:
DataLayout keeps the string used for its creation.

As a side effect it is no longer needed in the Module.
This is "almost" NFC, the string is no longer
canonicalized, you can't rely on two "equals" DataLayout
having the same string returned by getStringRepresentation().

Get rid of DataLayoutPass: the DataLayout is in the Module

The DataLayout is "per-module", let's enforce this by not
duplicating it more than necessary.
One more step toward non-optionality of the DataLayout in the
module.

Make DataLayout Non-Optional in the Module

Module->getDataLayout() will never returns nullptr anymore.

Reviewers: echristo

Subscribers: resistor, llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D7992

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 231270
2015-03-04 18:43:29 +00:00
Marek Olsak d2af89df10 R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32
Required by OpenGL (ARB_gpu_shader5).

llvm-svn: 231259
2015-03-04 17:33:45 +00:00
Nemanja Ivanovic d384cd9907 Test commit. Removed an unnecessary space
llvm-svn: 231257
2015-03-04 17:09:12 +00:00
JF Bastien f14889ee34 Mutate TargetLowering::shouldExpandAtomicRMWInIR to specifically dictate how AtomicRMWInsts are expanded.
Summary:
In PNaCl, most atomic instructions have their own @llvm.nacl.atomic.* function, each one, with a few exceptions, represents a consistent behaviour across all NaCl-supported targets. Unfortunately, the atomic RMW operations nand, [u]min, and [u]max aren't directly represented by any such @llvm.nacl.atomic.* function. This patch refines shouldExpandAtomicRMWInIR in TargetLowering so that a future `Le32TargetLowering` class can selectively inform the caller how the target desires the atomic RMW instruction to be expanded (ie via load-linked/store-conditional for ARM/AArch64, via cmpxchg for X86/others?, or not at all for Mips) if at all.

This does not represent a behavioural change and as such no tests were added.

Patch by: Richard Diamond.

Reviewers: jfb

Reviewed By: jfb

Subscribers: jfb, aemerson, t.p.northover, llvm-commits

Differential Revision: http://reviews.llvm.org/D7713

llvm-svn: 231250
2015-03-04 15:47:57 +00:00
Jozef Kolek c925808ee5 [mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator
Differential Revision: http://reviews.llvm.org/D7609

llvm-svn: 231249
2015-03-04 15:47:42 +00:00
Bill Schmidt d90aff2c4f [PowerPC] Remove unnecessary and incomplete commentary
This "itinerary class map" in PPCSchedule.td is incomplete and
redundant with the actual code.  As it provides no value, we've
decided to remove it.

No functional change.

llvm-svn: 231246
2015-03-04 14:56:05 +00:00
Andrea Di Biagio df93ccf49a [X86][FastISel] Simplify the logic in method X86SelectSIToFP.
The target-independent selection algorithm in FastISel already knows how
to select a SINT_TO_FP if the target is SSE but not AVX.

On targets that have SSE but not AVX, the tablegen'd 'fastEmit' functions
for ISD::SINT_TO_FP know how to select instruction X86::CVTSI2SSrr
(for an i32 to f32 conversion) and X86::CVTSI2SDrr (for an i32 to f64
conversion).

This patch simplifies the logic in method X86SelectSIToFP knowing that
the code would not be reachable if the subtarget doesn't have AVX.
No functional change intended.

llvm-svn: 231243
2015-03-04 14:23:25 +00:00
Toma Tabacu e1e3ffe71d [mips] Rename the LA/LI/DLI TableGen definitions and classes. NFC.
Summary:
Use more reasonable names for these pseudo-instructions.
As there's only one definition tied to any one of these classes, I named them with abbreviated versions of their respective class' name.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7831

llvm-svn: 231240
2015-03-04 13:01:14 +00:00
Vasileios Kalintiris 8761490d2e [mips] Keep the parameter list of Filler::searchRange() consistent. NFC.
Summary:
Move the "Filler" parameter to the end of the parameter list as it is,
conceptually, the only output parameter of that function.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7726

llvm-svn: 231239
2015-03-04 12:37:58 +00:00
Vasileios Kalintiris 2ef2888273 [mips] Specify the correct value type when combining a CMovFP node.
This commit fixes a bug introduced in r230956 where we were creating
CMovFP_{T,F} nodes with multiple return value types (one for each operand).
With this change the return value type of the new node is the same as the
value type of the True/False operands of the original node.

llvm-svn: 231237
2015-03-04 12:10:18 +00:00
Kristof Beyls aea8461820 Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers cannot handle yet.
As is described at http://llvm.org/bugs/show_bug.cgi?id=22408, the GNU linkers
ld.bfd and ld.gold currently only support a subset of the whole range of AArch64
ELF TLS relocations. Furthermore, they assume that some of the code sequences to
access thread-local variables are produced in a very specific sequence.
When the sequence is not as the linker expects, it can silently mis-relaxe/mis-optimize
the instructions.
Even if that wouldn't be the case, it's good to produce the exact sequence,
as that ensures that linkers can perform optimizing relaxations.

This patch:

* implements support for 16MiB TLS area size instead of 4GiB TLS area size. Ideally clang
  would grow an -mtls-size option to allow support for both, but that's not part of this patch.
* by default doesn't produce local dynamic access patterns, as even modern ld.bfd and ld.gold
  linkers do not support the associated relocations. An option (-aarch64-elf-ldtls-generation)
  is added to enable generation of local dynamic code sequence, but is off by default.
* makes sure that the exact expected code sequence for local dynamic and general dynamic
  accesses is produced, by making use of a new pseudo instruction. The patch also removes
  two (AArch64ISD::TLSDESC_BLR, AArch64ISD::TLSDESC_CALL) pre-existing AArch64-specific pseudo
  SDNode instructions that are superseded by the new one (TLSDESC_CALLSEQ).

llvm-svn: 231227
2015-03-04 09:12:08 +00:00
Davide Italiano fcae934c03 [MC][Target] Implement support for R_X86_64_SIZE{32,64}.
Differential Revision:	D7990
Reviewed by:	rafael, majnemer

llvm-svn: 231216
2015-03-04 06:49:39 +00:00
Pete Cooper ef21bd444d Remove MCStreamer.h include from MCContext.h and explictly include it where necessary. NFC
llvm-svn: 231193
2015-03-04 01:24:11 +00:00
Juergen Ributzka 1f7a17661c Remove 'llvm.x86.avx2.vbroadcasti128' intrinsic.
The intrinsic is no longer generated by the front-end. Remove the intrinsic and
auto-upgrade it to a vector shuffle.

Reviewed by Nadav

This is related to rdar://problem/18742778.

llvm-svn: 231182
2015-03-04 00:13:25 +00:00
Eric Christopher 6f1e5680f6 Remove subtarget dependence in pass pipeline setup for AArch64.
llvm-svn: 231165
2015-03-03 23:22:40 +00:00
David Blaikie 01a9a412a7 Avoid copying LiveInterval, this could lead to a double-delete
llvm-svn: 231154
2015-03-03 22:25:48 +00:00
David Blaikie 7f1e0565b3 Revert "Remove the explicit SDNodeIterator::operator= in favor of the implicit default"
Accidentally committed a few more of these cleanup changes than
intended. Still breaking these out & tidying them up.

This reverts commit r231135.

llvm-svn: 231136
2015-03-03 21:18:16 +00:00
David Blaikie bb8da4c08f Remove the explicit SDNodeIterator::operator= in favor of the implicit default
There doesn't seem to be any need to assert that iterator assignment is
between iterators over the same node - if you want to reuse an iterator
variable to iterate another node, that's perfectly acceptable. Just
don't mix comparisons between iterators into disjoint sequences, as
usual.

llvm-svn: 231135
2015-03-03 21:17:08 +00:00
Paul Robinson 06a8eb8343 [X86][ELF] Correct relocation for DWARF TLS references
Previously we had only Linux using DTPOFF for these; all X86 ELF
targets should. Fixes a side issue mentioned in PR21077.

Differential Revision: http://reviews.llvm.org/D8011

llvm-svn: 231130
2015-03-03 21:01:27 +00:00
Sanjay Patel 36a2dc895f remove enum value names from comments; NFC
llvm-svn: 231129
2015-03-03 20:58:35 +00:00
Sanjay Patel 948602bd17 use bool operator shortcut; NFC
llvm-svn: 231123
2015-03-03 20:41:27 +00:00
Kit Barton 0cfa7b7ad0 Add the following 64-bit vector integer arithmetic instructions added in POWER8:
vaddudm
vsubudm
vmulesw
vmulosw
vmuleuw
vmulouw
vmuluwm
vmaxsd
vmaxud
vminsd
vminud
vcmpequd
vcmpequd.
vcmpgtsd
vcmpgtsd.
vcmpgtud
vcmpgtud.
vrld
vsld
vsrd
vsrad

Phabricator review: http://reviews.llvm.org/D7959

llvm-svn: 231115
2015-03-03 19:55:45 +00:00
Eric Christopher 43768e311c 80-column fixup.
llvm-svn: 231088
2015-03-03 17:54:39 +00:00
Chad Rosier 8e38f30e49 [AArch64] When combining constant mul of -3, prefer (sub x, (shl x, N)).
This change only effects codegen when the constant is -3.

llvm-svn: 231085
2015-03-03 17:31:01 +00:00
Michael Kuperstein 84dff4c94c [X86][Haswell][SchedModel] Fix patterns for scalar FMA3 variants.
llvm-svn: 231073
2015-03-03 15:47:02 +00:00
Elena Demikhovsky d207f17fa1 AVX-512: Moved patterns for masked load/store under avx_store, avx_load classes.
No functional changes.

llvm-svn: 231069
2015-03-03 15:03:35 +00:00
Craig Topper ef04b2b505 [X86] Remove some unused code from disassembler.
llvm-svn: 231055
2015-03-03 05:24:03 +00:00
Ahmed Bougacha afbd6887c4 [X86] Special-case 2x CMOV when custom-inserting.
This lets us avoid a few copies that are otherwise hard to get rid of.
The way this is done is, the custom-inserter looks at the following
instruction for another CMOV, and replaces both at the same time.
A previous version used a new CMOV2 opcode, but the custom inserter
is expected to be able to return a different basic block anyway, which
means it's OK - though far from ideal - to alter that block's contents.
Explicitly document that, in case it ever makes a difference.
Alternatives welcome!

Follow-up to r231045.

rdar://19767934
Closes http://reviews.llvm.org/D8019

llvm-svn: 231046
2015-03-03 01:21:16 +00:00
Ahmed Bougacha 066d0b8e64 [X86] Combine (cmov (and/or (setcc) (setcc))) into (cmov (cmov)).
Fold and/or of setcc's to double CMOV:

(CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
(CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)

When we can't use the CMOV instruction, it might increase branch
mispredicts.  When we can, or when there is no mispredict, this
improves throughput and reduces register pressure.

These can't be catched by generic combines, because the pattern can
appear when legalizing some instructions (such as fcmp une).

rdar://19767934
http://reviews.llvm.org/D7634

llvm-svn: 231045
2015-03-03 01:09:14 +00:00
Paul Robinson c583abc888 Remove useless .debug_macinfo section setup.
llvm-svn: 231001
2015-03-02 19:52:42 +00:00
Jan Vesely 468e055f54 R600: Use c++11 style for loop
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>
llvm-svn: 230987
2015-03-02 18:56:52 +00:00
Paul Robinson 9f4cfc574e Revert r230979, should apply to all X86 ELF.
llvm-svn: 230985
2015-03-02 18:50:18 +00:00
Paul Robinson 10ae2e52de [PS4] Correct relocation for DWARF TLS references.
llvm-svn: 230979
2015-03-02 17:44:52 +00:00
Elena Demikhovsky 18fd49602b AVX-512: Add assembly parser support for Rounding mode
By Asaf Badouh <asaf.badouh@intel.com>

llvm-svn: 230962
2015-03-02 15:00:34 +00:00
Benjamin Kramer e86b0f186b NVPTX: Remove dead code.
Fun fact: This file was never referenced since the initial checkin of
the NVPTX backend.

llvm-svn: 230957
2015-03-02 13:16:28 +00:00
Vasileios Kalintiris e741eb2c7d [mips] Optimize conditional moves where RHS is zero.
Summary:
When the RHS of a conditional move node is zero, we can utilize the $zero
register by inverting the conditional move instruction and by swapping the
order of its True/False operands.

Reviewers: dsanders

Differential Revision: http://reviews.llvm.org/D7945

llvm-svn: 230956
2015-03-02 12:47:32 +00:00
Elena Demikhovsky 2689d78909 AVX-512: Simplified MOV patterns, no functional changes.
llvm-svn: 230954
2015-03-02 12:46:21 +00:00
Craig Topper 9c26bcca5a [X86] There are only 8 mask registers. Fail disassembly if instruction tries to reference more.
llvm-svn: 230931
2015-03-02 03:33:11 +00:00
Craig Topper 09b27e7b24 [X86] Fix diassembler crash on AVX512 cmpps/cmppd with immediate that doesn't fit in 5-bits. Fixes PR22743.
llvm-svn: 230924
2015-03-02 00:22:29 +00:00
Sanjoy Das e5d1466ab3 [AArch64] fix an invalid-iterator-use bug.
Summary:
In AArch64PromoteConstant::appendAndTransferDominatedUses,
`InsertPts[NewPt]` invalidates IPI.  Therefore, `InsertPts[NewPt] =
std::move(IPI->second)` is not legal.

This was caught by running `make check` with
http://reviews.llvm.org/D7931.

Reviewers: t.p.northover, grosbach, bkramer

Reviewed By: bkramer

Subscribers: aemerson, llvm-commits

Differential Revision: http://reviews.llvm.org/D7988

llvm-svn: 230923
2015-03-02 00:17:18 +00:00
Benjamin Kramer 42cc33e816 X86: Replace variadic function with init list. NFC.
llvm-svn: 230911
2015-03-01 21:47:40 +00:00
Benjamin Kramer 030133c5db ArrayRef: Remove the equals helper with many arguments.
With initializer lists there is a really neat idiomatic way to write
this, 'ArrayRef.equals({1, 2, 3, 4, 5})'. Remove the equal method which
always had a hard limit on the number of arguments. I considered
rewriting it with variadic templates but that's not really a good fit
for a function with homogeneous arguments.

'ArrayRef == {1, 2, 3, 4, 5}' would've been even more awesome, but C++11
doesn't allow init lists with binary operators.

llvm-svn: 230907
2015-03-01 21:05:05 +00:00
Benjamin Kramer 7149aabf8b Make some non-constant static variables non-static or fully const.
Otherwise we have to emit thread-safe initialization for them. NFC.

llvm-svn: 230894
2015-03-01 18:09:56 +00:00
Elena Demikhovsky 0995479e67 Reverted 230471 - gather scatter handling in table gen.
llvm-svn: 230892
2015-03-01 08:23:41 +00:00
Elena Demikhovsky 02ffd26023 AVX-512: Added mask and rounding mode for scalar arithmetics
Added more tests for scalar instructions to destinguish between AVX and AVX-512 forms.

llvm-svn: 230891
2015-03-01 07:44:04 +00:00
Craig Topper 782d620657 [X86] Remove the blendpd/blendps/pblendw/pblendd intrinsics. They can represented by shuffle_vector instructions.
llvm-svn: 230860
2015-02-28 19:33:17 +00:00
Alexei Starovoitov 1b7b56fbcc bpf: fix build
complete the plumbing of passing TargetRegisterInfo through
computeRegisterProperties started by r230583

llvm-svn: 230858
2015-02-28 18:03:04 +00:00
Benjamin Kramer 5fbfe2ffdc Convert push_back loops into append calls.
No functionality change intended.

llvm-svn: 230849
2015-02-28 13:20:15 +00:00
Benjamin Kramer f1362f6196 ArrayRefize memory operand folding. NFC.
llvm-svn: 230846
2015-02-28 12:04:00 +00:00
Benjamin Kramer 4f6ac16292 Replace std::copy with a back inserter with vector append where feasible
All of the cases were just appending from random access iterators to a
vector. Using insert/append can grow the vector to the perfect size
directly and moves the growing out of the loop. No intended functionalty
change.

llvm-svn: 230845
2015-02-28 10:11:12 +00:00
Bill Schmidt e3959eb54e [PowerPC] Fix PR22711 - Misaligned .toc section
Straightforward patch to emit an alignment directive when emitting a
TOC entry.  The test case was generated from the test in PR22711 that
demonstrated a misaligned .toc section.  The object code is run
through llvm-readobj to verify that the correct alignment has been
applied to the .toc section.

Thanks to Ulrich Weigand for running down where the fix was needed.

llvm-svn: 230801
2015-02-27 22:14:10 +00:00
Charles Davis 83687fb9e6 Target/X86: Never use the redzone for Win64 ABI functions.
Summary:
Until now, we did this (among other things) based on whether or not the
target was Windows. This is clearly wrong, not just for Win64 ABI functions
on non-Windows, but for System V ABI functions on Windows, too. In this
change, we make this decision based on the ABI the calling convention
specifies instead.

Reviewers: rnk

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7953

llvm-svn: 230793
2015-02-27 21:11:16 +00:00
Hal Finkel 5c3cacf5c0 [PowerPC] Use vector types for memcpy and friends (sometimes)
When using Altivec, we can use vector loads and stores for aligned memcpy and
friends. Starting with the P7 and VXS, we have reasonable unaligned vector
stores. Starting with the P8, we have fast unaligned loads too.

For QPX, we use vector loads are stores, but only for aligned memory accesses.

llvm-svn: 230788
2015-02-27 19:58:28 +00:00
Renato Golin a78995c0a0 Equally to NetBSD, Bitrig/ARM uses the Itanium-ABI.
Patch by Patrick Wildt.

llvm-svn: 230762
2015-02-27 16:35:27 +00:00
Zoran Jovanovic 71a33e2ad6 [mips][microMIPS] Change register class for GP register
Differential Revision: http://reviews.llvm.org/D7934

llvm-svn: 230760
2015-02-27 15:03:50 +00:00
Tom Stellard aec94b3bf3 R600/SI: Add missing mubuf instructions
llvm-svn: 230759
2015-02-27 14:59:46 +00:00
Tom Stellard 49282c92c5 R600/SI: Consistently put soffset before the offset operand for mubuf instructions
This matches the assembly syntax.

llvm-svn: 230758
2015-02-27 14:59:44 +00:00
Tom Stellard 1f9939fba6 R600/SI: Add slc, glc, and tfe to non-atomic _ADDR64 instructions
llvm-svn: 230757
2015-02-27 14:59:41 +00:00
Chandler Carruth 9ad2ffac23 [x86] Run most of the rest of the shuffle combining over non-128-bit
vectors. This lets us fix the rest of the v16 lowering problems when
pshufb is clearly better.

We might still be able to improve some of the lowerings by enabling the
other combine-based rewriting to fire for non-128-bit vectors, but this
at least should remove any regressions from using the fancy v16i16
lowering strategy.

llvm-svn: 230753
2015-02-27 12:13:14 +00:00
Chandler Carruth 66b705bc64 [x86] Teach a bunch of the x86-specific shuffle combining to work with
256-bit vectors as well as 128-bit vectors. Fixes some of the redundant
shuffles for v16i16.

llvm-svn: 230752
2015-02-27 11:45:13 +00:00
Chandler Carruth 97f3260f57 [x86] Make the v8i16 clever single-input shuffle lowering usable for
repeated 128-bit lane shuffles of wider vector types and use it to lower
256-bit v16i16 vector shuffles where applicable.

This should let us perfectly lowering the pattern of pshuflw and pshufhw
even for AVX2 256-bit patterns.

I've not added AVX-512 support, but it should be trivial for someone
working on that to wire up.

Note that currently this generates bad, long shuffle chains because we
don't combine 256-bit target shuffles. The subsequent patches will fix
that.

llvm-svn: 230751
2015-02-27 11:33:46 +00:00
Toma Tabacu 344c167436 [mips] Remove redundant periods from -mattr=help descriptions for MIPS.
Summary: Also fixes an infringement of the 80-column limit rule.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7910

llvm-svn: 230748
2015-02-27 10:44:02 +00:00
Chandler Carruth ddc4d085cc [x86] Make the single-input v8i16 lowering directly recurse rather than
going back through the entire vector shuffle lowering.

This is an important step to being able to re-use this logic.

llvm-svn: 230743
2015-02-27 09:11:38 +00:00
Vasileios Kalintiris 18581f16b4 [mips] Account for constant-zero operands in ADDE nodes.
Summary:
We identify the cases where the operand to an ADDE node is a constant
zero. In such cases, we can avoid generating an extra ADDu instruction
disguised as an identity move alias (ie. addu $r, $r, 0 --> move $r, $r).

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7906

llvm-svn: 230742
2015-02-27 09:01:39 +00:00
Charles Davis 84d28de627 Target/X86: Save Win64 non-volatile registers in a Win64 ABI function.
Summary:
This change causes us to actually save non-volatile registers in a Win64
ABI function that calls a System V ABI function, and vice-versa.

Reviewers: rnk

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7919

llvm-svn: 230714
2015-02-27 00:57:01 +00:00
Eric Christopher 1cdefae9c4 Rewrite MachineOperand::print and MachineInstr::print to avoid
uses of TM->getSubtargetImpl and propagate to all calls.

This could be a debugging regression in places where we had a
TargetMachine and/or MachineFunction but don't have it as part
of the MachineInstr. Fixing this would require passing a
MachineFunction/Function down through the print operator, but
none of the existing uses in tree seem to do this.

llvm-svn: 230710
2015-02-27 00:11:34 +00:00
Eric Christopher 11e4df73c8 getRegForInlineAsmConstraint wants to use TargetRegisterInfo for
a lookup, pass that in rather than use a naked call to getSubtargetImpl.
This involved passing down and around either a TargetMachine or
TargetRegisterInfo. Update all callers/definitions around the targets
and SelectionDAG.

llvm-svn: 230699
2015-02-26 22:38:43 +00:00
Chandler Carruth 653773d004 [x86] Fix PR22706 where we would incorrectly try lower a v32i8 dynamic
blend as legal.

We made the same mistake in two different places. Whenever we are custom
lowering a v32i8 blend we need to check whether we are custom lowering
it only for constant conditions that can be shuffled, or whether we
actually have AVX2 and full dynamic blending support on bytes. Both are
fixed, with comments added to make it clear what is going on and a new
test case.

llvm-svn: 230695
2015-02-26 22:15:34 +00:00
Chandler Carruth 7bd840d058 [x86] Restructure the comments and the conditions for handling
dynamic blends.

This makes it much more clear what is going on. The case we're handling
is that of dynamic conditions, and we're bailing when the nature of the
vector types and subtarget preclude lowering the dynamic condition
vselect as an actual blend.

No functionality changed here, but this will make a subsequent bug-fix
to this code much more clear.

llvm-svn: 230690
2015-02-26 21:29:06 +00:00
Chandler Carruth efc6819041 [x86] Re-order the combines of select in the X86 backend. This doesn't
change functionality, but makes it more clear that the dynamic case and
the shuffle case don't overlap in any interesting way.

llvm-svn: 230689
2015-02-26 21:21:36 +00:00
Chandler Carruth 0757f14c69 [x86] Add an assert to catch if we ever try to blend a v32i8 without
AVX2.

llvm-svn: 230688
2015-02-26 21:18:20 +00:00
Reid Kleckner e81017248c Don't sibcall between SysV and Win64 convention functions
The shadow stack space expectations won't match.

Fixes PR22709.

llvm-svn: 230667
2015-02-26 19:43:20 +00:00
Petar Jovanovic 90ec1b175e Fix justify error for small structures in varargs for MIPS64BE
There was a problem when passing structures as variable arguments.
The structures smaller than 64 bit were not left justified on MIPS64
big endian. This is now fixed by shifting the value to make it left-
justified when appropriate.

This fixes the bug http://llvm.org/bugs/show_bug.cgi?id=21608

Patch by Aleksandar Beserminji.

Differential Revision: http://reviews.llvm.org/D7881

llvm-svn: 230657
2015-02-26 18:35:15 +00:00
Sumanth Gundapaneni 28a3b86b06 Use ".arch_extension" ARM directive to support hwdiv on krait
In case of "krait" CPU, asm printer doesn't emit any ".cpu" so the
features bits are not computed. This patch lets the asm printer
emit ".cpu cortex-a9" directive for krait and the hwdiv feature is
enabled through ".arch_extension". In short, krait is treated
as "cortex-a9" with hwdiv. We can not emit ".krait" as CPU since
it is not supported bu GNU GAS yet

llvm-svn: 230651
2015-02-26 18:08:41 +00:00
Sumanth Gundapaneni a9049ea368 Use ".arch_extension" ARM directive to specify the additional CPU features
This patch is in response to r223147 where the avaiable features are
computed based on ".cpu" directive. This will work clean for the standard
variants like cortex-a9. For custom variants which rely on standard cpu names
for assembly, the additional features of a CPU should be propagated. This can be
done via ".arch_extension" as long as the assembler supports it. The
implementation for krait along with unit test will be submitted in next patch.

llvm-svn: 230650
2015-02-26 18:07:35 +00:00
Tom Stellard eb05c610b4 R600/SI: Remove M0 from DS assembly strings
This matches the assembly syntax for the proprietary compiler.

llvm-svn: 230645
2015-02-26 17:08:43 +00:00
Michael Kuperstein 4af7449659 [X86][Haswell][SchedModel] Fix WriteMULm latency.
The latency for the WriteMULm class was set to 4, which is actually lower than the latency for WriteMULr (5). 
A better estimate would be 4 added to WriteMULr, that is, 9.

llvm-svn: 230634
2015-02-26 14:30:09 +00:00
Chandler Carruth 8e0a3ea52c [x86] Sink the single-input v8i16 lowering code that is actually
formulaic into the top v8i16 lowering routine.

This makes the generalized lowering a completely general and single path
lowering which will allow generalizing it in turn for multiple 128-bit
lanes.

llvm-svn: 230623
2015-02-26 11:00:40 +00:00
Chandler Carruth 11e7f6b50a [x86] Remove a SimpleTy usage. No need for it here, we already have the
MVT.

llvm-svn: 230622
2015-02-26 10:37:01 +00:00
Chandler Carruth d283cb6203 [x86] Make the vector shuffle helpers order the SDLoc and MVT arguments.
This ordering matches that of DAG.getNode.

llvm-svn: 230617
2015-02-26 08:19:24 +00:00