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192 Commits

Author SHA1 Message Date
Dan Gohman dfc96aea90 Remove the SystemZ backend. 
llvm-svn: 142878
 2011-10-24 23:48:32 +00:00
Jakob Stoklund Olesen d9444d455e Ban rematerializable instructions with side effects. 
TableGen infers unmodeled side effects on instructions without a
pattern.  Fix some instruction definitions where that was overlooked.

Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.

llvm-svn: 141929
 2011-10-14 01:00:49 +00:00
Anton Korobeynikov 1f3bc9b5e6 Fix imm printing for logical instructions. 
Patch by Brian G. Lucas!

llvm-svn: 124679
 2011-02-01 20:22:53 +00:00
Chris Lattner 2a0a3b43d7 Flag -> Glue, the ongoing saga 
llvm-svn: 122513
 2010-12-23 18:28:41 +00:00
Eric Christopher 6dd51a2bb6 Remove isTwoAddress from SystemZ. 
llvm-svn: 106467
 2010-06-21 20:25:57 +00:00
Jakob Stoklund Olesen e02996ca8f Merge the SystemZ subreg_even32 SubRegIndex into subreg_32bit. The SubRegIndices 
were overspecified when inheriting sub-subregisters, for instance:

R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit.

This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous.

llvm-svn: 105063
 2010-05-28 23:48:29 +00:00
Chris Lattner a520b166dc Improve systemz to model cmp and ucmp nodes as returning 
their flags correctly.

llvm-svn: 99738
 2010-03-28 05:21:52 +00:00
Chris Lattner 0433699ef0 set SDNPVariadic on nodes throughout the rest of the targets that 
need them.

llvm-svn: 98937
 2010-03-19 05:33:51 +00:00
Chris Lattner 6742f1f338 fix a type compatibility bug. imm is i32 in the input 
pattern, not i64.

llvm-svn: 97956
 2010-03-08 18:52:55 +00:00
Dan Gohman 8c5d683aa9 The mayHaveSideEffects flag is no longer used. 
llvm-svn: 97348
 2010-02-27 23:47:46 +00:00
Dan Gohman 453d64c9f5 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
 2009-10-29 18:10:34 +00:00
Dan Gohman 9c6bc1f563 Update SystemZ to use PSW following the way x86 uses EFLAGS. Besides 
eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen
change.

This unfortunately requires SystemZ to switch to the list-burr
scheduler, in order to handle the physreg defs properly, however
that's what LLVM has available at this time.

llvm-svn: 85357
 2009-10-28 00:55:57 +00:00
Anton Korobeynikov f0d31ab7b8 Some dummy cost model for s390x: 
- Prefer short-imm instructions over ext-imm, when possible
 - Prefer Z10 instructions over Z9, when possible

This hopefully should fix some dejagnu test fails on solaris

llvm-svn: 79741
 2009-08-22 11:46:16 +00:00
Anton Korobeynikov cb7444342b Typo :( 
llvm-svn: 79657
 2009-08-21 18:41:02 +00:00
Anton Korobeynikov 81be4b345a Correct instruction names for subtract-with-borrow 
llvm-svn: 79656
 2009-08-21 18:37:28 +00:00
Anton Korobeynikov be47ccffef Convert bswap test to filecheck, add more test entries & convert stuff to filecheck 
llvm-svn: 78212
 2009-08-05 16:50:53 +00:00
Anton Korobeynikov 2e627cb37f Add memory versions of some instructions. 
Patch by Neale Ferguson!

llvm-svn: 78203
 2009-08-05 16:16:11 +00:00
Anton Korobeynikov 0ef680bcbd Add carry producing / using versions of add / sub 
llvm-svn: 76316
 2009-07-18 14:16:06 +00:00
Anton Korobeynikov 39f2a22401 Provide expansion for ct* intrinsics 
llvm-svn: 76311
 2009-07-18 12:26:13 +00:00
Anton Korobeynikov 73fcd3d962 Temporary disable 16 bit bswap 
llvm-svn: 76063
 2009-07-16 14:35:57 +00:00
Anton Korobeynikov 460e59034b Add instruction formats and few opcodes 
llvm-svn: 76062
 2009-07-16 14:35:20 +00:00
Anton Korobeynikov 902facfe96 Add bswap patterns 
llvm-svn: 76061
 2009-07-16 14:34:52 +00:00
Anton Korobeynikov ff21565821 Provide crazy pseudos for regpairs spills / reloads 
llvm-svn: 76060
 2009-07-16 14:34:15 +00:00
Anton Korobeynikov bd41c83ab0 Revert the commit, it just hides the real bug 
llvm-svn: 76045
 2009-07-16 14:28:26 +00:00
Anton Korobeynikov 6fb6e09781 Out GR128 regclass is not a 'real' i128 one. 
llvm-svn: 76044
 2009-07-16 14:27:53 +00:00
Anton Korobeynikov 6c01db428f Handle bitconverts 
llvm-svn: 76042
 2009-07-16 14:27:01 +00:00
Anton Korobeynikov 2acdac0f8e Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension side effects 
llvm-svn: 76035
 2009-07-16 14:24:41 +00:00
Anton Korobeynikov b106b60456 Handle FP callee-saved regs 
llvm-svn: 76029
 2009-07-16 14:23:01 +00:00
Anton Korobeynikov ead9b9fb31 Implement all comparisons 
llvm-svn: 76017
 2009-07-16 14:19:54 +00:00
Anton Korobeynikov 7cb00653c1 Add constpool lowering / printing 
llvm-svn: 76016
 2009-07-16 14:19:35 +00:00
Anton Korobeynikov 570d0c36ee Fix fallout from prev. patch 
llvm-svn: 76012
 2009-07-16 14:18:31 +00:00
Anton Korobeynikov e5b04d7102 Use divide single for 32 bit signed divides 
llvm-svn: 76010
 2009-07-16 14:17:52 +00:00
Anton Korobeynikov 091872cb37 Implement 'large' PIC model 
llvm-svn: 76006
 2009-07-16 14:16:05 +00:00
Anton Korobeynikov 569a94c4d0 Implement shifts properly (hopefilly - finally!) 
llvm-svn: 76005
 2009-07-16 14:15:24 +00:00
Anton Korobeynikov e0ad108f04 Remove redundand register move 
llvm-svn: 76004
 2009-07-16 14:14:54 +00:00
Anton Korobeynikov fe8df8ff61 Properly handle divides. As a bonus - implement memory versions of them. 
llvm-svn: 76003
 2009-07-16 14:14:33 +00:00
Anton Korobeynikov 68b101a0e1 Fix epic fail: full-width muls are not commutable. This unbreaks bunch of stuff from SingleSource/Benchmarks/Stanford 
llvm-svn: 76002
 2009-07-16 14:14:01 +00:00
Anton Korobeynikov 1de4295372 32 bit rotate is not twoaddr instruction 
llvm-svn: 76001
 2009-07-16 14:13:43 +00:00
Anton Korobeynikov 34ad780d0d 32 bit shifts have only 12 bit displacements 
llvm-svn: 76000
 2009-07-16 14:13:24 +00:00
Anton Korobeynikov 6f3d11cf0b Unbreak indirect branches 
llvm-svn: 75997
 2009-07-16 14:12:18 +00:00
Anton Korobeynikov 427dce8678 All calls clobbers R14 
llvm-svn: 75994
 2009-07-16 14:11:22 +00:00
Anton Korobeynikov 1eb6262b4b Consolidate reg-imm / reg-reg-imm address mode selection logic in one place. 
llvm-svn: 75990
 2009-07-16 14:10:17 +00:00
Anton Korobeynikov 62f8515b1c Add support for 12 bit displacements 
llvm-svn: 75988
 2009-07-16 14:09:35 +00:00
Anton Korobeynikov 7193e2670e Add jump tables 
llvm-svn: 75984
 2009-07-16 14:07:50 +00:00
Anton Korobeynikov 5dfac244a0 Exapnd br_jt into indirect branch. Provide pattern for indirect branches. 
llvm-svn: 75983
 2009-07-16 14:07:24 +00:00
Anton Korobeynikov d52a95f170 Implement 64 bit immediates 
llvm-svn: 75982
 2009-07-16 14:07:06 +00:00
Anton Korobeynikov 2ff298fad0 Add rotates 
llvm-svn: 75981
 2009-07-16 14:06:49 +00:00
Anton Korobeynikov 9362d9aa76 Add patterns for integer negate 
llvm-svn: 75980
 2009-07-16 14:06:27 +00:00
Anton Korobeynikov f07c7941f0 Provide proper patterns for and with imm instructions. Tune the tests accordingly. 
llvm-svn: 75979
 2009-07-16 14:06:00 +00:00
Anton Korobeynikov 59049d9176 Add 32 bit and reg-imm and disable invalid patterns for now 
llvm-svn: 75978
 2009-07-16 14:05:32 +00:00
Anton Korobeynikov 2d218394c6 Add z9 and z10 target processors. Mark z10-only instructions as such. 
llvm-svn: 75977
 2009-07-16 14:05:00 +00:00
Anton Korobeynikov 68b8486fde Fix MUL64rm instruction asmprinting 
llvm-svn: 75976
 2009-07-16 14:04:38 +00:00
Anton Korobeynikov edba6f3af7 Preliminary asmprinting of globals 
llvm-svn: 75975
 2009-07-16 14:04:22 +00:00
Anton Korobeynikov a2afc692f6 Implement asmprinting for odd-even regpairs 
llvm-svn: 75974
 2009-07-16 14:04:01 +00:00
Anton Korobeynikov ec66c122e0 32-bit ri addressing mode has only 12-bit displacement 
llvm-svn: 75973
 2009-07-16 14:03:41 +00:00
Anton Korobeynikov 59ef95bfc1 Print signed imms properly 
llvm-svn: 75970
 2009-07-16 14:02:45 +00:00
Anton Korobeynikov 73bf01f236 Pipehole pattern for i32 imm's 
llvm-svn: 75965
 2009-07-16 13:59:49 +00:00
Anton Korobeynikov ff1edc23ac Bunch of sext_inreg patterns 
llvm-svn: 75964
 2009-07-16 13:59:18 +00:00
Anton Korobeynikov c3170f5236 Provide normal 32 bit load and store 
llvm-svn: 75963
 2009-07-16 13:58:43 +00:00
Anton Korobeynikov d568f6dce2 Proper lower 'small' results 
llvm-svn: 75962
 2009-07-16 13:58:24 +00:00
Anton Korobeynikov f1bf3176c6 Completel forgot about unconditional branches 
llvm-svn: 75961
 2009-07-16 13:57:52 +00:00
Anton Korobeynikov 15d6e8785b Lower addresses of globals 
llvm-svn: 75960
 2009-07-16 13:57:27 +00:00
Anton Korobeynikov f0d7d6ce65 Provide "wide" muls and divs/rems 
llvm-svn: 75958
 2009-07-16 13:56:42 +00:00
Anton Korobeynikov 071178ea15 Preliminary mul lowering 
llvm-svn: 75951
 2009-07-16 13:53:55 +00:00
Anton Korobeynikov 23e3c6657c More extloads 
llvm-svn: 75950
 2009-07-16 13:53:35 +00:00
Anton Korobeynikov 0f59e1e874 SELECT_CC lowering 
llvm-svn: 75948
 2009-07-16 13:52:51 +00:00
Anton Korobeynikov ac4fb7f977 Conditional branches and comparisons 
llvm-svn: 75947
 2009-07-16 13:52:31 +00:00
Anton Korobeynikov 8695a30066 Emit callee-saved regs spills / restores 
llvm-svn: 75943
 2009-07-16 13:51:12 +00:00
Anton Korobeynikov d694b9ff8b Some preliminary call lowering 
llvm-svn: 75941
 2009-07-16 13:50:21 +00:00
Anton Korobeynikov 018599fc0b Prologue / epilogue emission 
llvm-svn: 75940
 2009-07-16 13:49:49 +00:00
Anton Korobeynikov 8a095bf56d Swap the order of imm and idx field for rri addrmode in order to make handling of rri and ri addrmodes common 
llvm-svn: 75937
 2009-07-16 13:48:42 +00:00
Anton Korobeynikov 19911b338a Do not truncate sign bits for negative imms 
llvm-svn: 75936
 2009-07-16 13:48:23 +00:00
Anton Korobeynikov 405833dfb6 Add address computation stuff 
llvm-svn: 75935
 2009-07-16 13:47:59 +00:00
Anton Korobeynikov b1e35b311c Cleanup 
llvm-svn: 75934
 2009-07-16 13:47:36 +00:00
Anton Korobeynikov df99232d27 Add mem-imm stores 
llvm-svn: 75933
 2009-07-16 13:47:14 +00:00
Anton Korobeynikov 44f8bbfb3f Add stores and truncstores 
llvm-svn: 75931
 2009-07-16 13:45:00 +00:00
Anton Korobeynikov 11b91b4e2e Add patterns for various extloads 
llvm-svn: 75930
 2009-07-16 13:44:30 +00:00
Anton Korobeynikov 0179364392 Do some heroic rri address matching (shamelessly stolen from x86 backend). Not tested though. 
llvm-svn: 75929
 2009-07-16 13:44:00 +00:00
Anton Korobeynikov 04be818918 Add shifts and reg-imm address matching 
llvm-svn: 75927
 2009-07-16 13:43:18 +00:00
Anton Korobeynikov cf7ea6a94f Add bunch of 32-bit patterns... Uffff :) 
llvm-svn: 75926
 2009-07-16 13:42:31 +00:00
Anton Korobeynikov de517f1e32 Add another bunch of reg-imm patterns for add/or/and/xor 
llvm-svn: 75922
 2009-07-16 13:35:08 +00:00
Anton Korobeynikov ebe2de0e14 Add bunch of reg-imm movs 
llvm-svn: 75921
 2009-07-16 13:34:50 +00:00
Anton Korobeynikov 168614f54f Proper match halfword-imm operands for mov and add 
llvm-svn: 75920
 2009-07-16 13:34:24 +00:00
Anton Korobeynikov 28234bcde2 Provide masked reg-imm 'or' and 'and' 
llvm-svn: 75919
 2009-07-16 13:33:57 +00:00
Anton Korobeynikov 0d76b17a78 Add reg-reg and pattern 
llvm-svn: 75917
 2009-07-16 13:32:49 +00:00
Anton Korobeynikov f9fe4036f2 Add sub reg-reg pattern 
llvm-svn: 75916
 2009-07-16 13:32:16 +00:00
Anton Korobeynikov a083d7af53 Add xor reg-reg pattern 
llvm-svn: 75915
 2009-07-16 13:31:28 +00:00
Anton Korobeynikov 65096d6a60 Add or reg-reg pattern. 
llvm-svn: 75914
 2009-07-16 13:30:53 +00:00
Anton Korobeynikov 18172d786f Add add reg-reg and reg-imm patterns 
llvm-svn: 75913
 2009-07-16 13:30:15 +00:00
Anton Korobeynikov 09082fa01a Add simple reg-reg and reg-imm moves 
llvm-svn: 75912
 2009-07-16 13:29:38 +00:00
Anton Korobeynikov cf4ba97dba Minimal lowering for formal_arguments / ret 
llvm-svn: 75911
 2009-07-16 13:28:59 +00:00
Anton Korobeynikov c334c28b3b Let's start another backend :) 
llvm-svn: 75909
 2009-07-16 13:27:25 +00:00