1b2156fcae
Add support on x86 for having Legalize lower ISD::LOCATION to ISD::DEBUG_LOC
...
instead of ISD::LABEL with a manual .debug_line entry when the assembler
supports .file and .loc directives.
llvm-svn: 42278
2007-09-24 21:54:14 +00:00
5b5484db63
claim that "st" is from the 80-bit register file. This causes x87-using inline
...
asm to die with:
ScheduleDAG.cpp:269: failed assertion `false && "Couldn't find the register class"'
instead of:
failed assertion `RegMap->getRegClass(VReg) == RC && "Register class of operand and regclass of use don't agree!"'
yay.
llvm-svn: 42259
2007-09-24 05:27:37 +00:00
e36c400255
Fix PR 1681. When X86 target uses +sse -sse2,
...
keep f32 in SSE registers and f64 in x87. This
is effectively a new codegen mode.
Change addLegalFPImmediate to permit float and
double variants to do different things.
Adjust callers.
llvm-svn: 42246
2007-09-23 14:52:20 +00:00
4730c04904
Don't add a default STACK_ALIGN (use the generic ABI alignment)
...
Implement calls to functions with byval arguments on X86
llvm-svn: 42192
2007-09-21 15:50:22 +00:00
f065f0e2a1
small cleanup: use LowerMemArgument in LowerFastCCArguments also
...
llvm-svn: 42189
2007-09-21 14:55:38 +00:00
7d67e547b5
More long double fixes. x86_64 should build now.
...
llvm-svn: 42155
2007-09-19 23:55:34 +00:00
863bdc332d
Emit integer x<1 as x<=0, as comparisons with zero (now includeing
...
64-bit) can use test instead of cmp with an immediate.
llvm-svn: 42026
2007-09-17 14:49:27 +00:00
98d3a08d8f
Remove the assumption that FP's are either float or
...
double from some of the many places in the optimizers
it appears, and do something reasonable with x86
long double.
Make APInt::dump() public, remove newline, use it to
dump ConstantSDNode's.
Allow APFloats in FoldingSet.
Expand X86 backend handling of long doubles (conversions
to/from int, mostly).
llvm-svn: 41967
2007-09-14 22:26:36 +00:00
272f7304f0
Add support for functions with byval arguments on x86
...
llvm-svn: 41953
2007-09-14 15:48:13 +00:00
245dceb06d
Add APInt interfaces to APFloat (allows directly
...
access to bits). Use them in place of float and
double interfaces where appropriate.
First bits of x86 long double constants handling
(untested, probably does not work).
llvm-svn: 41858
2007-09-11 18:32:33 +00:00
86e0119822
Fold the adjust_trampoline intrinsic into
...
init_trampoline. There is now only one
trampoline intrinsic.
llvm-svn: 41841
2007-09-11 14:10:23 +00:00
bed9dc423c
Next round of APFloat changes.
...
Use APFloat in UpgradeParser and AsmParser.
Change all references to ConstantFP to use the
APFloat interface rather than double. Remove
the ConstantFP double interfaces.
Use APFloat functions for constant folding arithmetic
and comparisons.
(There are still way too many places APFloat is
just a wrapper around host float/double, but we're
getting there.)
llvm-svn: 41747
2007-09-06 18:13:44 +00:00
50ab26e835
Reapply r41578 with proper fix
...
llvm-svn: 41680
2007-09-03 00:36:06 +00:00
e636fc05d6
Initial support for calling functions with byval arguments on x86-64
...
llvm-svn: 41643
2007-08-31 15:06:30 +00:00
3cf889f75e
Enhance APFloat to retain bits of NaNs (fixes oggenc).
...
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.
llvm-svn: 41632
2007-08-31 04:03:46 +00:00
d246b2ca5c
Change LegalFPImmediates to use APFloat.
...
Add APFloat interfaces to ConstantFP, SelectionDAG.
Fix integer bit in double->APFloat conversion.
Convert LegalizeDAG to use APFloat interface in
ConstantFPSDNode uses.
llvm-svn: 41587
2007-08-30 00:23:21 +00:00
7741427a09
Move getX86RegNum into X86RegisterInfo and use it
...
in the trampoline lowering. Lookup the jump and
mov opcodes for the trampoline rather than hard
coding them.
llvm-svn: 41577
2007-08-29 19:01:20 +00:00
b602461f48
Add a comment about using libc memset/memcpy or generating inline code.
...
llvm-svn: 41502
2007-08-27 17:48:26 +00:00
ff33241e16
call libc memcpy/memset if array size is bigger then threshold.
...
Coping 100MB array (after a warmup) shows that glibc 2.6.1 implementation on
x86-64 (core 2) is 30% faster (from 0.270917s to 0.188079s)
llvm-svn: 41479
2007-08-27 10:18:20 +00:00
d8c9cb9182
rename isOperandValidForConstraint to LowerAsmOperandForConstraint,
...
changing the interface to allow for future changes.
llvm-svn: 41384
2007-08-25 00:47:38 +00:00
9c3d20d823
Partial implementation of calling functions with byval arguments:
...
*) The needed information is propagated to the DAG
*) The X86-64 backend detects it and aborts
llvm-svn: 41179
2007-08-20 15:18:24 +00:00
597c8b77e4
Move ReturnAddrIndex variable to X86MachineFunctionInfo structure. This fixed
...
hard to catch bugs with retaddr lowering
llvm-svn: 41104
2007-08-15 17:12:32 +00:00
b2823dac69
Fix a typo pointd out by Maarten ter Huurne.
...
llvm-svn: 41059
2007-08-13 23:27:11 +00:00
b372abab14
Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)).
...
llvm-svn: 41010
2007-08-10 21:48:46 +00:00
66011c17d5
propagate struct size and alignment of byval arguments to the DAG
...
llvm-svn: 40986
2007-08-10 14:44:42 +00:00
ba1a98a4e0
long double 9 of N. This finishes up the X86-32 bits
...
(constants are still not handled). Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).
llvm-svn: 40958
2007-08-09 01:04:01 +00:00
57c6ac5fe5
Long double patch 7 of N, unless I lost count:).
...
Last x87 bits for full functionality (not
thoroughly tested, and long doubles do not work
in SSE modes at all - use -mcpu=i486 for now)
llvm-svn: 40886
2007-08-07 01:17:37 +00:00
b1888e73ad
Long double patch 4 of N: initial x87 implementation.
...
Lots of problems yet but some simple things work.
llvm-svn: 40847
2007-08-05 18:49:15 +00:00
8932bff7fe
Fix the alignment requirements of several unpck and shuf instructions.
...
Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's
memory operand alignment can be tested as well, with a fix to avoid
breaking MMX's use of isPSHUFDMask.
llvm-svn: 40756
2007-08-02 21:17:01 +00:00
d3d92890fc
Can't handle offset and scale if rip-relative addressing is to be used.
...
llvm-svn: 40703
2007-08-01 23:46:47 +00:00
242a87734a
This isn't safe when there are uses of load's chain result.
...
llvm-svn: 40617
2007-07-31 06:21:44 +00:00
ce38853cc6
Trampoline codegen support for X86-32.
...
llvm-svn: 40566
2007-07-27 20:02:49 +00:00
4788552deb
Re-apply 40504, but with a fix for the segfault it caused in oggenc:
...
Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.
llvm-svn: 40555
2007-07-27 17:16:43 +00:00
931de40afa
Reverting 40504 for now. It's breaking oggenc.
...
llvm-svn: 40547
2007-07-27 01:37:47 +00:00
8455bd3fae
Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from the
...
x86 target, replacing them with the new alignment attributes on memory
references.
llvm-svn: 40504
2007-07-26 00:31:09 +00:00
f906c7286f
Use movaps to load a v4f32 build_vector of all-constant values into a
...
register instead of loading each element individually.
llvm-svn: 40478
2007-07-24 22:55:08 +00:00
b6a8ae20c7
Fix some uses of dyn_cast to be uses of cast.
...
llvm-svn: 40443
2007-07-23 20:24:29 +00:00
64738536b3
Fix custom lowering of SSE FXOR.
...
llvm-svn: 40071
2007-07-19 23:36:01 +00:00
383a324735
Long live the exception handling!
...
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
llvm-svn: 39855
2007-07-14 14:06:15 +00:00
57111e7a60
Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp,
...
in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.
llvm-svn: 38478
2007-07-10 00:05:58 +00:00
de9c825859
Proper flag __alloca call
...
llvm-svn: 37923
2007-07-05 20:36:08 +00:00
3d7008cd49
Refactor X87 instructions. As a side effect, all
...
their names are changed.
llvm-svn: 37876
2007-07-04 21:07:47 +00:00
a2b3c175db
Fix for PR 1505 (and 1489). Rewrite X87 register
...
model to include f32 variants. Some factoring
improvments forthcoming.
llvm-svn: 37847
2007-07-03 00:53:03 +00:00
444d3ca53d
No vector fneg.
...
llvm-svn: 37786
2007-06-29 00:18:15 +00:00
3bd318e298
Type of vector extract / insert index operand should be iPTR.
...
llvm-svn: 37784
2007-06-29 00:01:20 +00:00
a866514528
Generalize MVT::ValueType and associated functions to be able to represent
...
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
llvm-svn: 37719
2007-06-25 16:23:39 +00:00
309d3d51b3
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
...
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
944200be45
If a function is vararg, never pass inreg arguments in registers. Thanks to
...
Anton for half of this patch.
llvm-svn: 37641
2007-06-19 00:13:10 +00:00
cea02ffd05
Look for VECTOR_SHUFFLE that's identity operation on either LHS or RHS. This can happen before DAGCombiner catches it.
...
llvm-svn: 37636
2007-06-19 00:02:56 +00:00
094a4e813a
Revert patch. It regresses:
...
define double @test2(i64 %A) {
%B = bitcast i64 %A to double
ret double %B
}
$ llvm-as < t.ll | llc -march=x86-64
before:
.align 4
.globl _test2
_test2:
movd %rdi, %xmm0
ret
after:
_test2:
subq $8, %rsp
movq %rdi, (%rsp)
movsd (%rsp), %xmm0
addq $8, %rsp
ret
llvm-svn: 37617
2007-06-16 23:57:15 +00:00
cd9673e565
Fix a failure to bit_convert from integer GPR to MMX register.
...
llvm-svn: 37611
2007-06-16 06:17:31 +00:00
5c4413120f
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
...
llvm-svn: 37579
2007-06-14 22:58:02 +00:00
75372ad603
fix x86-64 mmx calling convention for real, which passes in integer gprs.
...
llvm-svn: 37534
2007-06-09 05:08:10 +00:00
a4a49e37ab
fix mmx handling bug
...
llvm-svn: 37533
2007-06-09 05:01:50 +00:00
703e0f8608
Add explicit qualification for namespace MVT members.
...
llvm-svn: 37320
2007-05-24 14:33:05 +00:00
eefa83e67b
Use MVT::FIRST_VECTOR_VALUETYPE and MVT::LAST_VECTOR_VALUETYPE.
...
llvm-svn: 37234
2007-05-18 18:44:07 +00:00
afa1cb6da3
Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector.
...
llvm-svn: 37173
2007-05-17 18:45:50 +00:00
dade607f19
This is the correct fix for PR1427. This fixes mmx-shuffle.ll and doesn't
...
cause other regressions.
llvm-svn: 37160
2007-05-17 17:13:13 +00:00
1ad4618715
Revert patch for PR1427. It breaks almost all vector tests.
...
llvm-svn: 37159
2007-05-17 07:50:14 +00:00
6a5a46322f
Fix PR1427 and test/CodeGen/X86/mmx-shuffle.ll
...
llvm-svn: 37141
2007-05-17 03:29:42 +00:00
c8798d085c
fix subtle bugs in inline asm operand selection
...
llvm-svn: 37065
2007-05-15 01:28:08 +00:00
83df45a959
Fix two classes of bugs:
...
1. x86 backend rejected (&gv+c) for the 'i' constraint when in static mode.
2. the matcher didn't correctly reject and accept some global addresses.
the right predicate is GVRequiresExtraLoad, not "relomodel = pic".
llvm-svn: 36670
2007-05-03 16:52:29 +00:00
f1dcf69fc3
Emit correct register move information in eh frames for X86. This allows Shootout-C++/except to pass on x86/linux
...
with non-llvm-compiled (e.g. "native") unwind runtime.
llvm-svn: 36647
2007-05-02 19:53:33 +00:00
591eab8844
Support for the special case of a vector with the canonical form:
...
vector_shuffle v1, v2, <2, 6, 3, 7>
I.e.
vector_shuffle v, undef, <2, 2, 3, 3>
MMX only has a shuffle for v4i16 vectors. It needs to use the unpackh for
this type of operation.
llvm-svn: 36403
2007-04-24 21:16:55 +00:00
efb8077ddd
X86 TLS: fix and optimize the implementation of "initial exec" model.
...
llvm-svn: 36355
2007-04-22 22:50:52 +00:00
4e91908f17
X86 TLS: Implement review feedback.
...
llvm-svn: 36318
2007-04-21 20:56:26 +00:00
2518889872
Implement "general dynamic", "initial exec" and "local exec" TLS models for
...
X86 32 bits.
llvm-svn: 36283
2007-04-20 21:38:10 +00:00
9b91d98a30
Add comment
...
llvm-svn: 36213
2007-04-17 19:34:00 +00:00
ff0598de75
rename X86FunctionInfo to X86MachineFunctionInfo to match the header file
...
it is defined in.
llvm-svn: 36196
2007-04-17 17:21:52 +00:00
8b7aab009e
Implemented correct stack probing on mingw/cygwin for dynamic alloca's.
...
Also, fixed static case in presence of eax livin. This fixes PR331
PS: Why don't we still have push/pop instructions? :)
llvm-svn: 36195
2007-04-17 09:20:00 +00:00
fb80151c42
Removed tabs everywhere except autogenerated & external files. Add make
...
target for tabs checking.
llvm-svn: 36146
2007-04-16 18:10:23 +00:00
2805bce656
Fix mmx paddq, add support for the 'y' register class, though it isn't tested.
...
llvm-svn: 35940
2007-04-12 04:14:49 +00:00
808ac93f68
remove some dead hooks
...
llvm-svn: 35845
2007-04-09 23:31:19 +00:00
39f65335d5
remove some dead target hooks, subsumed by isLegalAddressingMode
...
llvm-svn: 35840
2007-04-09 22:27:04 +00:00
7451e4d6a1
move a bunch of register constraints from being handled by
...
getRegClassForInlineAsmConstraint to being handled by
getRegForInlineAsmConstraint. This allows us to let the llvm register allocator
allocate, which gives us better code. For example, X86/2007-01-29-InlineAsm-ir.ll
used to compile to:
_run_init_process:
subl $4, %esp
movl %ebx, (%esp)
xorl %ebx, %ebx
movl $11, %eax
movl %ebx, %ecx
movl %ebx, %edx
# InlineAsm Start
push %ebx ; movl %ebx,%ebx ; int $0x80 ; pop %ebx
# InlineAsm End
Now we get:
_run_init_process:
xorl %ecx, %ecx
movl $11, %eax
movl %ecx, %edx
# InlineAsm Start
push %ebx ; movl %ecx,%ebx ; int $0x80 ; pop %ebx
# InlineAsm End
llvm-svn: 35804
2007-04-09 05:49:22 +00:00
2b6b4eb471
implement support for CodeGen/X86/inline-asm-x-scalar.ll:test3 - i32/i64 values
...
used with x constraints.
llvm-svn: 35803
2007-04-09 05:31:48 +00:00
590ed5e5b7
implement CodeGen/X86/inline-asm-x-scalar.ll
...
llvm-svn: 35799
2007-04-09 05:11:28 +00:00
1eb94d973a
implement the new addressing mode description hook.
...
llvm-svn: 35521
2007-03-30 23:15:24 +00:00
2338e21b2b
Remove cruft I put in there...
...
llvm-svn: 35394
2007-03-28 01:02:54 +00:00
ad2db4a4cf
Unbreak mmx arithmetic. It was barfing trying to do v8i8 arithmetic.
...
llvm-svn: 35392
2007-03-28 00:57:11 +00:00
6dff51ae65
Fix so that pandn is emitted instead of an xor/and combo. Add integer
...
comparison operators.
llvm-svn: 35385
2007-03-27 20:22:40 +00:00
158f6092a2
Promote to v1i64 type...
...
llvm-svn: 35353
2007-03-26 08:03:33 +00:00
98d2104c6f
Add support for the v1i64 type. This makes better code for this:
...
#include <mmintrin.h>
extern __m64 C;
void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}
We get this:
_baz:
call "L1$pb"
"L1$pb":
popl %eax
movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret
GCC gives us this:
_baz:
pushl %ebx
call L3
"L00000000001$pb":
L3:
popl %ebx
subl $8, %esp
movl L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
movl (%eax), %edx
movl 4(%eax), %ecx
movl 16(%esp), %eax
movl %edx, (%eax)
movl %ecx, 4(%eax)
emms
addl $8, %esp
popl %ebx
ret
llvm-svn: 35351
2007-03-26 07:53:08 +00:00
d685514e2e
switch TargetLowering::getConstraintType to take the entire constraint,
...
not just the first letter. No functionality change.
llvm-svn: 35322
2007-03-25 02:14:49 +00:00
03a643aa69
enforce the proper range for the i386 N constraint.
...
llvm-svn: 35319
2007-03-25 01:57:35 +00:00
d551a18783
Support added for shifts and unpacking MMX instructions.
...
llvm-svn: 35266
2007-03-22 18:42:45 +00:00
0c6bb5eab7
repair x86 performance, dejagnu problems from previous change
...
llvm-svn: 35245
2007-03-21 21:51:52 +00:00
f01f87bc63
fix a warning
...
llvm-svn: 35152
2007-03-19 00:39:32 +00:00
b38c2ec89c
Support 'I' inline asm constraint.
...
llvm-svn: 35129
2007-03-17 00:13:28 +00:00
144b8bbf17
And now support for MMX logical operations.
...
llvm-svn: 35125
2007-03-16 09:44:46 +00:00
e31034125c
Multiplication support for MMX.
...
llvm-svn: 35118
2007-03-15 21:24:36 +00:00
a1779b9739
Under X86-64 large code model, do not emit 32-bit pc relative calls.
...
llvm-svn: 35108
2007-03-14 22:11:11 +00:00
3ab7ea7965
More flexible TargetLowering LSR hooks for testing whether an immediate is
...
a legal target address immediate or scale.
llvm-svn: 35073
2007-03-12 23:28:50 +00:00
57f261b13a
Stupid bug: SSE2 supports v2i64 add / sub.
...
llvm-svn: 35070
2007-03-12 22:58:52 +00:00
e9b81f5366
Adding more arithmetic operators to MMX. This is an almost exact copy of
...
the addition. Please let me know if you have suggestions.
llvm-svn: 35055
2007-03-10 09:57:05 +00:00
6092ce25cf
Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that
...
moves, loads, etc. are recognized.
llvm-svn: 35031
2007-03-08 22:09:11 +00:00
ed4b303c10
Refactoring of formal parameter flags. Enable properly use of
...
zext/sext/aext stuff.
llvm-svn: 35008
2007-03-07 16:25:09 +00:00
97905b4027
Properly support v8i8 and v4i16 types. It now converts them to v2i32 for
...
load and stores.
llvm-svn: 35002
2007-03-07 05:43:18 +00:00
bbd25984b7
Add LOAD/STORE support for MMX.
...
llvm-svn: 34978
2007-03-06 18:53:42 +00:00
e7ec3bc7bc
Use new SDIselParamAttr enumeration. This removes "magick" constants
...
from formal attributes' flags processing.
llvm-svn: 34963
2007-03-06 08:12:33 +00:00
deaea25eb9
X86-64 VACOPY needs custom expansion. va_list is a struct { i32, i32, i8*, i8* }.
...
llvm-svn: 34857
2007-03-02 23:16:35 +00:00
57af2a4f3b
Simplify things
...
llvm-svn: 34849
2007-03-02 21:50:27 +00:00
9c7e5e365d
argument lowering should copy from the vreg shadows of live-in arguments
...
passed in registers, not directly from the pregs themselves.
llvm-svn: 34838
2007-03-02 05:12:29 +00:00
af8be4458f
Ensure that fastcall'ed function is correctly mangled & stack is
...
properly aligned
llvm-svn: 34788
2007-03-01 16:29:22 +00:00
7373f3a351
remove dead option
...
llvm-svn: 34754
2007-02-28 18:39:53 +00:00
152bfa103e
use high-level functions in CCState
...
llvm-svn: 34739
2007-02-28 07:09:55 +00:00
227b6c5d19
make use of helper functions in CCState for analyzing formals and calls.
...
llvm-svn: 34737
2007-02-28 07:00:42 +00:00
d439e86078
switch LowerFastCCCallTo over to using the new fastcall description.
...
llvm-svn: 34734
2007-02-28 06:26:33 +00:00
66e1d1dd7e
switch LowerFastCCArguments over to using the autogenerated Fastcall description.
...
llvm-svn: 34733
2007-02-28 06:21:19 +00:00
3066beccb5
rearrange code
...
llvm-svn: 34731
2007-02-28 06:10:12 +00:00
3ed3be3b4a
remove fastcc (not fastcall) support
...
llvm-svn: 34730
2007-02-28 06:05:16 +00:00
b9db225049
switch LowerCCCArguments over to using autogenerated CC.
...
llvm-svn: 34729
2007-02-28 05:46:49 +00:00
5958b176f3
simplify sret handling
...
llvm-svn: 34728
2007-02-28 05:39:26 +00:00
be7995953a
switch LowerCCCCallTo over to using an autogenerated callingconv
...
llvm-svn: 34727
2007-02-28 05:31:48 +00:00
ba3d273122
switch return value passing and the x86-64 calling convention information
...
over to being autogenerated from the X86CallingConv.td file.
llvm-svn: 34722
2007-02-28 04:55:35 +00:00
c9eed39a5d
switch x86-64 return value lowering over to using same mechanism as argument
...
lowering uses.
llvm-svn: 34657
2007-02-27 05:28:59 +00:00
9f059194a7
Minor refactoring of CC Lowering interfaces
...
llvm-svn: 34656
2007-02-27 05:13:54 +00:00
dc3adc83e7
move CC Lowering stuff to its own public interface
...
llvm-svn: 34655
2007-02-27 04:43:02 +00:00
2e5e8407ad
refactor x86-64 argument lowering yet again, this time eliminating templates,
...
'clients', etc, and adding CCValAssign instead.
llvm-svn: 34654
2007-02-27 04:18:15 +00:00
ff19957468
switch to smallvector
...
llvm-svn: 34633
2007-02-26 07:59:53 +00:00
294780829a
initial hack at splitting the x86-64 calling convention info out from the
...
mechanics that process it. I'm still not happy with this, but it's a step
in the right direction.
llvm-svn: 34631
2007-02-26 07:50:02 +00:00
d41bff0f97
the truncate must always be done, it's only the assert that is conditional.
...
llvm-svn: 34628
2007-02-26 05:21:05 +00:00
1db979bae8
in X86-64 CCC, i8/i16 arguments are already properly zext/sext'd on input.
...
Capture this so that downstream zext/sext's are optimized out. This
compiles:
int test(short X) { return (int)X; }
to:
_test:
movl %edi, %eax
ret
instead of:
_test:
movswl %di, %eax
ret
GCC produces this bizarre code:
_test:
movw %di, -12(%rsp)
movswl -12(%rsp),%eax
ret
llvm-svn: 34623
2007-02-26 03:18:56 +00:00
8924332e22
Fix an X86-64 abi bug. We now compile:
...
void foo(short);
void bar(unsigned short A) {
foo(A);
}
into:
_bar:
subq $8, %rsp
movswl %di, %edi
call _foo
addq $8, %rsp
ret
instead of:
_bar:
subq $8, %rsp
call _foo
addq $8, %rsp
ret
Testcase here: test/CodeGen/X86/x86-64-shortint.ll
llvm-svn: 34615
2007-02-25 23:10:46 +00:00
3e0703357f
fix CodeGen/X86/2007-02-25-FastCCStack.ll, a regression from my patch last
...
night: fastcc returns should only go in XMM0 if we have SSE2 or above.
llvm-svn: 34613
2007-02-25 22:23:46 +00:00
fcee9b5568
fastcc functions that return double values now return them in xmm0 on x86-32.
...
This implements CodeGen/X86/fp-stack-ret.ll:test[23]
llvm-svn: 34592
2007-02-25 09:31:16 +00:00
9d9cc84f5b
allow vectors to be passed to stdcall/fastcall functions
...
llvm-svn: 34590
2007-02-25 09:14:25 +00:00
2fc0d70392
move LowerRET into the 'Return Value Calling Convention Implementation'
...
section of the file.
llvm-svn: 34589
2007-02-25 09:12:39 +00:00
ba474f58a4
make all Lower*CallTo implementations use LowerCallResult to handle their
...
result value stuff. This eliminates a bunch of duplicated code and now
GetRetValueLocs is the sole place that decides where a value is returned.
llvm-svn: 34588
2007-02-25 09:10:05 +00:00
7802f3e2ea
pass the calling convention into Lower*CallTo, instead of using ad-hoc flags.
...
llvm-svn: 34587
2007-02-25 09:06:15 +00:00
0cd9960fe7
factor a bunch of code out of LowerCCCCallTo into a new LowerCallResult
...
function. This function now uses GetRetValueLocs to determine *where*
the result values are located and concerns itself with *how* to pull the
values out.
llvm-svn: 34586
2007-02-25 08:59:22 +00:00
3c76309a5b
move some code around, pass in calling conv, even though it is unused
...
llvm-svn: 34585
2007-02-25 08:29:00 +00:00
dfda38f7dc
simplify result value lowering by splitting the selection of *where* to return
...
registers out from the logic of *how* to return them.
This changes X86-64 to mark EAX live out when returning a 32-bit value,
where before it marked RAX liveout.
llvm-svn: 34582
2007-02-25 08:15:11 +00:00
d6b853ad1b
make void-return not a special case
...
llvm-svn: 34579
2007-02-25 07:18:38 +00:00
35a08551a5
eliminate a bunch more temporary vectors from X86 lowering.
...
llvm-svn: 34578
2007-02-25 07:10:00 +00:00
e56fef9b51
eliminate temporary vectors created during X86 lowering.
...
llvm-svn: 34577
2007-02-25 06:40:16 +00:00
84141d4e99
remove std::vector's in RET lowering.
...
llvm-svn: 34576
2007-02-25 06:21:57 +00:00
e0008e23cf
Simplify lowering and selection of exception ops.
...
llvm-svn: 34488
2007-02-22 14:56:36 +00:00
3796abea0f
Support to provide exception and selector registers.
...
llvm-svn: 34482
2007-02-21 22:54:50 +00:00
84a041eb98
ELF / PIC requires GOT be in the EBX register during calls via PLT GOT pointer.
...
Add implicit uses of EBX to calls to ensure liveintervalanalysis does not treat
the GOT in EBX move as dead upon definition.
This should fix PR1207.
llvm-svn: 34470
2007-02-21 21:18:14 +00:00
1b4e6015b4
Fixed uninitialized stuff inside LegalizeDAG. Fortunately, the only
...
affected part is codegen of "memove" inside x86 backend. This fixes
PR1144
llvm-svn: 33752
2007-02-01 08:39:52 +00:00
eda5997cc8
Finish off bug 680, allowing targets to custom lower frame and return
...
address nodes.
llvm-svn: 33636
2007-01-29 22:58:52 +00:00
0c49722b36
Fix compile error "jump to case label crosses initialization".
...
What compiler are people using that accepts this code?
llvm-svn: 33603
2007-01-28 15:39:16 +00:00
037c867b54
Propagate changes from my local tree. This patch includes:
...
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret => sret.
Before this, there will be some unexpected test fails.
llvm-svn: 33597
2007-01-28 13:31:35 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
...
llvm-svn: 33537
2007-01-26 14:34:52 +00:00
1281dc32ef
Linux GOT indirect reference is only necessary in PIC mode.
...
llvm-svn: 33441
2007-01-22 21:34:25 +00:00
a0554d90e8
* PIC codegen for X86/Linux has been implemented
...
* PIC-aware internal structures in X86 Codegen have been refactored
* Visibility (default/weak) has been added
* Docs fixes (external weak linkage, visibility, formatting)
llvm-svn: 33136
2007-01-12 19:20:47 +00:00
82241c86e9
- FCOPYSIGN custom lowering bug. Clear the sign bit of operand 0 first before
...
or'ing in the sign bit of operand 1.
- Tweaking: rather than left shift the sign bit, fp_extend operand 1 first
before taking its sign bit if its type is smaller than that of operand 0.
llvm-svn: 32932
2007-01-05 21:37:56 +00:00
8c7094a770
Typo
...
llvm-svn: 32902
2007-01-05 08:32:24 +00:00
4363e884c0
With SSE2, expand FCOPYSIGN to a series of SSE bitwise operations.
...
llvm-svn: 32900
2007-01-05 07:55:56 +00:00
e87b5e9825
Fix a comment that referred to the now defunct ubyte type.
...
llvm-svn: 32840
2007-01-03 17:24:59 +00:00
4efbbc963f
Really big cleanup.
...
- New target type "mingw" was introduced
- Same things for both mingw & cygwin are marked as "cygming" (as in
gcc)
- .lcomm is supported here, so allow LLVM to use it
- Correctly use underscored versions of setjmp & _longjmp for both mingw
& cygwin
llvm-svn: 32833
2007-01-03 11:43:14 +00:00
e63b6518fa
For PR950:
...
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
type of an function parameter was used to determine whether it should
be sign extended or zero extended before the call. This information is
now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
the parameter attribute information. Although it would have been
convenient to pass in the FunctionType itself, there isn't always one
present in the caller. Consequently, a signedness indication for the
result type and for each parameter was provided for in the interface
to this method. All implementations were changed to make the adjustment
necessary.
llvm-svn: 32788
2006-12-31 05:55:36 +00:00
430e68a1b9
Refactored JIT codegen for mingw32. Now we're using standart relocation
...
type for distinguish JIT & non-JIT instead of "dirty" hacks :)
llvm-svn: 32745
2006-12-22 22:29:05 +00:00
735fcf74d8
f64 <-> i64 bit_convert using movq in 64-bit mode.
...
llvm-svn: 32587
2006-12-14 21:55:39 +00:00
3b7c257cae
Cleaned setjmp/longjmp lowering interfaces. Now we're producing right
...
code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.
llvm-svn: 32415
2006-12-10 23:12:42 +00:00
c20b7e878a
If we have ScalarSSE, we can select bitconvert into single instructions.
...
This compiles bitcast.ll:test3/test4 into:
_test3:
movd %xmm0, %eax
ret
_test4:
movd %edi, %xmm0
ret
llvm-svn: 32230
2006-12-05 18:45:06 +00:00
55c17f9177
Fix PR1033 and CodeGen/X86/bitcast.ll, by expanding bitcast to a load/store pair.
...
This could be better, readme entry pending.
llvm-svn: 32228
2006-12-05 18:22:22 +00:00
a16201c672
Fix typo noticed by Lauro Ramos Venancio, thanks!
...
llvm-svn: 32223
2006-12-05 17:29:40 +00:00
62cdc3f011
- Fix X86-64 JIT by temporarily disabling code that treats GV address as 32-bit
...
immediate in small code model. The JIT cannot ensure GV's are placed in the
lower 4G.
- Some preliminary support for large code model.
llvm-svn: 32215
2006-12-05 04:01:03 +00:00
d139ddd2e6
Add support for 64-bit 'r' constraint. Patch by by Rafael ~Avila de EspÃndol!
...
This fixes PR1029 and Regression/CodeGen/X86/x86-64-asm.ll
llvm-svn: 32206
2006-12-04 22:38:21 +00:00
ae1cd75af7
- Use a different wrapper node for RIP-relative GV, etc.
...
- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.
llvm-svn: 32046
2006-11-30 21:55:46 +00:00
7a9238c84d
In PIC mode, GV not requiring an extra load can be used as address immediate.
...
llvm-svn: 32028
2006-11-29 23:48:14 +00:00
0b1692216d
Fix for PR1018 - Better support for X86-64 Linux in small code model.
...
llvm-svn: 32026
2006-11-29 23:19:46 +00:00
28a9e9b230
Custom lower READCYCLECOUNTER for x86-64.
...
llvm-svn: 32017
2006-11-29 08:28:13 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
...
of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
5b96cdebb0
Refactored *GVRequiresExtraLoad() to Subtarget method.
...
llvm-svn: 31887
2006-11-21 00:01:06 +00:00
37d080b11d
We should perform extra load for dllimported calls
...
llvm-svn: 31874
2006-11-20 10:46:14 +00:00
dbd3d294e6
Matches MachineInstr changes.
...
llvm-svn: 31712
2006-11-13 23:36:35 +00:00
db04c958a5
Add implicit use / def operands to created MI's.
...
llvm-svn: 31676
2006-11-11 10:21:44 +00:00
49683ba236
Don't dag combine floating point select to max and min intrinsics. Those
...
take v4f32 / v2f64 operands and may end up causing larger spills / restores.
Added X86 specific nodes X86ISD::FMAX, X86ISD::FMIN instead.
This fixes PR996.
llvm-svn: 31645
2006-11-10 21:43:37 +00:00
b9c91c265c
Fixing PR990: http://llvm.org/PR990 .
...
This should unbreak csretcc on Linux & mingw targets. Several tests from
llvm-test should be also restored (fftbench, bigfib).
llvm-svn: 31613
2006-11-10 00:48:11 +00:00
922e191116
Fixed a bug which causes x86 be to incorrectly match
...
shuffle v, undef, <2, ?, 3, ?>
to movhlps
It should match to unpckhps instead.
Added proper matching code for
shuffle v, undef, <2, 3, 2, 3>
llvm-svn: 31519
2006-11-07 22:14:24 +00:00
de46e48420
For PR786:
...
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
llvm-svn: 31380
2006-11-02 20:25:50 +00:00
44daa50bed
allow the address of a global to be used with the "i" constraint when in
...
-static mode. This implements PR882.
llvm-svn: 31326
2006-10-31 20:13:11 +00:00
f6a6966cd2
handle "st" as "st(0)"
...
llvm-svn: 31320
2006-10-31 19:42:44 +00:00
aa4c0f9374
1. Clean up code due to changes in SwitchTo*Section(2)
...
2. Added partial debug support for mingw\cygwin targets (the same as
Linux\ELF). Please note, that currently mingw\cygwin uses 'stabs' format
for storing debug info by default, thus many (runtime) libraries has
this information included. These formats shouldn't be mixed in one binary
('stabs' & 'DWARF'), otherwise binutils tools will be confused.
llvm-svn: 31311
2006-10-31 08:31:24 +00:00
b51b5c0b1f
Add debug support for X86/ELF targets (Linux). This allows llvm-gcc4
...
generated object modules to be debugged with gdb. Hopefully this helps
pre-release debugging.
llvm-svn: 31299
2006-10-30 22:32:30 +00:00
0d41d19427
All targets expand BR_JT for now.
...
llvm-svn: 31294
2006-10-30 08:02:39 +00:00
e056dd5928
Fixed a significant bug where unpcklpd is incorrectly used to extract element 1 from a v2f64 value.
...
llvm-svn: 31228
2006-10-27 21:08:32 +00:00
bf3df77758
Fix for PR968: expand vector sdiv, udiv, srem, urem.
...
llvm-svn: 31220
2006-10-27 18:49:08 +00:00
c415c5be49
During vector shuffle lowering, we sometimes commute a vector shuffle to try
...
to match MOVL (movss, movsd, etc.). Don't forget to commute it back and try
unpck* and shufp* if that doesn't pan out.
llvm-svn: 31186
2006-10-25 21:49:50 +00:00
798b306311
Remove -disable-x86-shuffle-opti
...
llvm-svn: 31183
2006-10-25 20:48:19 +00:00
c0fb567e23
Implement branch analysis/xform hooks required by the branch folding pass.
...
llvm-svn: 31065
2006-10-20 17:42:20 +00:00
949bcc94ea
Avoid getting into an infinite loop when -disable-x86-shuffle-opti is specified.
...
llvm-svn: 30974
2006-10-16 06:36:00 +00:00
ab51cf2e78
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
694810c227
Some X86ISD::CMP were created with wrong ValueType's.
...
llvm-svn: 30913
2006-10-12 19:12:56 +00:00
e646abb7b6
Don't convert to MOVLP if using shufps etc. may allow load folding.
...
llvm-svn: 30847
2006-10-09 21:39:25 +00:00
e71fe34d75
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
df9ac47e5e
Make use of getStore().
...
llvm-svn: 30759
2006-10-05 23:01:46 +00:00
f2ef243580
Lower some min/max idioms to minss/maxss when unsafe fp math is enabled.
...
llvm-svn: 30748
2006-10-05 04:11:26 +00:00
8c5766ef3f
Added option -disable-x86-shuffle-opti to disable X86 specific vector shuffle optimizations.
...
llvm-svn: 30723
2006-10-04 18:33:38 +00:00
9259b1efb6
Pattern match min/max nodes when we have sse. This implements
...
CodeGen/X86/scalar_sse_minmax.ll
llvm-svn: 30719
2006-10-04 06:57:07 +00:00
5d9fd977d3
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
...
extra operand to LOADX to specify the exact value extension type.
llvm-svn: 30714
2006-10-04 00:56:09 +00:00
f598d73142
Fix PR933 and CodeGen/X86/2006-10-02-BoolRetCrash.ll
...
llvm-svn: 30703
2006-10-03 17:18:42 +00:00
fc36039f86
silence warnings in release build
...
llvm-svn: 30631
2006-09-27 18:29:38 +00:00
104aa5dbc1
Various random and minor code cleanups.
...
llvm-svn: 30608
2006-09-26 03:57:53 +00:00
c68bbef874
Fix compile error.
...
llvm-svn: 30553
2006-09-21 02:08:31 +00:00
3c5b3df6a0
Adding codegeneration for StdCall & FastCall calling conventions
...
llvm-svn: 30549
2006-09-20 22:03:51 +00:00
6f7072c66a
Added some eye-candy for Subtarget type checking
...
Added X86 StdCall & FastCall calling conventions. Codegen will follow.
llvm-svn: 30446
2006-09-17 20:25:45 +00:00
Dan Gohman