Commit Graph

55 Commits

Author SHA1 Message Date
Richard Sandiford ee8343822e [SystemZ] Be more careful about inverting CC masks (conditional loads)
Extend r187495 to conditional loads.  I split this out because the
easiest way seemed to be to force a particular operand order in
SystemZISelDAGToDAG.cpp.

llvm-svn: 187496
2013-07-31 12:38:08 +00:00
Richard Sandiford 6a06ba36ba [SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()
r186399 aggressively used the RISBG instruction for immediate ANDs,
both because it can handle some values that AND IMMEDIATE can't,
and because it allows the destination register to be different from
the source.  I realized later while implementing the distinct-ops
support that it would be better to leave the choice up to
convertToThreeAddress() instead.  The AND IMMEDIATE form is shorter
and is less likely to be cracked.

This is a problem for 32-bit ANDs because we assume that all 32-bit
operations will leave the high word untouched, whereas RISBG used in
this way will either clear the high word or copy it from the source
register.  The patch uses the z196 instruction RISBLG for this instead.

This means that z10 will be restricted to NILL, NILH and NILF for
32-bit ANDs, but I think that should be OK for now.  Although we're
using z10 as the base architecture, the optimization work is going
to be focused more on z196 and zEC12.

llvm-svn: 187492
2013-07-31 11:36:35 +00:00
Richard Sandiford 5109321042 [SystemZ] Use RNSBG
This should be the last of the R.SBG patches for now.

llvm-svn: 186573
2013-07-18 10:40:35 +00:00
Richard Sandiford 297f7d2724 [SystemZ] Generalize RxSBG SRA case
The original code only folded SRA into ROTATE ... SELECTED BITS
if there was no outer shift.  This patch splits out that check
and generalises it slightly.  The extra cases aren't really that
interesting, but this is paving the way for RNSBG support.

llvm-svn: 186571
2013-07-18 10:14:55 +00:00
Richard Sandiford 7878b852e6 [SystemZ] Use RXSBG
Extend the previous R.SBG patches to handle XORs.

llvm-svn: 186570
2013-07-18 10:06:15 +00:00
Richard Sandiford 5cbac96730 [SystemZ] Rename and formatting fixes
In hindsight, using "RISBG" for something that can be any type of
R.SBG instruction was a bit confusing, so this renames it to RxSBG.
That might not be the best choice either, since there is an instruction
called RXSBG, but hopefully the lower-case letter stands out enough.

While there I fixed a couple of GNUisms that had crept in --
sorry about that!

llvm-svn: 186569
2013-07-18 09:45:08 +00:00
Aaron Ballman fbb104513b Silencing an MSVC warning about signed vs unsigned comparison mismatches.
llvm-svn: 186529
2013-07-17 19:43:13 +00:00
Richard Sandiford 885140c951 [SystemZ] Use ROSBG and non-zero form of RISBG for OR nodes
llvm-svn: 186405
2013-07-16 11:55:57 +00:00
Richard Sandiford 82ec87dbdb [SystemZ] Use RISBG for (shift (and ...))
Another patch in the series to make more use of R.SBG.  This one extends
r186072 and r186073 to handle cases where the AND is inside the shift.

llvm-svn: 186399
2013-07-16 11:02:24 +00:00
Richard Sandiford ea9b6aa20b [SystemZ] Use zeroing form of RISBG for shift-and-AND sequences
Extend r186072 to handle shifts and ANDs.

llvm-svn: 186073
2013-07-11 09:10:09 +00:00
Richard Sandiford 84f54a3bc9 [SystemZ] Use zeroing form of RISBG for some AND sequences
RISBG can handle some ANDs for which no AND IMMEDIATE exists.
It also acts as a three-operand AND for some cases where an
AND IMMEDIATE could be used instead.

It might be worth adding a pass to replace RISBG with AND IMMEDIATE
in cases where the register operands end up being the same and where
AND IMMEDIATE is smaller.

llvm-svn: 186072
2013-07-11 08:59:12 +00:00
Richard Sandiford 9784649157 [SystemZ] Use MVC for simple load/store pairs
Look for patterns of the form (store (load ...), ...) in which the two
locations are known not to partially overlap.  (Identical locations are OK.)
These sequences are better implemented by MVC unless either the load or
the store could use RELATIVE LONG instructions.

The testcase showed that we weren't using LHRL and LGHRL for extload16,
only sextloadi16.  The patch fixes that too.

llvm-svn: 185919
2013-07-09 09:46:39 +00:00
Andrew Trick ef9de2a739 Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

llvm-svn: 182703
2013-05-25 02:42:55 +00:00
Ulrich Weigand 5f613dfd1f [SystemZ] Add back end
This adds the actual lib/Target/SystemZ target files necessary to
implement the SystemZ target.  Note that at this point, the target
cannot yet be built since the configure bits are missing.  Those
will be provided shortly by a follow-on patch.

This version of the patch incorporates feedback from reviews by
Chris Lattner and Anton Korobeynikov.  Thanks to all reviewers!

Patch by Richard Sandiford.

llvm-svn: 181203
2013-05-06 16:15:19 +00:00
Dan Gohman dfc96aea90 Remove the SystemZ backend.
llvm-svn: 142878
2011-10-24 23:48:32 +00:00
Chris Lattner 0e023ea02a fix a long standing wart: all the ComplexPattern's were being
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.

llvm-svn: 114471
2010-09-21 20:31:19 +00:00
Chris Lattner 65b48b5dfc zap dead code.
llvm-svn: 113073
2010-09-04 18:12:00 +00:00
Jakob Stoklund Olesen e02996ca8f Merge the SystemZ subreg_even32 SubRegIndex into subreg_32bit. The SubRegIndices
were overspecified when inheriting sub-subregisters, for instance:

R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit.

This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous.

llvm-svn: 105063
2010-05-28 23:48:29 +00:00
Jakob Stoklund Olesen 36caaf1c59 Use enums instead of literals for SystemZ subregisters
llvm-svn: 104612
2010-05-25 17:04:18 +00:00
Dan Gohman 21cea8ac2e Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635
2010-04-17 15:26:15 +00:00
Chris Lattner f98f124a73 Sink InstructionSelect() out of each target into SDISel, and rename it
DoInstructionSelection.  Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.

Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.

 17 files changed, 114 insertions(+), 430 deletions(-)

llvm-svn: 97555
2010-03-02 06:34:30 +00:00
Evan Cheng 5e73ff2e3a Split SelectionDAGISel::IsLegalAndProfitableToFold to
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.

This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.

llvm-svn: 96255
2010-02-15 19:41:07 +00:00
Chris Lattner b06015aa69 move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
2010-02-09 19:54:29 +00:00
Dan Gohman ea6f91ff64 Change SelectCode's argument from SDValue to SDNode *, to make it more
clear what information these functions are actually using.

This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.

llvm-svn: 92564
2010-01-05 01:24:18 +00:00
Anton Korobeynikov d91a14dba5 Fix invalid chain folding for memory variant of sdiv / udiv
llvm-svn: 92472
2010-01-04 10:31:54 +00:00
Dan Gohman b15f4a1cbd Remove uninteresting and confusing debug output.
llvm-svn: 86149
2009-11-05 18:47:09 +00:00
Dan Gohman 32f71d714b Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.

llvm-svn: 82790
2009-09-25 18:54:59 +00:00
Daniel Dunbar 34ee203337 Fix some refactos for iostream changes (in -Asserts mode).
- The world needs better C++ refactoring tools, can I get an Amen!?

llvm-svn: 79843
2009-08-23 08:50:52 +00:00
Chris Lattner 317dbbcfb1 eliminate uses of cerr()
llvm-svn: 79834
2009-08-23 07:05:07 +00:00
Chris Lattner af29ea6d57 eliminate the last DOUTs from the targets.
llvm-svn: 79833
2009-08-23 06:49:22 +00:00
Owen Anderson 9f94459d24 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713
2009-08-11 20:47:22 +00:00
Owen Anderson 53aa7a960c Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
Daniel Dunbar 7ecc62d8c1 Fix 'may be used uninitialized' warning.
- Anton, please review.

llvm-svn: 76144
2009-07-17 02:19:26 +00:00
Anton Korobeynikov 02fc607d54 Unbreak
llvm-svn: 76064
2009-07-16 14:36:52 +00:00
Anton Korobeynikov 3ae30e08ef Fix logic inversion for RI-mode address selection
llvm-svn: 76052
2009-07-16 14:31:14 +00:00
Anton Korobeynikov 70d0bceed6 Unbreak mvi and friends - emit only 'significant' part of the operand
llvm-svn: 76041
2009-07-16 14:26:38 +00:00
Anton Korobeynikov b25949b0f5 Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide problems
llvm-svn: 76011
2009-07-16 14:18:17 +00:00
Anton Korobeynikov e5b04d7102 Use divide single for 32 bit signed divides
llvm-svn: 76010
2009-07-16 14:17:52 +00:00
Anton Korobeynikov e0ad108f04 Remove redundand register move
llvm-svn: 76004
2009-07-16 14:14:54 +00:00
Anton Korobeynikov fe8df8ff61 Properly handle divides. As a bonus - implement memory versions of them.
llvm-svn: 76003
2009-07-16 14:14:33 +00:00
Anton Korobeynikov 34ad780d0d 32 bit shifts have only 12 bit displacements
llvm-svn: 76000
2009-07-16 14:13:24 +00:00
Anton Korobeynikov d8458e6c09 Typos
llvm-svn: 75991
2009-07-16 14:10:35 +00:00
Anton Korobeynikov 1eb6262b4b Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.
llvm-svn: 75990
2009-07-16 14:10:17 +00:00
Anton Korobeynikov 62f8515b1c Add support for 12 bit displacements
llvm-svn: 75988
2009-07-16 14:09:35 +00:00
Anton Korobeynikov ec66c122e0 32-bit ri addressing mode has only 12-bit displacement
llvm-svn: 75973
2009-07-16 14:03:41 +00:00
Anton Korobeynikov 8a095bf56d Swap the order of imm and idx field for rri addrmode in order to make handling of rri and ri addrmodes common
llvm-svn: 75937
2009-07-16 13:48:42 +00:00
Anton Korobeynikov 19911b338a Do not truncate sign bits for negative imms
llvm-svn: 75936
2009-07-16 13:48:23 +00:00
Anton Korobeynikov 405833dfb6 Add address computation stuff
llvm-svn: 75935
2009-07-16 13:47:59 +00:00
Anton Korobeynikov 44f8bbfb3f Add stores and truncstores
llvm-svn: 75931
2009-07-16 13:45:00 +00:00
Anton Korobeynikov 11b91b4e2e Add patterns for various extloads
llvm-svn: 75930
2009-07-16 13:44:30 +00:00