fc12e7016c
Make ARM hint ranges consistent, and add tests for these ranges
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llvm-svn: 193238
2013-10-23 10:14:40 +00:00
87dacc38b8
Add hint disassembly syntax for 16-bit Thumb hint instructions.
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Patch by Artyom Skrobov
llvm-svn: 192972
2013-10-18 14:09:49 +00:00
78f9572f39
Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
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While the .td entry is nice and all, it takes a pretty gross hack in
ARMAsmParser::ParseInstruction() because of handling of other "subs"
instructions to get it to match. Ran it by Jim Grosbach and he said it was
about what he expected to make this work given the existing code.
rdar://14214063
llvm-svn: 187530
2013-07-31 21:05:30 +00:00
a6f5542be4
ARM: operands should be explicit when disassembled
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llvm-svn: 184943
2013-06-26 13:39:07 +00:00
4b6c076da3
ARM: enable decoding of pc-relative PLD/PLI
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llvm-svn: 184701
2013-06-24 09:11:38 +00:00
aa7fdf8741
ARM: add operands pre-writeback variants when needed
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llvm-svn: 184181
2013-06-18 08:12:51 +00:00
4d3e3f279e
ARM: fix thumb literal loads decoding
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This fixes two previous issues:
- Negative offsets were not correctly disassembled
- The decoded opcodes were not the right one
llvm-svn: 184180
2013-06-18 08:03:06 +00:00
bd2b610eba
ARM: fix B decoding
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llvm-svn: 183914
2013-06-13 16:41:55 +00:00
43cb13a5c9
ARM: ISB cannot be passed the same options as DMB
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ISB should only accepts full system sync, other options are reserved
llvm-svn: 183656
2013-06-10 14:17:08 +00:00
772cf466da
Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when the upper bit is set.
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They should always be zero-extended, not sign extended. Added test case.
llvm-svn: 178275
2013-03-28 19:22:28 +00:00
f686be4674
Patch by Gordon Keiser!
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If PC or SP is the destination, the disassembler erroneously failed with the
invalid encoding, despite the manual saying that both are fine.
This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a
postindexed load, where the offset 0xc is applied to SP after the load occurs.
llvm-svn: 178017
2013-03-26 13:58:53 +00:00
6fd9624843
Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target
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is 24 bits not 20 and the decoding needed to correctly handle converting the
J1 and J2 bits to their I1 and I2 values to reconstruct the displacement.
llvm-svn: 166982
2012-10-29 23:27:20 +00:00
6a43bf7d74
Fix #13035 , a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue.
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llvm-svn: 161162
2012-08-02 08:29:50 +00:00
288e1af8c8
Fix #13138 , a bug around ARM instruction DSB encoding and decoding issue.
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llvm-svn: 161161
2012-08-02 08:21:27 +00:00
10dd40e42d
Fix #13241 , a bug around shift immediate operand for ARM instruction ADR.
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llvm-svn: 161159
2012-08-02 08:13:13 +00:00
8a8e9d1b63
Specify cpu to unbreak tests.
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llvm-svn: 155604
2012-04-26 01:38:10 +00:00
287d6ef088
Fix an incorrect decoder test.
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llvm-svn: 140579
2011-09-26 23:08:34 +00:00
737beaf86d
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
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llvm-svn: 140420
2011-09-23 21:26:40 +00:00
987a878946
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
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llvm-svn: 140415
2011-09-23 21:07:25 +00:00
f52c68f0ca
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123 ] rather than simply #123 .
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llvm-svn: 140283
2011-09-21 23:44:46 +00:00
2b35d7cff1
Port over more Thumb2 encoding tests to decoding tests.
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llvm-svn: 140152
2011-09-20 17:44:48 +00:00
ddfcec92d9
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
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llvm-svn: 140032
2011-09-19 18:07:10 +00:00
09a9b6b953
Add a testcase for another corner-case decoding.
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llvm-svn: 139970
2011-09-16 23:15:29 +00:00
3ca958cd19
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
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llvm-svn: 139964
2011-09-16 22:29:48 +00:00
9764bced10
Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.
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llvm-svn: 139958
2011-09-16 22:17:02 +00:00
fe82365cb0
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
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llvm-svn: 139943
2011-09-16 21:08:33 +00:00
30fc19a6dd
Port over more Thumb2 assembly tests to disassembly tests.
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llvm-svn: 139915
2011-09-16 17:56:04 +00:00
b489e3b408
Port over more Thumb2 assembly tests to disassembly tests.
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llvm-svn: 139912
2011-09-16 17:22:48 +00:00
3eb2470eed
Make use of Eli's FileCheck sorcery to improve this test.
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llvm-svn: 139645
2011-09-13 21:37:50 +00:00
7f0e98fd7f
Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.
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llvm-svn: 139639
2011-09-13 20:46:26 +00:00
a9ebf6fb64
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
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llvm-svn: 139522
2011-09-12 18:56:30 +00:00
5bfb0e0a85
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
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llvm-svn: 139422
2011-09-09 22:24:36 +00:00
cd5612d3a5
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
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llvm-svn: 139240
2011-09-07 17:55:19 +00:00
b041e866b0
Port more encoding tests over to Thumb2 decoding tests.
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llvm-svn: 139171
2011-09-06 20:26:34 +00:00
2fa06a7226
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
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llvm-svn: 138840
2011-08-30 22:58:27 +00:00
2e282257ed
Port Thumb2 assembler tests over to disassembler tests.
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llvm-svn: 138822
2011-08-30 20:03:11 +00:00
Artyom Skrobov