Commit Graph

5063 Commits

Author SHA1 Message Date
Yaxun (Sam) Liu 0309e50f33 [Driver] Fix ToolChain::getSanitizerArgs
The driver uses class SanitizerArgs to store parsed sanitizer arguments. It keeps a cached
SanitizerArgs object in ToolChain and uses it for different jobs. This does not work if
the sanitizer options are different for different jobs, which could happen when an
offloading toolchain translates the options for different jobs.

To fix this, SanitizerArgs should be created by using the actual arguments passed
to jobs instead of the original arguments passed to the driver, since the toolchain
may change the original arguments. And the sanitizer arguments should be diagnose
once.

This patch also fixes HIP toolchain for handling -fgpu-sanitize: a warning is emitted
for GPU's not supporting sanitizer and skipped. This is for backward compatibility
with existing -fsanitize options. -fgpu-sanitize is also turned on by default.

Reviewed by: Artem Belevich, Evgenii Stepanov

Differential Revision: https://reviews.llvm.org/D111443
2021-11-11 17:17:08 -05:00
Zahira Ammarguellat f04e387055 Making the code compliant to the documentation about Floating Point
support default values for C/C++. FPP-MODEL=PRECISE enables
FFP-CONTRACT(FMA is enabled).

Fix for https://bugs.llvm.org/show_bug.cgi?id=50222
2021-11-11 07:40:35 -05:00
Fangrui Song a77d1f68a0 [Driver] Change Linux::isPIEDefault to true for all Android versions
Currently any API level>=16 uses default PIE.
If API level<16 is too old to be supported, we can clean up some code.

Reviewed By: danalbert

Differential Revision: https://reviews.llvm.org/D113370
2021-11-11 00:12:07 -08:00
Roland McGrath ff11f0aa5d [Clang] Pass -z rel to linker for Fuchsia
Fuchsia already supports the more compact relocation format.
Make it the default.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D113136
2021-11-10 13:31:22 -08:00
Kostya Serebryany b7f3a4f4fa [sancov] add tracing for loads and store
add tracing for loads and stores.

The primary goal is to have more options for data-flow-guided fuzzing,
i.e. use data flow insights to perform better mutations or more agressive corpus expansion.
But the feature is general puspose, could be used for other things too.

Pipe the flag though clang and clang driver, same as for the other SanitizerCoverage flags.
While at it, change some plain arrays into std::array.

Tests: clang flags test, LLVM IR test, compiler-rt executable test.

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D113447
2021-11-09 14:35:13 -08:00
Ard Biesheuvel 24772720c5 [ARM] reject -mtp=cp15 if target subarch does not support it
Currently, we permit -mtp=cp15 even for targets that don't implement the
TLS register. When building for ARMv6 or earlier, this means we emit
instructions that will UNDEF at runtime. For Thumb1, passing -mtp=cp15
will trigger an assert in the backend.

So let's add some diagnostics to ensure that -mtp=cp15 is only accepted
for ARMv6T2 or newer.

Reviewed By: nickdesaulniers

Differential Revision: https://reviews.llvm.org/D113026
2021-11-09 18:29:30 +01:00
Ard Biesheuvel a19da876ab [ARM] implement support for TLS register based stack protector
Implement support for loading the stack canary from a memory location held in
the TLS register, with an optional offset applied. This is used by the Linux
kernel to implement per-task stack canaries, which is impossible on SMP systems
when using a global variable for the stack canary.

Reviewed By: nickdesaulniers

Differential Revision: https://reviews.llvm.org/D112768
2021-11-09 18:19:47 +01:00
Aaron Ballman 190bde404c Revert "Making the code compliant to the documentation about Floating Point"
This reverts commit 438437cbb6.

There are still broken bots from this:

https://lab.llvm.org/buildbot/#/builders/188/builds/5495
https://lab.llvm.org/buildbot/#/builders/171/builds/5710
2021-11-08 11:43:49 -05:00
Zahira Ammarguellat 438437cbb6 Making the code compliant to the documentation about Floating Point
support default values for C/C++. FPP-MODEL=PRECISE enables FFP-CONTRACT
FMA is enabled.

Fix for https://bugs.llvm.org/show_bug.cgi?id=50222
2021-11-08 08:35:19 -05:00
Nico Weber 0425087b8b Revert "Making the code compliant to the documentation about Floating Point"
This reverts commit 17d9560294.
Breaks check-clang everywhere, see e.g.:
https://lab.llvm.org/buildbot/#/builders/105/builds/17229
https://lab.llvm.org/buildbot/#/builders/109/builds/25831
https://lab.llvm.org/buildbot/#/builders/188/builds/5493
https://lab.llvm.org/buildbot/#/builders/123/builds/7073
2021-11-08 08:32:42 -05:00
Zahira Ammarguellat 17d9560294 Making the code compliant to the documentation about Floating Point
support default values for C/C++. FPP-MODEL=PRECISE enables FFP-CONTRACT
FMA is enabled.

Fix for https://bugs.llvm.org/show_bug.cgi?id=50222
2021-11-08 07:51:29 -05:00
Shao-Ce SUN 5c3d7184b4 [RISCV] Support Zfhmin extension
According to RISC-V Unprivileged ISA 15.6.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D111866
2021-11-06 01:41:02 +08:00
Kazushi (Jam) Marukawa 3d32218d1a [VE] Change to omitting the frame pointer on leaf functions
Change to omitting the frame pointer on leaf functions by default for VE.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D113087
2021-11-03 17:45:18 +09:00
Yaxun (Sam) Liu 60a085beb0 Revert "[clang] deprecate frelaxed-template-template-args, make it on by default"
This reverts commit 2d7fba5f95.

The patch was reverted because it caused regression with rocThrust
due to ambiguity of template specialization.

For details please see https://reviews.llvm.org/D109496
2021-11-02 17:02:19 -04:00
Mubashar Ahmad 0b83a18a2b [AArch64] Enablement of Cortex-X2
Enables support for Cortex-X2 cores.

Differential Revision: https://reviews.llvm.org/D112459
2021-11-01 11:55:24 +00:00
Keith Smiley bd8a9507ef [clang][driver] Fix multiarch output name with -Wl arg
Previously if you passed a `-Wl,-foo` _before_ the source filename, the
first `InputInfos`, which is used for the base input name would be an
`InputArg` kind, which would never have a base input name. Now we use
that by default, but pick the first `InputInfo` that is of kind
`Filename` to get the name from if there is one.

Differential Revision: https://reviews.llvm.org/D112767
2021-10-29 10:09:38 -07:00
Martin Storsjö d758069f5e [clang] [MinGW] Guess the right ix86 arch name spelling as sysroot
For x86, most contempory mingw toolchains use i686 as 32 bit
x86 arch target.

As long as the target triple is set to the right form, this works
fine, either as the compiler's default target, or via e.g.
a triple prefix like i686-w64-mingw32-clang.

However, if the unprefixed toolchain targets x86_64, but the user
tries to switch it to target 32 bit by adding the -m32 option, the
computeTargetTriple function in Clang, together with
Triple::get32BitArchVariant, sets the arch to i386. This causes
the right sysroot to not be found.

When targeting an arch where there are potential spelling ambiguities
with respect to the sysroots (i386 and arm), check if the driver can
find a sysroot with the arch name - if not, try a couple other
candidates.

Differential Revision: https://reviews.llvm.org/D111952
2021-10-29 09:32:36 +03:00
Alex Lorenz 3d0d7d8c5b [clang][driver][darwin] support -target with Mac Catalyst triple without OS version
Some users might omit the version and assume the compiler will target the initial
Mac Catalyst version.
2021-10-28 18:46:10 -07:00
Caroline Concatto 2186b011e9 [Driver][AArch64]Add driver support for neoverse-512tvb target
The support for  neoverse-512tvb mirrors the same option available in GCC[1].
There is no functional effect for this option yet.
This patch ensures the driver accepts "-mcpu=neoverse-512tvb", and enough
plumbing is in place to allow the new option to be used in the future.

[1]https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html

Differential Revision: https://reviews.llvm.org/D112406
2021-10-28 09:08:40 +01:00
YunQiang Su 284c2ebc5e [clang][MIPS] Fix search path for Debian multilib O32
In the situation of multilib, the gcc objects are in a /32 directory. On
Debian, the libraries is under /libo32 to avoid confliction. This patch
enables clang find gcc in /32, and C lib in /libo32.

Differential Revision: https://reviews.llvm.org/D112158
2021-10-28 10:23:06 +03:00
Matheus Izvekov 2d7fba5f95
[clang] deprecate frelaxed-template-template-args, make it on by default
A resolution to the ambiguity issues created by P0522, which is a DR solving
CWG 150, did not come as expected, so we are just going to accept the change,
and watch how users digest it.

For now we deprecate the flag with a warning, and make it on by default.
We don't remove the flag completely in order to give users a chance to
work around any problems by disabling it.

Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>

Reviewed By: rsmith

Differential Revision: https://reviews.llvm.org/D109496
2021-10-27 22:48:27 +02:00
Alexandros Lamprineas 8689f5e6e7 [AArch64] Add support for the 'R' architecture profile.
This change introduces subtarget features to predicate certain
instructions and system registers that are available only on
'A' profile targets. Those features are not present when
targeting a generic CPU, which is the default processor.

In other words the generic CPU now means the intersection of
'A' and 'R' profiles. To maintain backwards compatibility we
enable the features that correspond to -march=armv8-a when the
architecture is not explicitly specified on the command line.

References: https://developer.arm.com/documentation/ddi0600/latest

Differential Revision: https://reviews.llvm.org/D110065
2021-10-27 12:32:30 +01:00
Bradley Smith 0ce46a1d43 [AArch64][Driver][SVE] Allow -msve-vector-bits=<n>+ syntax to mean no maximum vscale
This patch splits the existing SveVectorBits LangOpt into VScaleMin and
VScaleMax LangOpts such that we can represent such an option. The cc1
option has also been split into -mvscale-{min,max}=<n> options so that the
cc1 arguments better reflect the vscale_range IR attribute.

Differential Revision: https://reviews.llvm.org/D111790
2021-10-25 11:10:52 +00:00
Kristof Beyls 49e1753c5e Mark baremetal.cpp test as unsupported on Windows.
A new check was added in 3b93dc68, which seems to not be possible to get
working correctly on windows systems:

The test first "captures" the install directory of the clang toolchain
running the test as follows:
// CHECK-AARCH64-NO-HOST-INC: InstalledDir: [[INSTALLEDDIR:.+]]
Then, in a check line a bit later, it uses this to check if a particular
directory in the toolchain installation directory is included when
targeting aarch64-none-elf:
// CHECK-AARCH64-NO-HOST-INC-SAME: "-internal-isystem" "[[INSTALLEDDIR]]{{[/\\]+}}..{{[/\\]+}}lib{{[/\\]+}}clang-runtimes{{[/\\]+}}aarch64-none-elf{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1"

Even though the test aims to take into account forward vs backward slash
differences between Windows and Unix paths, it still fails on Windows.

It seems that on Windows (this is based on the output log from a Windows
bot), the INSTALLEDDIR variable has the following value:

note: with "INSTALLEDDIR" equal to "c:\\\\b\\\\slave\\\\clang-x64-windows-msvc\\\\build\\\\stage1\\\\bin"

However the actual "InstalledDir:" output produced by the clang
toolchain on that Windows bot was:

InstalledDir: c:\b\slave\clang-x64-windows-msvc\build\stage1\bin

It is unclear where the explosion of backslashes happens. Maybe this is
a bug in FileCheck somewhere?
Anyway, marking this test as not supported on Windows to make the bots
green again.
2021-10-22 11:46:50 +01:00
Kristof Beyls e5b87fb722 Fix baremetal.cpp test to handle windows paths. 2021-10-22 10:24:04 +01:00
Kristof Beyls 3b93dc6880 Add basic aarch64-none-elf bare metal driver.
Differential Revision: https://reviews.llvm.org/D111134
2021-10-22 08:06:17 +01:00
Brad Smith 34188f237f [Driver][OpenBSD] Some improvements to the external assembler handling
- Pass CPU variant for ARM
- Pass MIPS CPU in addition to the ABI
2021-10-20 21:05:14 -04:00
Keith Smiley 17386cb4dc [clang][Driver] Make multiarch output file basenames reproducible
When building a multiarch MachO binary, previously the intermediate
output file names would contain random characters. On macOS this
filename, since it's used when linking, ended up being used as a
stable-ish identifier for the adhoc codesignature of the binary, leading
to non-reproducible binaries. This change uses the architecture, when
available, to create a stable, but unique, basename for the file.

Differential Revision: https://reviews.llvm.org/D111269
2021-10-19 13:49:47 -07:00
Volodymyr Sapsai 91e19f66e5 [driver] Explicitly specify `-fbuild-session-timestamp` in seconds.
Representation of the file's last modification time depends on the file
system and isn't guaranteed to be in seconds. Cast to seconds explicitly
and tighten the test case to check the magnitude of the calculated
value, so we can catch passing milliseconds or nanoseconds.

rdar://83915615

Differential Revision: https://reviews.llvm.org/D111205
2021-10-19 13:30:26 -07:00
Amy Kwan 5eaf5b9161 [PowerPC] Restrict various P10 options to P10 only.
This patch attempts to restrict the following P10 options:
```
-mprefixed
-mpcrel
-mpaired-vector-memops
```
To P10 only. This will prevent the use of these options on P9 and earlier.

The behaviour of this patch looks like the following on pre-P10:
```
$ clang -mcpu=pwr9 -mpaired-vector-memops test.c -o test
error: option '-mpaired-vector-memops' cannot be specified without '-mcpu=pwr10'
$ clang -mcpu=pwr9 -mprefixed test.c -o test
error: option '-mprefixed' cannot be specified without '-mcpu=pwr10'
$ clang -mcpu=pwr9 -mprefixed -mpcrel test.c -o test
error: option '-mpcrel' cannot be specified without '-mcpu=pwr10 -mprefixed'
$ clang -mcpu=pwr9 -mpcrel -mprefixed test.c -o test
error: option '-mpcrel' cannot be specified without '-mcpu=pwr10 -mprefixed'
$ clang -mcpu=pwr9 -mpcrel test.c -o test
error: option '-mpcrel' cannot be specified without '-mcpu=pwr10 -mprefixed'
```

Differential Revision: https://reviews.llvm.org/D109652
2021-10-19 09:01:01 -05:00
David Sherwood 607fb1bb8c [AArch64] Always add -tune-cpu argument to -cc1 driver
This patch ensures that we always tune for a given CPU on AArch64
targets when the user specifies the "-mtune=xyz" flag. In the
AArch64Subtarget if the tune flag is unset we use the CPU value
instead.

I've updated the release notes here:

  llvm/docs/ReleaseNotes.rst

and added tests here:

  clang/test/Driver/aarch64-mtune.c

Differential Revision: https://reviews.llvm.org/D110258
2021-10-19 14:57:51 +01:00
Fangrui Song 408e6de8c0 [Driver][Gnu] Support -shared -static: pass -shared to ld and use crtbeginS.o
This mode never works (mismatching crtbeginT.o and crtendS.o) and probably
unsupported by GCC on glibc based Linux distro (incorrect crtbeginT.o causes
linker error) but makes sense (-shared means building a shared object, -static
means avoid shared object dependencies) and can be used on musl based Linux
distro.

mingw supports this mode as well.
2021-10-19 01:09:41 -07:00
Arthur Eubanks cb5a10199b [test] Remove tests pinned to the legacy PM
Now that the legacy PM is deprecated for the optimization pipeline, we
can start deleting legacy PM tests.

For tests that test both PMs, merge the RUN lines.
Delete tests specific to the legacy PM.
2021-10-18 16:40:46 -07:00
Kito Cheng ff13189c5d [RISCV] Unify the arch string parsing logic to to RISCVISAInfo.
How many place you need to modify when implementing a new extension for RISC-V?

At least 7 places as I know:

- Add new SubtargetFeature at RISCV.td
- -march parser in RISCV.cpp
- RISCVTargetInfo::initFeatureMap@RISCV.cpp for handling feature vector.
- RISCVTargetInfo::getTargetDefines@RISCV.cpp for pre-define marco.
- Arch string parser for ELF attribute in RISCVAsmParser.cpp
- ELF attribute emittion in RISCVAsmParser.cpp, and make sure it's in
  canonical order...
- ELF attribute emittion in RISCVTargetStreamer.cpp, and again, must in
  canonical order...

And now, this patch provide an unified infrastructure for handling (almost)
everything of RISC-V arch string.

After this patch, you only need to update 2 places for implement an extension
for RISC-V:
- Add new SubtargetFeature at RISCV.td, hmmm, it's hard to avoid.
- Add new entry to RISCVSupportedExtension@RISCVISAInfo.cpp or
  SupportedExperimentalExtensions@RISCVISAInfo.cpp .

Most codes are come from existing -march parser, but with few new feature/bug
fixes:
- Accept version for -march, e.g. -march=rv32i2p0.
- Reject version info with `p` but without minor version number like `rv32i2p`.

Differential Revision: https://reviews.llvm.org/D105168
2021-10-17 16:25:23 +08:00
Jinsong Ji 42eea2b69b [AIX] Enable int128 in 64 bit mode
This patch remove the override in AIX target,
so the int128 is enabled in 64 bit mode or with ForceEnableInt128.

Reviewed By: lkail

Differential Revision: https://reviews.llvm.org/D111078
2021-10-15 16:23:04 +00:00
Mubashar Ahmad 97809c828f [AArch64]Enabling Cortex-A510 Support
This patch enables support for Cortex-A510 CPUs.

Reviewed By: MarkMurrayARM, dmgreen

Differential Revision: https://reviews.llvm.org/D109825
2021-10-15 14:31:18 +01:00
Craig Topper f7ba572483 [RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0.
I've removed the Zbs W instructions that are not part of the frozen spec.

References to B as an extension name have been removed. Tests are updated or split accordingly.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D110669
2021-10-14 09:25:03 -07:00
Martin Storsjö b541845ea0 [clang] [Windows] Mark PIC as implicitly enabled for aarch64, just like for x86_64
This doesn't practically affect the code generation.

Differential Revision: https://reviews.llvm.org/D111707
2021-10-13 22:55:00 +03:00
Yaxun (Sam) Liu 1439df00fc [HIP] Fix test rcom-detect.hip
This patches fixes https://bugs.llvm.org/show_bug.cgi?id=51404

Some builds use custom resource directory for clang, therefore the test
cannot assume default resource directory for clang. Use -resource-dir
to force it.

Differential Revision: https://reviews.llvm.org/D111726
2021-10-13 15:01:07 -04:00
Ahmed Bougacha c30a52852b [Driver] Re-enable aarch64-cpus.c test for arm64-apple.
"darwin" is ambiguous.  When there isn't a better source
of truth (e.g., SDKs), the driver will either interpret it
as "iOS" when cross-compiling to a different architecture,
or "the host" when not.  That's now the case on AS Macs.

Update the test to more explicitly test the OS.
aarch64-mac-cpus.c already tests the mac-specific driver logic.
2021-10-11 18:46:26 -07:00
Haowei Wu 998e067a0a Reland "[clang][Fuchsia] Support availability attr on Fuchsia"
This reland commit 1131b1eb35, which
adds support to __attribute__((availability)) annotation for Fuchsia
platform. This patch also adds '-ffuchsia-api-level' to allow specify
Fuchsia API level from the command line.

Differential Revision: https://reviews.llvm.org/D108592
2021-10-11 18:41:29 -07:00
Haowei Wu b5e8348bf2 Revert "[clang][Fuchsia] Support availability attr on Fuchsia"
This reverts commit 1131b1eb35, which
breaks several llvm bots.
2021-10-11 17:32:38 -07:00
Haowei Wu 1131b1eb35 [clang][Fuchsia] Support availability attr on Fuchsia
This patch adds support to __attribute__((availability)) annotation for
Fuchsia platform. This patch also adds '-ffuchsia-api-level' to allow
specify Fuchsia API level from the command line.

Differential Revision: https://reviews.llvm.org/D108592
2021-10-11 15:33:04 -07:00
Jinsong Ji 64d1d5f336 [AIX] Unsupported newly added AMDGPU clang test 2021-10-11 21:34:48 +00:00
Victor Campos 3550e242fa [Clang][ARM][AArch64] Add support for Armv9-A, Armv9.1-A and Armv9.2-A
armv9-a, armv9.1-a and armv9.2-a can be targeted using the -march option
both in ARM and AArch64.

 - Armv9-A maps to Armv8.5-A.
 - Armv9.1-A maps to Armv8.6-A.
 - Armv9.2-A maps to Armv8.7-A.
 - The SVE2 extension is enabled by default on these architectures.
 - The cryptographic extensions are disabled by default on these
 architectures.

The Armv9-A architecture is described in the Arm® Architecture Reference
Manual Supplement Armv9, for Armv9-A architecture profile
(https://developer.arm.com/documentation/ddi0608/latest).

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D109517
2021-10-11 17:44:09 +01:00
Fangrui Song 3db1ade368 [Driver][test] Fix undefined-libs.cpp when CLANG_DEFAULT_UNWINDLIB is libunwind 2021-10-08 14:40:22 -07:00
Masoud Ataei b0f68791f0 [clang] Option control afn flag
Clang option to set/unset afn fast-math flag.

 Differential: https://reviews.llvm.org/D106191
 Reviewd with: aaron.ballman, erichkeane, and others
2021-10-08 14:26:14 -04:00
Saiyedul Islam 35ebe4cc24 [Clang][OpenMP] Add partial support for Static Device Libraries
An archive containing device code object files can be passed to
clang command line for linking. For each given offload target
it creates a device specific archives which is either passed to llvm-link
if the target is amdgpu, or to clang-nvlink-wrapper if the target is
nvptx. -L/-l flags are used to specify these fat archives on the command
line. E.g.
  clang++ -fopenmp -fopenmp-targets=nvptx64 main.cpp -L. -lmylib

It currently doesn't support linking an archive directly, like:
  clang++ -fopenmp -fopenmp-targets=nvptx64 main.cpp libmylib.a

Linking with x86 offload also does not work.

Reviewed By: ye-luo

Differential Revision: https://reviews.llvm.org/D105191
2021-10-08 09:37:51 +00:00
Craig Topper f2ad8c9dc6 [RISCV] Remove experimental-b extension that includes all Zb* extensions
At this point it looks like a B extension will never exist. Instead
Zba, Zbb, Zbc, and Zbs are individual extensions being ratified
together as a package. Unknown at this time when or if the other
Zb* extensions will be ratified.

This patch removes references to the B extension. I've updated and
split tests accordingly.

This has been split from D110669 to make review a little easier.

Differential Revision: https://reviews.llvm.org/D111338
2021-10-07 20:47:17 -07:00
Keith Smiley 9f9ed7a81a [clang] Fix darwin REQUIRES test annotation (NFC)
Some subprojects like compiler-rt define the `darwin` feature in their
lit config, but clang does not do that, so we need to use the global
`system-darwin` here instead.

Differential Revision: https://reviews.llvm.org/D111267
2021-10-07 12:58:49 -07:00