Commit Graph

18130 Commits

Author SHA1 Message Date
Eli Bendersky 597fc1233a In this patch, we teach X86_64TargetMachine that it has a ILP32
(defined by the x32 ABI) mode, in which case its pointers are 32-bits
in size. This knowledge is also added to X86RegisterInfo that now
returns the appropriate registers in getPointerRegClass.

There are many outcomes to this change. In order to keep the patches
separate and manageable, we start by focusing on some simple testable
cases. The patch adds a test with passing a pointer to a function -
focusing on the difference between the two data models for x86-64.
Another test is added for handling of 'sret' arguments (and
functionality is added in X86ISelLowering to make it work).

A note on naming: the "x32 ABI" document refers to the AMD64
architecture (in LLVM it's distinguished by being is64Bits() in the
x86 subtarget) with two variations: the LP64 (default) data model, and
the ILP32 data model. This patch adds predicates to the subtarget
which are consistent with this naming scheme.

llvm-svn: 173503
2013-01-25 22:07:43 +00:00
Eli Bendersky 158ea095c0 Add back a RUN line removed by mistake by a previous commit
llvm-svn: 173502
2013-01-25 21:58:09 +00:00
Richard Osborne 6b86eec819 Add instruction encodings / disassembly support for l4r instructions.
llvm-svn: 173501
2013-01-25 21:55:32 +00:00
Eli Bendersky e6abe83258 Now that llvm-dwarfdump supports flags to specify which DWARF section to dump,
use them in tests that run llvm-dwarfdump. This is in order to make tests as
specific as possible.

llvm-svn: 173498
2013-01-25 21:44:53 +00:00
Hal Finkel 1a57ba57a2 Improve the !add TableGen test case.
Suggested by Sean Silva.

llvm-svn: 173481
2013-01-25 20:29:25 +00:00
Eli Bendersky 7a94daa170 Add command-line flags for DWARF dumping.
Flags for dumping specific DWARF sections added in lib/DebugInfo and
llvm-dwarfdump.

llvm-svn: 173480
2013-01-25 20:26:43 +00:00
Richard Osborne a19fa86a70 Add instruction encodings / disassembly support for l5r instructions.
llvm-svn: 173479
2013-01-25 20:20:07 +00:00
Evgeniy Stepanov fac8403249 [msan] Implement exact shadow propagation for relational ICmp.
Only for integers, pointers, and vectors of those. No floats.
Instrumentation seems very heavy, and may need to be replaced
with some approximation in the future.

llvm-svn: 173452
2013-01-25 15:31:10 +00:00
Hal Finkel c7d4dc13a4 Add an addition operator to TableGen
This adds an !add(a, b) operator to tablegen; this will be used
to cleanup the PPC register definitions.

llvm-svn: 173445
2013-01-25 14:49:08 +00:00
Silviu Baranga 3eb45a03af Fixed the condition codes for the atomic64 min/umin code generation on ARM. If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation.
llvm-svn: 173437
2013-01-25 10:39:49 +00:00
Andrew Trick e2c3f5c982 MIsched: Improve the interface to SchedDFS analysis (subtrees).
Allow the strategy to select SchedDFS. Allow the results of SchedDFS
to affect initialization of the scheduler state.

llvm-svn: 173425
2013-01-25 06:33:57 +00:00
Chandler Carruth ceff222dea Switch this code away from Value::isUsedInBasicBlock. That code either
loops over instructions in the basic block or the use-def list of the
value, neither of which are really efficient when repeatedly querying
about values in the same basic block.

What's more, we already know that the CondBB is small, and so we can do
a much more efficient test by counting the uses in CondBB, and seeing if
those account for all of the uses.

Finally, we shouldn't blanket fail on any such instruction, instead we
should conservatively assume that those instructions are part of the
cost.

Note that this actually fixes a bug in the pass because
isUsedInBasicBlock has a really terrible bug in it. I'll fix that in my
next commit, but the fix for it would make this code suddenly take the
compile time hit I thought it already was taking, so I wanted to go
ahead and migrate this code to a faster & better pattern.

The bug in isUsedInBasicBlock was also causing other tests to test the
wrong thing entirely: for example we weren't actually disabling
speculation for floating point operations as intended (and tested), but
the test passed because we failed to speculate them due to the
isUsedInBasicBlock failure.

llvm-svn: 173417
2013-01-25 05:40:09 +00:00
Andrew Trick 44f750a3e5 MISched: Add SchedDFSResult to ScheduleDAGMI to formalize the
interface and allow other strategies to select it.

llvm-svn: 173413
2013-01-25 04:01:04 +00:00
Jack Carter 07c818d2da This patch implements parsing the .word
directive for the Mips assembler.

Contributer: Vladimir Medic
 
llvm-svn: 173407
2013-01-25 01:31:34 +00:00
Akira Hatanaka 28aed9ca85 [mips] Set flag neverHasSideEffects flag on some of the floating point instructions.
llvm-svn: 173401
2013-01-25 00:20:39 +00:00
Benjamin Kramer 1c4e323fdd Reapply chandlerc's r173342 now that the miscompile it was triggering is fixed.
Original commit message:
Plug TTI into the speculation logic, giving it a real cost interface
that can be specialized by targets.

The goal here is not to be more aggressive, but to just be more accurate
with very obvious cases. There are instructions which are known to be
truly free and which were not being modeled as such in this code -- see
the regression test which is distilled from an inner loop of zlib.

Everywhere the TTI cost model is insufficiently conservative I've added
explicit checks with FIXME comments to go add proper modelling of these
cost factors.

If this causes regressions, the likely solution is to make TTI even more
conservative in its cost estimates, but test cases will help here.

llvm-svn: 173357
2013-01-24 16:44:25 +00:00
Benjamin Kramer 435eba09b7 ConstantFolding: Add a missing folding that leads to a miscompile.
We use constant folding to see if an intrinsic evaluates to the same value as a
constant that we know. If we don't take the undefinedness into account we get a
value that doesn't match the actual implementation, and miscompiled code.

This was uncovered by Chandler's simplifycfg changes.

llvm-svn: 173356
2013-01-24 16:28:28 +00:00
Chandler Carruth 321c6a7c50 Revert r173342 temporarily. It appears to cause a very late miscompile
of stage2 in a bootstrap. Still investigating....

llvm-svn: 173343
2013-01-24 13:24:24 +00:00
Chandler Carruth 5f4519309f Plug TTI into the speculation logic, giving it a real cost interface
that can be specialized by targets.

The goal here is not to be more aggressive, but to just be more accurate
with very obvious cases. There are instructions which are known to be
truly free and which were not being modeled as such in this code -- see
the regression test which is distilled from an inner loop of zlib.

Everywhere the TTI cost model is insufficiently conservative I've added
explicit checks with FIXME comments to go add proper modelling of these
cost factors.

If this causes regressions, the likely solution is to make TTI even more
conservative in its cost estimates, but test cases will help here.

llvm-svn: 173342
2013-01-24 12:39:29 +00:00
Chandler Carruth 01bffaad03 Address a large chunk of this FIXME by accumulating the cost for
unfolded constant expressions rather than checking each one
independently.

llvm-svn: 173341
2013-01-24 12:05:17 +00:00
Chandler Carruth 8a21005cca Switch the constant expression speculation cost evaluation away from
a cost fuction that seems both a bit ad-hoc and also poorly suited to
evaluating constant expressions.

Notably, it is missing any support for trivial expressions such as
'inttoptr'. I could fix this routine, but it isn't clear to me all of
the constraints its other users are operating under.

The core protection that seems relevant here is avoiding the formation
of a select instruction wich a further chain of select operations in
a constant expression operand. Just explicitly encode that constraint.

Also, update the comments and organization here to make it clear where
this needs to go -- this should be driven off of real cost measurements
which take into account the number of constants expressions and the
depth of the constant expression tree.

llvm-svn: 173340
2013-01-24 11:53:01 +00:00
Kostya Serebryany 87191f6221 [asan] adaptive redzones for globals (the larger the global the larger is the redzone)
llvm-svn: 173335
2013-01-24 10:35:40 +00:00
Reed Kotler a2d76bce1f The next phase of Mips16 hard float implementation.
Allow Mips16 routines to call Mips32 routines that have abi requirements
that either arguments or return values are passed in floating point 
registers. This handles only the pic case. We have not done non pic
for Mips16 yet in any form.

The libm functions are Mips32, so with this addition we have a complete
Mips16 hard float implementation.

We still are not able to complete mix Mip16 and Mips32 with hard float.
That will be the next phase which will have several steps. For Mips32
to freely call Mips16 some stub functions must be created.

llvm-svn: 173320
2013-01-24 04:24:02 +00:00
Benjamin Kramer d9c3dabbba ConstantFolding: Evaluate GEP indices in the index type.
This fixes some edge cases that we would get wrong with uint64_ts.
PR14986.

llvm-svn: 173289
2013-01-23 20:41:05 +00:00
Richard Osborne 54e311821f Add instruction encodings / disassembly support for l6r instructions.
llvm-svn: 173288
2013-01-23 20:08:11 +00:00
Benjamin Kramer e4c46fec73 Revert "InstCombine: Clean up weird code that talks about a modulus that's long gone."
This causes crashes during the build of compiler-rt during selfhost. Add a
testcase for coverage.

llvm-svn: 173279
2013-01-23 17:52:29 +00:00
Bill Wendling 7c8f96a91b Add the heuristic to differentiate SSPStrong from SSPRequired.
The requirements of the strong heuristic are:

* A Protector is required for functions which contain an array, regardless of
  type or length.

* A Protector is required for functions which contain a structure/union which
  contains an array, regardless of type or length.  Note, there is no limit to
  the depth of nesting.

* A protector is required when the address of a local variable (i.e., stack
  based variable) is exposed. (E.g., such as through a local whose address is
  taken as part of the RHS of an assignment or a local whose address is taken as
  part of a function argument.)

llvm-svn: 173231
2013-01-23 06:43:53 +00:00
Bill Wendling d154e283f2 Add the IR attribute 'sspstrong'.
SSPStrong applies a heuristic to insert stack protectors in these situations:

* A Protector is required for functions which contain an array, regardless of
  type or length.

* A Protector is required for functions which contain a structure/union which
  contains an array, regardless of type or length.  Note, there is no limit to
  the depth of nesting.

* A protector is required when the address of a local variable (i.e., stack
  based variable) is exposed. (E.g., such as through a local whose address is
  taken as part of the RHS of an assignment or a local whose address is taken as
  part of a function argument.)

This patch implements the SSPString attribute to be equivalent to
SSPRequired. This will change in a subsequent patch.

llvm-svn: 173230
2013-01-23 06:41:41 +00:00
Nadav Rotem ab3e698ee9 Add support for reverse pointer induction variables. These are loops that contain pointers that count backwards.
For example, this is the hot loop in BZIP:

  do {
    m = *--p;
    *p = ( ... );
  } while (--n);

llvm-svn: 173219
2013-01-23 01:35:00 +00:00
Richard Osborne 1a06479f46 Add instruction encodings / disassembly support for u10 / lu10 instructions.
llvm-svn: 173204
2013-01-22 22:55:04 +00:00
Michael Liao 3dffc5e2b7 Fix an issue of pseudo atomic instruction DAG schedule
- Add list of physical registers clobbered in pseudo atomic insts
  Physical registers are clobbered when pseudo atomic instructions are
  expanded. Add them in clobber list to prevent DAG scheduler to
  mis-schedule them after these insns are declared side-effect free.
- Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com>

llvm-svn: 173200
2013-01-22 21:47:38 +00:00
Kevin Enderby 81c944cadb Add a warning when there is a macro defintion that has named parameters but
the body does not use them and it appears the body has positional parameters.

This can cause unexpected results as in the added test case.  As the darwin
version of gas(1) which only supported positional parameters, happened to
ignore the named parameters.  Now that we want to support both styles of
macros we issue a warning in this specific case.

rdar://12861644

llvm-svn: 173199
2013-01-22 21:44:53 +00:00
Akira Hatanaka 88c0ec826c [mips] Implement MipsRegisterInfo::getRegPressureLimit.
llvm-svn: 173197
2013-01-22 21:34:25 +00:00
Kevin Enderby 0017d8a469 Have the integrated assembler give an error if $1 is used as an identifier in
an expression.  Currently this bug causes the line to be ignored in a
release build and an assert in a debug build.

rdar://13062484

llvm-svn: 173195
2013-01-22 21:09:20 +00:00
Eli Bendersky 583860339b Add forgotten test case for the x32 commit
llvm-svn: 173181
2013-01-22 18:52:39 +00:00
Benjamin Kramer fee7d21ae7 X86: Make sure we account for the FMA4 register immediate value, otherwise rip-rel relocations will be off by one byte.
PR15040.

llvm-svn: 173176
2013-01-22 18:05:59 +00:00
Dmitri Gribenko 44ee2e7a23 Tests: rewrite 'opt ... %s' to 'opt ... < %s' so that opt does not emit a ModuleID
This is done to avoid odd test failures, like the one fixed in r171243.

llvm-svn: 173163
2013-01-22 14:39:21 +00:00
Evgeniy Stepanov c4415591ed [msan] Do not insert check on volatile store.
Volatile bitfields can cause valid stores of uninitialized bits.

llvm-svn: 173153
2013-01-22 12:30:52 +00:00
Michael Gottesman 469a465fa8 This test is only supposed to test that the objc-arc alias analysis
allows for gvn to perform certain optimizations. Thus the runline should
only contain -objc-arc-aa, not the full -objc-arc.

llvm-svn: 173126
2013-01-22 04:41:11 +00:00
Daniel Dunbar 34ea79f9a3 [MC/Mach-O] Load commands are supposed to 8-byte aligned on 64-bit.
llvm-svn: 173120
2013-01-22 03:42:49 +00:00
Andrew Trick 2d35fabc7d Remove target triple from an LSR test.
Manish already fixed this test to work with NoTTI.

llvm-svn: 173110
2013-01-22 00:57:16 +00:00
Paul Redmond 9d86a4a3b6 Transform (sub 0, (zext bool to A)) to (sext bool to A) and
(sub 0, (sext bool to A)) to (zext bool to A).

Patch by Muhammad Ahmad
Reviewed by Duncan Sands

llvm-svn: 173093
2013-01-21 21:57:20 +00:00
Richard Osborne 9d3ec06ef8 Add instruction encodings / disassembly support for u6 / lu6 instructions.
llvm-svn: 173086
2013-01-21 20:44:17 +00:00
Richard Osborne 6e58c6d86d Add instruction encoding / disassembly support for ru6 / lru6 instructions.
llvm-svn: 173085
2013-01-21 20:42:16 +00:00
Richard Osborne 4e69724869 Add instruction encodings / disassembly support for l2rus instructions.
llvm-svn: 172987
2013-01-20 18:51:15 +00:00
Richard Osborne 9fbf57b26c Add instruction encodings / disassembly support for l3r instructions.
llvm-svn: 172986
2013-01-20 18:37:49 +00:00
Richard Osborne f063fcee7a Add instruction encodings / disassembler support for 2rus instructions.
llvm-svn: 172985
2013-01-20 17:22:43 +00:00
Richard Osborne 3fb7395233 Add instruction encodings / disassembly support 3r instructions.
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.

llvm-svn: 172984
2013-01-20 17:18:47 +00:00
NAKAMURA Takumi 9439237063 llvm/test/CodeGen/X86/win_ftol2.ll: Add -cpu=generic to appease valgrind.
On valgrind the processor is reported;
  Host CPU: athlon-fx

llvm-svn: 172983
2013-01-20 15:40:02 +00:00
Nadav Rotem 9450fcfff1 Revert 172708.
The optimization handles esoteric cases but adds a lot of complexity both to the X86 backend and to other backends.
This optimization disables an important canonicalization of chains of SEXT nodes and makes SEXT and ZEXT asymmetrical.
Disabling the canonicalization of consecutive SEXT nodes into a single node disables other DAG optimizations that assume
that there is only one SEXT node. The AVX mask optimizations is one example. Additionally this optimization does not update the cost model.

llvm-svn: 172968
2013-01-20 08:35:56 +00:00