4751bb9edb
Remove the redundant TM member from X86DAGToDAGISel; replace it
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with an accessor method which simply casts the parent class
SelectionDAGISel's TM to the target-specific type.
llvm-svn: 72801
2009-06-03 20:20:00 +00:00
25bbcc67fa
Make the buildbot see green (to make it easier to spot the next person
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that puts a new warning in).
llvm-svn: 72797
2009-06-03 19:07:46 +00:00
11231d0c75
Remove unnecessary #includes.
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llvm-svn: 72782
2009-06-03 16:47:12 +00:00
215921ef94
Emit file directives correctly in case of a .bc is generated by llvm-ld after linking in several .bc files.
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llvm-svn: 72781
2009-06-03 16:27:49 +00:00
b011aa3a5e
FrameIndex could be used as a value (addressof (arg)) or as an address.
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Expand it exactly like GlobalAddress.
Fix some more crashes (InsertBranch() not being implemented) for compiling hitec libs.
llvm-svn: 72776
2009-06-03 15:31:12 +00:00
a53241a880
Fixed a bug in which signed comparisons were being used instead of unsigned comparisons.
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llvm-svn: 72771
2009-06-03 13:36:44 +00:00
c66ad73e35
Avoid a warning "'U' might be used uninitialized in
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this function" when using a not-too-smart compiler.
llvm-svn: 72768
2009-06-03 12:05:18 +00:00
ab0c710fae
Temporarily revert 72756 for now.
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llvm-svn: 72757
2009-06-03 07:40:47 +00:00
dfe6e689fd
Fold preceding / trailing base inc / dec into the single load / store as well.
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llvm-svn: 72756
2009-06-03 06:14:58 +00:00
fc262babc3
Revert r72734. The Darwin assembler doesn't support the static
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relocation model on x86-64. Higher level logic should override
the relocation model to PIC on x86_64-apple-darwin.
llvm-svn: 72746
2009-06-03 00:37:20 +00:00
448641d87c
On Darwin x86_64 small code model doesn't guarantee code address fits in 32-bit.
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llvm-svn: 72734
2009-06-02 20:09:31 +00:00
5234d3795f
Revert 72707 and 72709, for the moment.
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llvm-svn: 72712
2009-06-02 03:12:52 +00:00
7fde88cce8
Add missing file.
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llvm-svn: 72709
2009-06-01 23:48:58 +00:00
0b8ca79253
Make the implicit inputs and outputs of target-independent
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ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.
Most targets will still produce a Flag-setting target-dependent
version when selection is done. X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted. All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly. The
same can be done on other targets.
The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.
llvm-svn: 72707
2009-06-01 23:27:20 +00:00
ff10450680
Comment grammaro/clarification.
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llvm-svn: 72706
2009-06-01 23:13:42 +00:00
67f472feed
Trailing whitespace.
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llvm-svn: 72705
2009-06-01 23:12:52 +00:00
12694bd8ac
Implement review feedback. Make thumb2 'normal' subtarget feature
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llvm-svn: 72698
2009-06-01 20:00:48 +00:00
9fd794bebf
Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray
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llvm-svn: 72697
2009-06-01 19:57:37 +00:00
2afc641e04
Do not emit "generic" CPU string. This fixes PR4291.
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llvm-svn: 72696
2009-06-01 19:03:17 +00:00
c1c2c68945
Fix a grammaro and clarify a comment.
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llvm-svn: 72668
2009-05-31 17:52:18 +00:00
a194c3a69e
First patch in the direction of splitting MachineCodeEmitter in two subclasses:
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JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray
llvm-svn: 72631
2009-05-30 20:51:52 +00:00
7142ad75a1
(i64 (zext (srl GR32 8))) -> movzbl AH is not safe since srl 8 only clear the top 8 bits.
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llvm-svn: 72618
2009-05-30 08:43:27 +00:00
09f17a8479
Untabification.
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llvm-svn: 72604
2009-05-30 01:09:53 +00:00
b6f4538683
Add placeholder for thumb2 stuff
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llvm-svn: 72593
2009-05-29 23:41:08 +00:00
716e688fca
More h-registers tricks: folding zext nodes.
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llvm-svn: 72558
2009-05-29 01:44:43 +00:00
2e09bd3d34
The MONITOR and MWAIT instructions have insufficient information for
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decoding. Essentially, they both map to the same column in the "opcode
extensions for one- and two-byte opcodes" table in the x86 manual. The RawFrm
complicates decoding this.
Instead, use opcode 0x01, prefix 0x01, and form MRM1r. Then have the code
emitter special case these, a la [SML]FENCE.
llvm-svn: 72556
2009-05-28 23:40:46 +00:00
cc3ae1f2ff
Fix MOVMSKPDrr encoding.
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llvm-svn: 72535
2009-05-28 18:55:28 +00:00
60618fe4ac
Fix PSIGND encoding bug. Patch by Sean Callanan.
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llvm-svn: 72534
2009-05-28 18:48:53 +00:00
ae028d48be
Emit debug info for locals with proper scope.
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llvm-svn: 72531
2009-05-28 18:24:11 +00:00
fc4707a331
Mark the branch insns correctly.
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llvm-svn: 72529
2009-05-28 17:32:56 +00:00
335311c67a
Fixing problems that got exposed after the refactoring of LegalizeDAG done in 72447.
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llvm-svn: 72521
2009-05-28 06:59:57 +00:00
5806e18ce1
Return the operand rather than a null SDValue when the given SELECT_CC
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is actually legal. Part of LegalizeDAG cleanups.
llvm-svn: 72513
2009-05-28 04:31:08 +00:00
97021ae319
This patch brings the list of attributes in CPPBackend.cpp up to date with the
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list in Attributes.h. It also reorders the CPPBackend list to match so that
it's easier to see that it's complete.
llvm-svn: 72510
2009-05-28 03:16:17 +00:00
0feb0e6071
"The instructions MMX_PSADBWrm and MMX_PSADBWrr have opcode 0b11100000 (e0), but
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the Intel manual (screenshot) says it should be 0b11110110 (f6). The existing
encoding causes a disassembly conflict with MMX_PAVGBrm, which really should be
0f e0."
Patch by Sean Callanan!
llvm-svn: 72508
2009-05-28 02:04:00 +00:00
a9cda8abf2
Added optimization that narrow load / op / store and the 'op' is a bit twiddling instruction and its second operand is an immediate. If bits that are touched by 'op' can be done with a narrower instruction, reduce the width of the load and store as well. This happens a lot with bitfield manipulation code.
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e.g.
orl $65536, 8(%rax)
=>
orb $1, 10(%rax)
Since narrowing is not always a win, e.g. i32 -> i16 is a loss on x86, dag combiner consults with the target before performing the optimization.
llvm-svn: 72507
2009-05-28 00:35:15 +00:00
a56159b7e9
Ger rid of some dead code.
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llvm-svn: 72494
2009-05-27 20:39:00 +00:00
4db1631a43
Fix sfence jit encoding. Patch by Sean Callanan.
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llvm-svn: 72488
2009-05-27 18:38:01 +00:00
a72a505a80
Added support for fround, fextend and FP_TO_SINT
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llvm-svn: 72483
2009-05-27 17:23:44 +00:00
acb851a8c0
Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and
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FP_TO_XINT. Necessary for some cleanups I'm working on. Updated
from the previous version (r72431) to fix a bug and make some things a
bit clearer.
llvm-svn: 72445
2009-05-27 00:47:34 +00:00
d96b117872
Back out r72431, it is causing a number of compilation crashes with clang.
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llvm-svn: 72436
2009-05-26 21:27:02 +00:00
96180b5387
Update CPU capabilities for AMD machines
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- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10
New processor names match those used by gcc.
Patch by Paul Redmond!
llvm-svn: 72434
2009-05-26 21:04:35 +00:00
8c7bff96ed
Don't abuse the quirky behavior of LegalizeDAG for XINT_TO_FP and
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FP_TO_XINT. Necessary for some cleanups I'm working on.
llvm-svn: 72431
2009-05-26 19:18:56 +00:00
9b65031add
add some late optimizations that GCC does. It thinks these are a win
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even on Core2, not just AMD processors which was a surprise to me.
llvm-svn: 72396
2009-05-25 20:28:19 +00:00
9a3f3a5c3d
fix typo
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llvm-svn: 72395
2009-05-25 19:51:07 +00:00
be31b7b534
we should eventually add -march=atom and the new atom movbe instruction.
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llvm-svn: 72387
2009-05-25 16:34:44 +00:00
9c6ab1a34d
Make the PPC backend use a legal type for the operands to the BUILD_VECTOR
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nodes it generates.
llvm-svn: 72356
2009-05-24 02:03:36 +00:00
2199ed399f
Make the X86 backend mark EXTRACT_SUBVECTOR as Expand, at least for the
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moment.
llvm-svn: 72350
2009-05-23 22:44:52 +00:00
0b91cc4260
Add ARMv7 architecture, Cortex processors and different FPU modes handling.
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llvm-svn: 72337
2009-05-23 19:51:43 +00:00
fa6f1eea36
Emit ARM Build Attributes
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llvm-svn: 72336
2009-05-23 19:51:20 +00:00
08bf4c0f5a
Propagate CPU string out of SubtargetFeatures
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llvm-svn: 72335
2009-05-23 19:50:50 +00:00
Dan Gohman